From patchwork Fri Aug 30 04:15:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuquan Wang X-Patchwork-Id: 13784214 Received: from zg8tmtyylji0my4xnjqumte4.icoremail.net (zg8tmtyylji0my4xnjqumte4.icoremail.net [162.243.164.118]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B9C4613D60E for ; Fri, 30 Aug 2024 04:16:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=162.243.164.118 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724991394; cv=none; b=e6br8dgE1wd4EfzYM1gqjUIcxrwgH5cR0l7AVgHdZADNf+QTENcAiM+x5CRkBnDwtxv8jGnCU73c5xcrg8VEzJEtLbeQN7uFy80bdCUKkVkypG7CjOBb/3SjW9oNKsVk8fMTs7rheOFm2v2Higgjrj3xZ6X9GsTx3ZAIW+BqkA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724991394; c=relaxed/simple; bh=mRT4Bo4OwlPLuexu9oqtuiVpLuSMbh5UXKSycw6ayL0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uyeQNZGg9FODgYL6lDqpuDpBMSGyq8jdTgPxLLRbQuLuaam1sJl8a7xcae8iZJxPudoSpTuYyw1CHKEu4f06kLc+SnkfYpS9rip7ZpIDq6pqlw0qBu9RKO3uqfjYgg/1eo8lUfSDUsjg8imQ1+hb8USck0EF7+VFxJ9EtY1pF0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=phytium.com.cn; spf=pass smtp.mailfrom=phytium.com.cn; arc=none smtp.client-ip=162.243.164.118 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=phytium.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=phytium.com.cn Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwCnqSGXR9Fmob+CAg--.18550S2; Fri, 30 Aug 2024 12:16:23 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwC34bGOR9FmmakpAA--.16568S4; Fri, 30 Aug 2024 12:16:21 +0800 (CST) From: Yuquan Wang To: Jonathan.Cameron@Huawei.com, quic_llindhol@quicinc.com, peter.maydell@linaro.org, marcin.juszkiewicz@linaro.org Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, qemu-arm@nongnu.org, chenbaozi@phytium.com.cn, wangyinfeng@phytium.com.cn, shuyiqi@phytium.com.cn, Yuquan Wang Subject: [RFC PATCH 1/2] hw/arm/sbsa-ref: Enable CXL Host Bridge by pxb-cxl Date: Fri, 30 Aug 2024 12:15:56 +0800 Message-Id: <20240830041557.600607-2-wangyuquan1236@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240830041557.600607-1-wangyuquan1236@phytium.com.cn> References: <20240830041557.600607-1-wangyuquan1236@phytium.com.cn> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: AQAAfwC34bGOR9FmmakpAA--.16568S4 X-CM-SenderInfo: 5zdqw5pxtxt0arstlqxsk13x1xpou0fpof0/1tbiAQANAWbQ2MkCWwAAsz Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=wangyuquan 1236@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoWxXr48Jr1UGFy5KFWrJFyrZwb_yoWrXFyUpF 45ur95CrW8GF17ArZ3Z347GF45Wayvkayjyry7Cr9YyF17Gr1Fq3ykK3WUKa47JFWDt34j 9FZxZr1fWr17AaUanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU The memory layout places 1M space for 16 host bridge register regions in the sbsa-ref memmap. In addition, this creates a default pxb-cxl (bus_nr=0xfe) bridge with one cxl-rp on sbsa-ref. Signed-off-by: Yuquan Wang --- hw/arm/sbsa-ref.c | 54 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 3 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index ae37a92301..dc924d181e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -41,7 +41,10 @@ #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" #include "hw/loader.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/qdev-properties.h" #include "hw/usb.h" #include "hw/usb/xhci.h" @@ -52,6 +55,8 @@ #include "qom/object.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) @@ -94,6 +99,7 @@ enum { SBSA_SECURE_MEM, SBSA_AHCI, SBSA_XHCI, + SBSA_CXL_HOST, }; struct SBSAMachineState { @@ -105,6 +111,9 @@ struct SBSAMachineState { int psci_conduit; DeviceState *gic; PFlashCFI01 *flash[2]; + CXLState cxl_devices_state; + PCIBus *bus; + PCIBus *cxlbus; }; #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") @@ -132,6 +141,8 @@ static const MemMapEntry sbsa_ref_memmap[] = { /* Space here reserved for more SMMUs */ [SBSA_AHCI] = { 0x60100000, 0x00010000 }, [SBSA_XHCI] = { 0x60110000, 0x00010000 }, + /* 1M CXL Host Bridge Registers space (64KiB * 16) */ + [SBSA_CXL_HOST] = { 0x60120000, 0x00100000 }, /* Space here reserved for other devices */ [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, /* 32-bit address PCIE MMIO space */ @@ -631,6 +642,26 @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) } } +static void create_pxb_cxl(SBSAMachineState *sms) +{ + CXLHost *host; + PCIHostState *cxl; + + sms->cxl_devices_state.is_enabled = true; + + DeviceState *qdev; + qdev = qdev_new(TYPE_PXB_CXL_DEV); + qdev_prop_set_uint32(qdev, "bus_nr", 0xfe); + + PCIDevice *dev = PCI_DEVICE(qdev); + pci_realize_and_unref(dev, sms->bus, &error_fatal); + + host = PXB_CXL_DEV(dev)->cxl_host_bridge; + cxl = PCI_HOST_BRIDGE(host); + sms->cxlbus = cxl->bus; + pci_create_simple(sms->cxlbus, -1, "cxl-rp"); +} + static void create_pcie(SBSAMachineState *sms) { hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; @@ -682,12 +713,25 @@ static void create_pcie(SBSAMachineState *sms) } pci = PCI_HOST_BRIDGE(dev); + sms->bus = pci->bus; + + pci_init_nic_devices(sms->bus, mc->default_nic); - pci_init_nic_devices(pci->bus, mc->default_nic); + pci_create_simple(sms->bus, -1, "bochs-display"); - pci_create_simple(pci->bus, -1, "bochs-display"); + create_smmu(sms, sms->bus); - create_smmu(sms, pci->bus); + create_pxb_cxl(sms); +} + +static void create_cxl_host_reg_region(SBSAMachineState *sms) +{ + MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *mr = &sms->cxl_devices_state.host_mr; + + memory_region_init(mr, OBJECT(sms), "cxl_host_reg", + sbsa_ref_memmap[SBSA_CXL_HOST].size); + memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_CXL_HOST].base, mr); } static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) @@ -823,6 +867,10 @@ static void sbsa_ref_init(MachineState *machine) create_pcie(sms); + create_cxl_host_reg_region(sms); + + cxl_hook_up_pxb_registers(sms->bus, &sms->cxl_devices_state, &error_fatal); + create_secure_ec(secure_sysmem); sms->bootinfo.ram_size = machine->ram_size; From patchwork Fri Aug 30 04:15:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuquan Wang X-Patchwork-Id: 13784215 Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net (zg8tmja5ljk3lje4ms43mwaa.icoremail.net [209.97.181.73]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36408146D69 for ; Fri, 30 Aug 2024 04:16:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.97.181.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724991394; cv=none; b=W/9tBTuMWhH0BybkJlVookLY5B9+N60WnJXdoD2LjZOEBuJLpkf081G4aYqWRzlNiFdzpSw7H4CmFf+uPgX254rcTXEHbMBcnbwy5XNYeC/KgMyoiwMp6sSX1bF3/H9b7KWvOZGle5/0Voj0O1vFn0M4p9hF2TfQD1zUEmgA6A8= ARC-Message-Signature: i=1; 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Fri, 30 Aug 2024 12:16:23 +0800 (CST) From: Yuquan Wang To: Jonathan.Cameron@Huawei.com, quic_llindhol@quicinc.com, peter.maydell@linaro.org, marcin.juszkiewicz@linaro.org Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, qemu-arm@nongnu.org, chenbaozi@phytium.com.cn, wangyinfeng@phytium.com.cn, shuyiqi@phytium.com.cn, Yuquan Wang Subject: [RFC PATCH 2/2] hw/arm/sbsa-ref: Support CXL Fixed Memory Window Date: Fri, 30 Aug 2024 12:15:57 +0800 Message-Id: <20240830041557.600607-3-wangyuquan1236@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240830041557.600607-1-wangyuquan1236@phytium.com.cn> References: <20240830041557.600607-1-wangyuquan1236@phytium.com.cn> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: AQAAfwC34bGOR9FmmakpAA--.16568S5 X-CM-SenderInfo: 5zdqw5pxtxt0arstlqxsk13x1xpou0fpof0/1tbiAQANAWbQ2MkCXQAAs1 Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=wangyuquan 1236@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoW3AryrWr17Zw4ftw17Cw4xXrb_yoW3CF45pF s8uw43Wr48GFWvvrs2qayDJF15urWkCayjkrZrCrs29F17Kr18Xr4DKayYyFyUJrWDKry8 Z3WxZr1Fva15Zw7anT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU In order to provide CFMWs on sbsa-ref, this extends 1TB space from the hole above RAM Memory [SBSA_MEM] for CXL Fixed Memory Window. 0xA0000000000 is chosen as the base address of this space because of 3 reasons: 1) It is more suitable to choose a static address instead of that implementation in virt, since a dynamic address space layout of sbsa-ref is not appropriate for its original purpose as a reference platform. 2) The Hotplug Memory address range should in the range of maximum addressable range of sbsa-ref platform(0x10000000000-0x80ffffffffff). It is satisfied the requirements of memory hotplug in linux kernel. 3) The start pfn of CFMW should exceed the reserved_pfn_range for onlined numa node. Based on 'cxl_fmws_link_targets', this adds a new function 'sbsa_cxl_fmws_link_targets' for binding cfmws.target with the default pxb-cxl-bus on sbsa-ref. In addition, this also adds 'create_cxl_fixed_window_region' which based on 'machine_set_cfmw' to support creating a static cfmw region on sbsa-ref. Thus, to run sbsa-ref with a cxl device could use: qemu-system-aarch64 \ -machine sbsa-ref \ -cpu cortex-a57 \ -smp 4 \ -m 4G \ -object memory-backend-ram,size=2G,id=mem0 \ -numa node,nodeid=0,cpus=0-1,memdev=mem0 \ -object memory-backend-ram,size=2G,id=mem1 \ -numa node,nodeid=1,cpus=2-3,memdev=mem1 \ -object memory-backend-file,id=mem2,mem-path=/tmp/mem2,size=256M,share=true \ -device cxl-type3,bus=cxl.0,volatile-memdev=mem2,id=cxl-mem1 \ -hda ubuntu.ext4 \ -pflash SBSA_FLASH0.fd \ -pflash SBSA_FLASH1.fd \ I'm not sure if the new space layout would bring a series of bad influence, this patch is here to hopefully some comments to guide me! Signed-off-by: Yuquan Wang --- hw/arm/sbsa-ref.c | 73 +++++++++++++++++++++++++++++ hw/cxl/cxl-host-stubs.c | 1 + hw/cxl/cxl-host.c | 2 +- hw/pci-bridge/pci_expander_bridge.c | 1 - include/hw/cxl/cxl_host.h | 1 + include/hw/pci/pci_bridge.h | 1 + 6 files changed, 77 insertions(+), 2 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index dc924d181e..b10865920e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -100,6 +100,7 @@ enum { SBSA_AHCI, SBSA_XHCI, SBSA_CXL_HOST, + SBSA_CXL_FIXED_WINDOW, }; struct SBSAMachineState { @@ -152,6 +153,8 @@ static const MemMapEntry sbsa_ref_memmap[] = { /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, + /* 1TB CXL FIXED WINDOW space */ + [SBSA_CXL_FIXED_WINDOW] = { 0xA0000000000ULL, 0x10000000000ULL }, }; static const int sbsa_ref_irqmap[] = { @@ -734,6 +737,72 @@ static void create_cxl_host_reg_region(SBSAMachineState *sms) memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_CXL_HOST].base, mr); } +static void create_cxl_fixed_window_region(SBSAMachineState *sms, MemoryRegion *mem) +{ + char cxl_host[] = "pxb-cxl-bus.0"; + CXLFixedMemoryWindowOptionsList *list; + hwaddr base, end; + GList *it; + strList host_target = { NULL, cxl_host }; + CXLFixedMemoryWindowOptions sbsa_ref_cfmwoptions = { + .size = 1 * TiB, + .has_interleave_granularity = false, + .targets = &host_target, + }; + CXLFixedMemoryWindowOptionsList sbsa_ref_cfmwlist = { NULL, &sbsa_ref_cfmwoptions }; + + for (list = &sbsa_ref_cfmwlist; list; list = list->next) { + cxl_fixed_memory_window_config(&sms->cxl_devices_state, list->value, &error_fatal); + } + + base = sbsa_ref_memmap[SBSA_CXL_FIXED_WINDOW].base; + end = base + sbsa_ref_memmap[SBSA_CXL_FIXED_WINDOW].size; + + for (it = sms->cxl_devices_state.fixed_windows; it; it = it->next) { + CXLFixedWindow *fw = it->data; + if (base + fw->size > end) { + error_report("CFMWS does not fit under PA limit"); + exit(EXIT_FAILURE); + } + + fw->base = base; + memory_region_init_io(&fw->mr, OBJECT(sms), &cfmws_ops, fw, + "cxl-fixed-memory-region", fw->size); + + memory_region_add_subregion(mem, fw->base, &fw->mr); + base += fw->size; + } +} + +static void sbsa_cxl_fmws_link_targets(SBSAMachineState *sms, + CXLState *cxl_state, Error **errp) +{ + PXBCXLDev *pxb = PXB_CXL_DEV(pci_bridge_get_device(sms->cxlbus)); + if (cxl_state && cxl_state->fixed_windows) { + GList *it; + + for (it = cxl_state->fixed_windows; it; it = it->next) { + CXLFixedWindow *fw = it->data; + int i; + + for (i = 0; i < fw->num_targets; i++) { + Object *o; + bool ambig; + + o = object_resolve_path_type(fw->targets[i], + TYPE_PXB_CXL_BUS, + &ambig); + if (!o) { + error_setg(errp, "Could not resolve CXLFM target %s", + fw->targets[i]); + return; + } + fw->target_hbs[i] = pxb; + } + } + } +} + static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const SBSAMachineState *board = container_of(binfo, SBSAMachineState, @@ -869,8 +938,12 @@ static void sbsa_ref_init(MachineState *machine) create_cxl_host_reg_region(sms); + create_cxl_fixed_window_region(sms, sysmem); + cxl_hook_up_pxb_registers(sms->bus, &sms->cxl_devices_state, &error_fatal); + sbsa_cxl_fmws_link_targets(sms, &sms->cxl_devices_state, &error_fatal); + create_secure_ec(secure_sysmem); sms->bootinfo.ram_size = machine->ram_size; diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c index cae4afcdde..d523be24a2 100644 --- a/hw/cxl/cxl-host-stubs.c +++ b/hw/cxl/cxl-host-stubs.c @@ -11,5 +11,6 @@ void cxl_fmws_link_targets(CXLState *stat, Error **errp) {}; void cxl_machine_init(Object *obj, CXLState *state) {}; void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp) {}; +void cxl_fixed_memory_window_config(CXLState *cxl_state, CXLFixedMemoryWindowOptions *object, Error **errp) {}; const MemoryRegionOps cfmws_ops; diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index e9f2543c43..d408c7db15 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -22,7 +22,7 @@ #include "hw/pci/pcie_port.h" #include "hw/pci-bridge/pci_expander_bridge.h" -static void cxl_fixed_memory_window_config(CXLState *cxl_state, +void cxl_fixed_memory_window_config(CXLState *cxl_state, CXLFixedMemoryWindowOptions *object, Error **errp) { diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 0411ad31ea..f5431443b9 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -38,7 +38,6 @@ DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS, DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS, TYPE_PXB_PCIE_BUS) -#define TYPE_PXB_CXL_BUS "pxb-cxl-bus" DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS, TYPE_PXB_CXL_BUS) diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h index c9bc9c7c50..5fbf5a9347 100644 --- a/include/hw/cxl/cxl_host.h +++ b/include/hw/cxl/cxl_host.h @@ -16,6 +16,7 @@ void cxl_machine_init(Object *obj, CXLState *state); void cxl_fmws_link_targets(CXLState *stat, Error **errp); void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp); +void cxl_fixed_memory_window_config(CXLState *cxl_state, CXLFixedMemoryWindowOptions *object, Error **errp); extern const MemoryRegionOps cfmws_ops; diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index 5cd452115a..5456e24883 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -102,6 +102,7 @@ typedef struct PXBPCIEDev { PXBDev parent_obj; } PXBPCIEDev; +#define TYPE_PXB_CXL_BUS "pxb-cxl-bus" #define TYPE_PXB_DEV "pxb" OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV)