From patchwork Sat Aug 31 07:18:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13785958 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C6F01D12E6; Sat, 31 Aug 2024 07:19:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725088751; cv=none; b=kZwnHDf8N8J6l4NZeCunVs+Om5+CW/fxdb+FZs73YiOCF+/jF82Wbve8H+8lyUgNz7iv7COvvPYMbvHYMYskHwA6f/hovzHt/yoywqLUVbHknf3BvWulW3yr6tknE1FNvYWRK2ZYOTBW/Rr587F2mf5kkgSs75PFPH6hD0zkq6M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725088751; c=relaxed/simple; bh=FZvzmN2QmkFMKRZRjjhpM9mGeFi/KjKH6wH2YnfODb0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pM2Axe3iyjD3Son2bYwF9GheOez0P4nLipzyor4YdmF4chGBeCw5NDJWp3/XVG/GS5ML11KIEQkdTaNqQAGEYT6KyzGBMhRwqhhW+XxBr8NkjVSk6xJgIMhnPj47iEAxqWVzh6KOpDzyqYBsiXUe6VVcHoUS5e58u/Yct9vgKnk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OV+5M4BZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OV+5M4BZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 37329C4CEC0; Sat, 31 Aug 2024 07:19:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725088750; bh=FZvzmN2QmkFMKRZRjjhpM9mGeFi/KjKH6wH2YnfODb0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=OV+5M4BZU21KzagrraQ6xVHLG2SmRQsqOvq3zC7UXIlqZKJW/JfcX0yOR8/4ulTme yPcVt0xc3qn5mIxw7LNx73DoD7eE2Ahp+5oOohmwlxGwvU+pWjPYujqqAHZsatdyOX adJ1bImYmdLYeQe0ihJtLUdix+Bo53K4trJQQmoo679AQiEjsXzWSqid8QZVPc87+f 8e4jCsLJ76FeWXSwKIJFurvRb67JLn8bF4wnXDJCnx/OYqkAwZs0W484jCfUOdOILw kwizjH4JEeupYv7MyKs4YOjzpN6LxaBvacrf/8quYippw2EFtJD2/f0fGeVq7qcm58 YtssG7AVznQ0Q== From: Lorenzo Bianconi Date: Sat, 31 Aug 2024 09:18:43 +0200 Subject: [PATCH 1/7] dt-bindings: clock: airoha: update reg mapping for EN7581 SoC. Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240831-clk-en7581-syscon-v1-1-5c2683541068@kernel.org> References: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> In-Reply-To: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 clk-en7523 driver for EN7581 SoC is mapping all the scu memory region while it is configuring the chip-scu one via a syscon. Update the reg mapping definition for this device. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not public yet. Signed-off-by: Lorenzo Bianconi --- .../devicetree/bindings/clock/airoha,en7523-scu.yaml | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index 84353fd09428..ca426c328535 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -34,8 +34,8 @@ properties: - airoha,en7581-scu reg: - minItems: 2 - maxItems: 4 + minItems: 1 + maxItems: 2 "#clock-cells": description: @@ -75,9 +75,6 @@ allOf: reg: items: - description: scu base address - - description: misc scu base address - - description: reset base address - - description: pb scu base address additionalProperties: false @@ -98,10 +95,7 @@ examples: scuclk: clock-controller@1fa20000 { compatible = "airoha,en7581-scu"; - reg = <0x0 0x1fa20000 0x0 0x400>, - <0x0 0x1fb00000 0x0 0x90>, - <0x0 0x1fb00830 0x0 0x8>, - <0x0 0x1fbe3400 0x0 0xfc>; + reg = <0x0 0x1fb00000 0x0 0x970>; #clock-cells = <1>; #reset-cells = <1>; }; From patchwork Sat Aug 31 07:18:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13785959 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4EE516DEBB; Sat, 31 Aug 2024 07:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725088753; cv=none; b=Zwk6FT9pgNZi9Whcr0JiRNicGDuinl5ARXMQSx/GfQZm8p0TWhqBe2yp+oITcuP8w8jTh8SCt7sMnhg3oGL+pYma9qV2/fTAW2ON/5Nwc6Lr2XhVAyJYG4unoqKhVZB+KRkru4zw1JlQiuCb2NoDkpmTBvWMGK6o2FDkRek4urQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725088753; c=relaxed/simple; bh=WN8qnYso/OqQzZPqMv9ygjMnLiv6+Y8d2xbdKSe1W/Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Aiyp2TIg2u9o6Rg4cSrim3o+30ynmRWpndMQ+/kBG8K8hmSW2iyPPf+GkB1z3qaSAn7QzR2PzQDbbQveuukUb58XnDbGNiSkTNx9JlZmUItb2IooANjanXe2smsKIYAo5CfVKzTnPrWatqgry3whGy0yJ9IHZdjONZOPvt4XK4M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=t6PXy+Ra; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="t6PXy+Ra" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F2A7C4CEC0; Sat, 31 Aug 2024 07:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725088753; bh=WN8qnYso/OqQzZPqMv9ygjMnLiv6+Y8d2xbdKSe1W/Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=t6PXy+RaWEXj3ftmXfbGo7QdQn0lTK+GhJ9CETel+/4gQaT/7yoEhzpyPXH49LqKU UzVJtuHIcLRvaV8EgC0RsX5y0+ME+ze6+P4K7Kb9yZd4YMS5cuT43lc9ls9CX8VDXW uI2InafjZg676bqlrtaqAoerOTEwinzcd7aTPK/F4M9O29KmMEagbqgiEG5YDzfNd2 QvpDzpiOPT/asSbzn2ZsNWbvxbzp8t8pEbSgXyf4PiWO5L6Yux7qbuspGQ/6+sUtzC fZFXxhfXKAj2uCzZuF57F/Zre/8RX16NfIYFpPX4tZUT7MbEB4bKSgZHbABi4zb4Mf UM9D93iYshvgQ== From: Lorenzo Bianconi Date: Sat, 31 Aug 2024 09:18:44 +0200 Subject: [PATCH 2/7] clk: en7523: set REG_PCIE*_{MEM,MEM_MASK} via syscon Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240831-clk-en7581-syscon-v1-2-5c2683541068@kernel.org> References: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> In-Reply-To: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 REG_PCIE*_MEM and REG_PCIE*_MEM_MASK memory regions (PBUS_CSR) are not part of the scu block on the EN7581 SoC, so configure them via a dedicated syscon node. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not public yet. Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 22fbea61c3dc..2bc1bf4afbed 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -3,8 +3,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -415,25 +417,25 @@ static void en7581_pci_disable(struct clk_hw *hw) static int en7581_clk_hw_init(struct platform_device *pdev, void __iomem *np_base) { - void __iomem *pb_base; + struct regmap *map; u32 val; - pb_base = devm_platform_ioremap_resource(pdev, 3); - if (IS_ERR(pb_base)) - return PTR_ERR(pb_base); - val = readl(np_base + REG_NP_SCU_SSTR); val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); writel(val, np_base + REG_NP_SCU_SSTR); val = readl(np_base + REG_NP_SCU_PCIC); writel(val | 3, np_base + REG_NP_SCU_PCIC); - writel(0x20000000, pb_base + REG_PCIE0_MEM); - writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK); - writel(0x24000000, pb_base + REG_PCIE1_MEM); - writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK); - writel(0x28000000, pb_base + REG_PCIE2_MEM); - writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK); + map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr"); + if (IS_ERR(map)) + return PTR_ERR(map); + + regmap_write(map, REG_PCIE0_MEM, 0x20000000); + regmap_write(map, REG_PCIE0_MEM_MASK, 0xfc000000); + regmap_write(map, REG_PCIE1_MEM, 0x24000000); + regmap_write(map, REG_PCIE1_MEM_MASK, 0xfc000000); + regmap_write(map, REG_PCIE2_MEM, 0x28000000); + regmap_write(map, REG_PCIE2_MEM_MASK, 0xfc000000); return 0; } From patchwork Sat Aug 31 07:18:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13785960 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADCD91662E4; Sat, 31 Aug 2024 07:19:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725088756; cv=none; b=T4pAGTxyTCI/tR9svdKFKOLjJ/Jm0xu3DRHk5Z9Pq1nsuFM85FQAlSgCzHUXwcbxJbfAnQWZNuj6ofHzSG8WGjUugg5qT+xFbSVzPRpHZxgIHqy5Q94TA4Jm8yqQAdQkI3Q0UOhcpZTusB0VoRco9cWWSHA4AbCiuGFrzi5Uk1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725088756; c=relaxed/simple; bh=wxirsGQfghx8sEXgTMK+2xTQCHoa8BxdA/oLCL1aN0s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CyiYXCm9TZRP4WKLNMEeEq7H/PkkZvImlKp+muQ1h6cP2LPvb/2PxlITweweYiBIvugsKsnbePVEm4D/nnkqu69AnN7MZwmQhxE+N8Ec7FEyLFg1L6lWmFCrFjhpduBmkxp4nVnDXMjj7GVFw6LB3p216/1+RI8F6loDTqZJ4cU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jX1Azl5l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jX1Azl5l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D7AE0C4CEC0; Sat, 31 Aug 2024 07:19:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725088756; bh=wxirsGQfghx8sEXgTMK+2xTQCHoa8BxdA/oLCL1aN0s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jX1Azl5lP4/FwYU9pqvlKFNenySIHMvYdRfDza99ppPYMg3egRdlKqJ0c3DcfNPB6 TWN3/LknTyL29O4MDnJQzHc+Zy1e2rCX3pahqK4bYIsv0gWneGCy0TppI8EWaafCfk pHIBlQ5GLNVpR62DH07AyHBXEcxOr6tSgLxxzd4jumwVqTQvd7IGuCmbTBMiPZZ5bU lCMNlOEOhZzC5QeC6sl1a7b2sZJ64MZvWF9XG/ROVU3g/+NUJmBHby9gvvtaMbGTLM dMvmYXkaTwnLX2He9LLXITwL4EnoFC/vWg7fqio4qVHubQx/g4AnXDjs6QA+f2QjxC iJqKjbQ1Y0SwA== From: Lorenzo Bianconi Date: Sat, 31 Aug 2024 09:18:45 +0200 Subject: [PATCH 3/7] clk: en7523: move clock_register in hw_init callback Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240831-clk-en7581-syscon-v1-3-5c2683541068@kernel.org> References: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> In-Reply-To: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 Move en7523_register_clocks routine in hw_init callback. Introduce en7523_clk_hw_init callback for EN7523 SoC. This is a preliminary patch to differentiate IO mapped region between EN7523 and EN7581 SoCs in order to access chip-scu IO region <0x1fa20000 0x384> on EN7581 SoC as syscon device since it contains miscellaneous registers needed by multiple devices (clock, pinctrl ..). Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 106 +++++++++++++++++++++++++++-------------------- 1 file changed, 62 insertions(+), 44 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 2bc1bf4afbed..78bcb0ce77a5 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -86,7 +86,8 @@ struct en_clk_soc_data { const u16 *idx_map; u16 idx_map_nr; } reset; - int (*hw_init)(struct platform_device *pdev, void __iomem *np_base); + int (*hw_init)(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data); }; static const u32 gsw_base[] = { 400000000, 500000000 }; @@ -414,32 +415,6 @@ static void en7581_pci_disable(struct clk_hw *hw) usleep_range(1000, 2000); } -static int en7581_clk_hw_init(struct platform_device *pdev, - void __iomem *np_base) -{ - struct regmap *map; - u32 val; - - val = readl(np_base + REG_NP_SCU_SSTR); - val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); - writel(val, np_base + REG_NP_SCU_SSTR); - val = readl(np_base + REG_NP_SCU_PCIC); - writel(val | 3, np_base + REG_NP_SCU_PCIC); - - map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr"); - if (IS_ERR(map)) - return PTR_ERR(map); - - regmap_write(map, REG_PCIE0_MEM, 0x20000000); - regmap_write(map, REG_PCIE0_MEM_MASK, 0xfc000000); - regmap_write(map, REG_PCIE1_MEM, 0x24000000); - regmap_write(map, REG_PCIE1_MEM_MASK, 0xfc000000); - regmap_write(map, REG_PCIE2_MEM, 0x28000000); - regmap_write(map, REG_PCIE2_MEM_MASK, 0xfc000000); - - return 0; -} - static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, void __iomem *base, void __iomem *np_base) { @@ -469,6 +444,61 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->num = EN7523_NUM_CLOCKS; } +static int en7523_clk_hw_init(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data) +{ + void __iomem *base, *np_base; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(np_base)) + return PTR_ERR(np_base); + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + return 0; +} + +static int en7581_clk_hw_init(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data) +{ + void __iomem *base, *np_base; + struct regmap *map; + u32 val; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + np_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(np_base)) + return PTR_ERR(np_base); + + en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + + val = readl(np_base + REG_NP_SCU_SSTR); + val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); + writel(val, np_base + REG_NP_SCU_SSTR); + val = readl(np_base + REG_NP_SCU_PCIC); + writel(val | 3, np_base + REG_NP_SCU_PCIC); + + map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr"); + if (IS_ERR(map)) + return PTR_ERR(map); + + regmap_write(map, REG_PCIE0_MEM, 0x20000000); + regmap_write(map, REG_PCIE0_MEM_MASK, 0xfc000000); + regmap_write(map, REG_PCIE1_MEM, 0x24000000); + regmap_write(map, REG_PCIE1_MEM_MASK, 0xfc000000); + regmap_write(map, REG_PCIE2_MEM, 0x28000000); + regmap_write(map, REG_PCIE2_MEM_MASK, 0xfc000000); + + return 0; +} + static int en7523_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -563,31 +593,18 @@ static int en7523_clk_probe(struct platform_device *pdev) struct device_node *node = pdev->dev.of_node; const struct en_clk_soc_data *soc_data; struct clk_hw_onecell_data *clk_data; - void __iomem *base, *np_base; int r; - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - np_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(np_base)) - return PTR_ERR(np_base); - - soc_data = device_get_match_data(&pdev->dev); - if (soc_data->hw_init) { - r = soc_data->hw_init(pdev, np_base); - if (r) - return r; - } - clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, EN7523_NUM_CLOCKS), GFP_KERNEL); if (!clk_data) return -ENOMEM; - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + soc_data = device_get_match_data(&pdev->dev); + r = soc_data->hw_init(pdev, clk_data); + if (r) + return r; r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -610,6 +627,7 @@ static const struct en_clk_soc_data en7523_data = { .prepare = en7523_pci_prepare, .unprepare = en7523_pci_unprepare, }, + .hw_init = en7523_clk_hw_init, }; static const struct en_clk_soc_data en7581_data = { From patchwork Sat Aug 31 07:18:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13785961 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D4D616A92E; Sat, 31 Aug 2024 07:19:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sat, 31 Aug 2024 07:19:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725088759; bh=YHZJ988FcV1F6uBvvv9QjPxEj5imGTvAZwqhOOIKZMw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oq3xgBpJHlfBfoOOTOeVBPqjHOlKNrS7FVMEgo3Vz1dXy47NgTCxqpkGs1G5Lw4wN uaWTYp6t6ONiteLlQXhVbDH4FdDQ0hh3qv0TPgYXCxbJPIozBPWvJ7bJZ68FjCs07J d6LCaNYx52miNtfp3K0t3WBOD6f6pv6B040/0HE0KqDc3PqblXfdHz6LUp+Mq7Bq53 wx7ca/UWvA6TGLatelI9HsuiSMTvrB0UNW2U19P588SQ2Q0TgPT5tkDqvYSE0bgmUT mq6AFct3R09R/ycDb3F3tL1Lu0/BS8nz56H6iogzgR52J4mXb7k2FGbwCaCS8glwCR KpZihWPlEqZbQ== From: Lorenzo Bianconi Date: Sat, 31 Aug 2024 09:18:46 +0200 Subject: [PATCH 4/7] clk: en7523: introduce chip_scu regmap Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240831-clk-en7581-syscon-v1-4-5c2683541068@kernel.org> References: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> In-Reply-To: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 Introduce chip_scu regmap pointer since EN7581 SoC will access chip-scu memory area through a syscon node. Remove first memory region mapping for EN7581 SoC. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not public yet. Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 75 +++++++++++++++++++++++++++++++++++------------- 1 file changed, 55 insertions(+), 20 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 78bcb0ce77a5..d0f936ec6bb2 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -255,15 +255,11 @@ static const u16 en7581_rst_map[] = { [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, }; -static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) +static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; - u32 val; - if (!desc->base_bits) return desc->base_value; - val = readl(base + desc->base_reg); val >>= desc->base_shift; val &= (1 << desc->base_bits) - 1; @@ -273,16 +269,11 @@ static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) return desc->base_values[val]; } -static u32 en7523_get_div(void __iomem *base, int i) +static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; - u32 reg, val; - if (!desc->div_bits) return 1; - reg = desc->div_reg ? desc->div_reg : desc->base_reg; - val = readl(base + reg); val >>= desc->div_shift; val &= (1 << desc->div_bits) - 1; @@ -424,9 +415,12 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg; + u32 val = readl(base + desc->base_reg); - rate = en7523_get_base_rate(base, i); - rate /= en7523_get_div(base, i); + rate = en7523_get_base_rate(desc, val); + val = readl(base + reg); + rate /= en7523_get_div(desc, val); hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); if (IS_ERR(hw)) { @@ -462,22 +456,63 @@ static int en7523_clk_hw_init(struct platform_device *pdev, return 0; } +static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, + struct regmap *map, void __iomem *base) +{ + struct clk_hw *hw; + u32 rate; + int i; + + for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { + const struct en_clk_desc *desc = &en7523_base_clks[i]; + u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; + + if (regmap_read(map, desc->base_reg, &val)) { + pr_err("Failed reading fixed clk rate %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + rate = en7523_get_base_rate(desc, val); + + if (regmap_read(map, reg, &val)) { + pr_err("Failed reading fixed clk div %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + rate /= en7523_get_div(desc, val); + + hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate); + if (IS_ERR(hw)) { + pr_err("Failed to register clk %s: %ld\n", + desc->name, PTR_ERR(hw)); + continue; + } + + clk_data->hws[desc->id] = hw; + } + + hw = en7523_register_pcie_clk(dev, base); + clk_data->hws[EN7523_CLK_PCIE] = hw; + + clk_data->num = EN7523_NUM_CLOCKS; +} + static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { - void __iomem *base, *np_base; + void __iomem *np_base; struct regmap *map; u32 val; - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); + map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); - np_base = devm_platform_ioremap_resource(pdev, 1); + np_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(np_base)) return PTR_ERR(np_base); - en7523_register_clocks(&pdev->dev, clk_data, base, np_base); + en7581_register_clocks(&pdev->dev, clk_data, map, np_base); val = readl(np_base + REG_NP_SCU_SSTR); val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); @@ -565,7 +600,7 @@ static int en7523_reset_register(struct platform_device *pdev, if (!soc_data->reset.idx_map_nr) return 0; - base = devm_platform_ioremap_resource(pdev, 2); + base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(base)) return PTR_ERR(base); From patchwork Sat Aug 31 07:18:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13785962 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8F0D16A94A; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bcPj41u3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 37197C4CEC0; Sat, 31 Aug 2024 07:19:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725088761; bh=mZL17vTSI21fYGe1Av6s7TLeSZDfb8YawTBbr0HBHhI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=bcPj41u3QSyfWeqJkfGD1hRF2ZAZQ3efZZE+7tvYBrIMQmvum/tK7aUPZC9m2upKh wu1pINB3emr1YxBGd/j2NDWHjwjFcslw+jpz/U78XyraE47kz/+gLhDY8CB7LJlrtT Ops/IMVaeHj+DVVBTZwgL1Q13z5tDsd7dV+bC5EvJfHQiHZIAqyb5xCtHSE91HgC/H pqF/yHPTV07KQfd0otv/eJj9G8JT1rCayen5GMEH1D62DwJlhKPmWYdeXazKLAzPxy L7AiQhegq1I86jz2xiimCRtpdIQzGVbWNh5RqezFKlCfuBTIZnTmmXT41jCsitjy90 GF55Lnfr5kx7w== From: Lorenzo Bianconi Date: Sat, 31 Aug 2024 09:18:47 +0200 Subject: [PATCH 5/7] clk: en7523: fix estimation of fixed rate for EN7581 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240831-clk-en7581-syscon-v1-5-5c2683541068@kernel.org> References: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> In-Reply-To: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 Introduce en7581_base_clks array in order to define per-SoC fixed-rate clock parameters and fix wrong parameters for emi, npu and crypto EN7581 clocks Fixes: 66bc47326ce2 ("clk: en7523: Add EN7581 support") Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 105 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index d0f936ec6bb2..f9ebbdb70393 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -43,6 +43,7 @@ #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) +#define REG_CRYPTO_CLKSRC2 0x20c #define REG_RST_CTRL2 0x00 #define REG_RST_CTRL1 0x04 @@ -95,6 +96,10 @@ static const u32 emi_base[] = { 333000000, 400000000 }; static const u32 bus_base[] = { 500000000, 540000000 }; static const u32 slic_base[] = { 100000000, 3125000 }; static const u32 npu_base[] = { 333000000, 400000000, 500000000 }; +/* EN7581 */ +static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 }; +static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 }; +static const u32 crypto_base[] = { 540000000, 480000000 }; static const struct en_clk_desc en7523_base_clks[] = { { @@ -192,6 +197,102 @@ static const struct en_clk_desc en7523_base_clks[] = { } }; +static const struct en_clk_desc en7581_base_clks[] = { + { + .id = EN7523_CLK_GSW, + .name = "gsw", + + .base_reg = REG_GSW_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = gsw_base, + .n_base_values = ARRAY_SIZE(gsw_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_EMI, + .name = "emi", + + .base_reg = REG_EMI_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = emi7581_base, + .n_base_values = ARRAY_SIZE(emi7581_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_BUS, + .name = "bus", + + .base_reg = REG_BUS_CLK_DIV_SEL, + .base_bits = 1, + .base_shift = 8, + .base_values = bus_base, + .n_base_values = ARRAY_SIZE(bus_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_SLIC, + .name = "slic", + + .base_reg = REG_SPI_CLK_FREQ_SEL, + .base_bits = 1, + .base_shift = 0, + .base_values = slic_base, + .n_base_values = ARRAY_SIZE(slic_base), + + .div_reg = REG_SPI_CLK_DIV_SEL, + .div_bits = 5, + .div_shift = 24, + .div_val0 = 20, + .div_step = 2, + }, { + .id = EN7523_CLK_SPI, + .name = "spi", + + .base_reg = REG_SPI_CLK_DIV_SEL, + + .base_value = 400000000, + + .div_bits = 5, + .div_shift = 8, + .div_val0 = 40, + .div_step = 2, + }, { + .id = EN7523_CLK_NPU, + .name = "npu", + + .base_reg = REG_NPU_CLK_DIV_SEL, + .base_bits = 2, + .base_shift = 8, + .base_values = npu7581_base, + .n_base_values = ARRAY_SIZE(npu7581_base), + + .div_bits = 3, + .div_shift = 0, + .div_step = 1, + .div_offset = 1, + }, { + .id = EN7523_CLK_CRYPTO, + .name = "crypto", + + .base_reg = REG_CRYPTO_CLKSRC2, + .base_bits = 1, + .base_shift = 0, + .base_values = crypto_base, + .n_base_values = ARRAY_SIZE(crypto_base), + } +}; + static const u16 en7581_rst_ofs[] = { REG_RST_CTRL2, REG_RST_CTRL1, @@ -463,8 +564,8 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat u32 rate; int i; - for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) { - const struct en_clk_desc *desc = &en7523_base_clks[i]; + for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) { + const struct en_clk_desc *desc = &en7581_base_clks[i]; u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg; if (regmap_read(map, desc->base_reg, &val)) { From patchwork Sat Aug 31 07:18:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13785963 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FBAC16A94A; Sat, 31 Aug 2024 07:19:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sat, 31 Aug 2024 07:19:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725088764; bh=oSjqHUxHhFTQQpQZ02qWUHUFeOJxU9IRo9BaPP4vfX4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VPl6khfH5sMkPxxAB4w2JwPe57q7ELcmArGHeLjeuRHNnkgkBJLc+2WUnb61SziJX lX6kTW+tvArqVapvCDxsalwGezw8j2dyOUdYa5QtB3hVrfWHn43YTFIg/AZrmsVylS w6LlZ/8ffXa+l7z583NDFZT9kWlxEedZN5FUBPDy7xUBS3tzK4GPLJBm9pcnAX9vMg Bumi4K3qexg7E3SMuf/wsv/mhY4VubST3ZHsrvZA5a7Amz071BvvFQZ20JpGu6H26h lUq/ynPCIABpzA0zk0aXryaOAlMsJIqSSNGSWogytiwsvpbwE7OYxxQbWOmltlIUd+ KCgvFvuD3rlow== From: Lorenzo Bianconi Date: Sat, 31 Aug 2024 09:18:48 +0200 Subject: [PATCH 6/7] clk: en7523: move en7581_reset_register() in en7581_clk_hw_init() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240831-clk-en7581-syscon-v1-6-5c2683541068@kernel.org> References: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> In-Reply-To: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 Move en7581_reset_register routine in en7581_clk_hw_init() since reset feature is supported just by EN7581 SoC. Get rid of reset struct in en_clk_soc_data data struct. Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 115 ++++++++++++++++++----------------------------- 1 file changed, 44 insertions(+), 71 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index f9ebbdb70393..946c85a89102 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -82,11 +82,6 @@ struct en_rst_data { struct en_clk_soc_data { const struct clk_ops pcie_ops; - struct { - const u16 *bank_ofs; - const u16 *idx_map; - u16 idx_map_nr; - } reset; int (*hw_init)(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data); }; @@ -598,43 +593,6 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat clk_data->num = EN7523_NUM_CLOCKS; } -static int en7581_clk_hw_init(struct platform_device *pdev, - struct clk_hw_onecell_data *clk_data) -{ - void __iomem *np_base; - struct regmap *map; - u32 val; - - map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); - if (IS_ERR(map)) - return PTR_ERR(map); - - np_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(np_base)) - return PTR_ERR(np_base); - - en7581_register_clocks(&pdev->dev, clk_data, map, np_base); - - val = readl(np_base + REG_NP_SCU_SSTR); - val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); - writel(val, np_base + REG_NP_SCU_SSTR); - val = readl(np_base + REG_NP_SCU_PCIC); - writel(val | 3, np_base + REG_NP_SCU_PCIC); - - map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr"); - if (IS_ERR(map)) - return PTR_ERR(map); - - regmap_write(map, REG_PCIE0_MEM, 0x20000000); - regmap_write(map, REG_PCIE0_MEM_MASK, 0xfc000000); - regmap_write(map, REG_PCIE1_MEM, 0x24000000); - regmap_write(map, REG_PCIE1_MEM_MASK, 0xfc000000); - regmap_write(map, REG_PCIE2_MEM, 0x28000000); - regmap_write(map, REG_PCIE2_MEM_MASK, 0xfc000000); - - return 0; -} - static int en7523_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -684,23 +642,18 @@ static int en7523_reset_xlate(struct reset_controller_dev *rcdev, return rst_data->idx_map[reset_spec->args[0]]; } -static const struct reset_control_ops en7523_reset_ops = { +static const struct reset_control_ops en7581_reset_ops = { .assert = en7523_reset_assert, .deassert = en7523_reset_deassert, .status = en7523_reset_status, }; -static int en7523_reset_register(struct platform_device *pdev, - const struct en_clk_soc_data *soc_data) +static int en7581_reset_register(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct en_rst_data *rst_data; void __iomem *base; - /* no reset lines available */ - if (!soc_data->reset.idx_map_nr) - return 0; - base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(base)) return PTR_ERR(base); @@ -709,13 +662,13 @@ static int en7523_reset_register(struct platform_device *pdev, if (!rst_data) return -ENOMEM; - rst_data->bank_ofs = soc_data->reset.bank_ofs; - rst_data->idx_map = soc_data->reset.idx_map; + rst_data->bank_ofs = en7581_rst_ofs; + rst_data->idx_map = en7581_rst_map; rst_data->base = base; - rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr; + rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map); rst_data->rcdev.of_xlate = en7523_reset_xlate; - rst_data->rcdev.ops = &en7523_reset_ops; + rst_data->rcdev.ops = &en7581_reset_ops; rst_data->rcdev.of_node = dev->of_node; rst_data->rcdev.of_reset_n_cells = 1; rst_data->rcdev.owner = THIS_MODULE; @@ -724,6 +677,43 @@ static int en7523_reset_register(struct platform_device *pdev, return devm_reset_controller_register(dev, &rst_data->rcdev); } +static int en7581_clk_hw_init(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data) +{ + void __iomem *np_base; + struct regmap *map; + u32 val; + + map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); + + np_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(np_base)) + return PTR_ERR(np_base); + + en7581_register_clocks(&pdev->dev, clk_data, map, np_base); + + val = readl(np_base + REG_NP_SCU_SSTR); + val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); + writel(val, np_base + REG_NP_SCU_SSTR); + val = readl(np_base + REG_NP_SCU_PCIC); + writel(val | 3, np_base + REG_NP_SCU_PCIC); + + map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr"); + if (IS_ERR(map)) + return PTR_ERR(map); + + regmap_write(map, REG_PCIE0_MEM, 0x20000000); + regmap_write(map, REG_PCIE0_MEM_MASK, 0xfc000000); + regmap_write(map, REG_PCIE1_MEM, 0x24000000); + regmap_write(map, REG_PCIE1_MEM_MASK, 0xfc000000); + regmap_write(map, REG_PCIE2_MEM, 0x28000000); + regmap_write(map, REG_PCIE2_MEM_MASK, 0xfc000000); + + return en7581_reset_register(pdev); +} + static int en7523_clk_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; @@ -742,19 +732,7 @@ static int en7523_clk_probe(struct platform_device *pdev) if (r) return r; - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n", - pdev->name); - - r = en7523_reset_register(pdev, soc_data); - if (r) { - of_clk_del_provider(node); - return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n", - pdev->name); - } - - return 0; + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } static const struct en_clk_soc_data en7523_data = { @@ -772,11 +750,6 @@ static const struct en_clk_soc_data en7581_data = { .enable = en7581_pci_enable, .disable = en7581_pci_disable, }, - .reset = { - .bank_ofs = en7581_rst_ofs, - .idx_map = en7581_rst_map, - .idx_map_nr = ARRAY_SIZE(en7581_rst_map), - }, .hw_init = en7581_clk_hw_init, }; From patchwork Sat Aug 31 07:18:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13785964 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6404F16A94A; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QOW/VliC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 986F7C4CEC0; Sat, 31 Aug 2024 07:19:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725088767; bh=PKPRn9PaxXEJstoqEqCr0zTFtympizdBdFTWRSAtK0w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=QOW/VliCP4unaYsOhpeHByO519dUR2jOOGjw6XWHrehuHJhPK/CX3hOmRdgpirmP2 eHzXGfnB0le0nxZcfY9mjcnHayHJp4s/TllpdmYVCeGRVU8arjWYTREECL7N3hMK/G TeSe41c4NIwfg3M3AdOfXoe2EuSPrr3h16hRNrEIbCYt92tMSQ4eX5CswlwHVb9tpI nn8y1moVdWZyzz7k0XBZVsk8K/CEKeqxFi+i35HpMl2bYVRG8qMODHqP4qV0gqnCTa AJcq8zQtTaJ50QXic4p6MsemOJOrJCbIQiwzQXTPBbwdKaplnzXZsf22DD4jNl5v6V MrxtNS/6opWrg== From: Lorenzo Bianconi Date: Sat, 31 Aug 2024 09:18:49 +0200 Subject: [PATCH 7/7] clk: en7523: map io region in a single block Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240831-clk-en7581-syscon-v1-7-5c2683541068@kernel.org> References: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> In-Reply-To: <20240831-clk-en7581-syscon-v1-0-5c2683541068@kernel.org> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , Philipp Zabel Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com, ansuelsmth@gmail.com, Lorenzo Bianconi X-Mailer: b4 0.14.1 Map all clock-controller memory region in a single block. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not public yet. Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 946c85a89102..c62120c1d26e 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -45,8 +45,8 @@ #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) #define REG_CRYPTO_CLKSRC2 0x20c -#define REG_RST_CTRL2 0x00 -#define REG_RST_CTRL1 0x04 +#define REG_RST_CTRL2 0x830 +#define REG_RST_CTRL1 0x834 struct en_clk_desc { int id; @@ -648,15 +648,9 @@ static const struct reset_control_ops en7581_reset_ops = { .status = en7523_reset_status, }; -static int en7581_reset_register(struct platform_device *pdev) +static int en7581_reset_register(struct device *dev, void __iomem *base) { - struct device *dev = &pdev->dev; struct en_rst_data *rst_data; - void __iomem *base; - - base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(base)) - return PTR_ERR(base); rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL); if (!rst_data) @@ -680,25 +674,25 @@ static int en7581_reset_register(struct platform_device *pdev) static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { - void __iomem *np_base; struct regmap *map; + void __iomem *base; u32 val; map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) return PTR_ERR(map); - np_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(np_base)) - return PTR_ERR(np_base); + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); - en7581_register_clocks(&pdev->dev, clk_data, map, np_base); + en7581_register_clocks(&pdev->dev, clk_data, map, base); - val = readl(np_base + REG_NP_SCU_SSTR); + val = readl(base + REG_NP_SCU_SSTR); val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK); - writel(val, np_base + REG_NP_SCU_SSTR); - val = readl(np_base + REG_NP_SCU_PCIC); - writel(val | 3, np_base + REG_NP_SCU_PCIC); + writel(val, base + REG_NP_SCU_SSTR); + val = readl(base + REG_NP_SCU_PCIC); + writel(val | 3, base + REG_NP_SCU_PCIC); map = syscon_regmap_lookup_by_compatible("airoha,en7581-pbus-csr"); if (IS_ERR(map)) @@ -711,7 +705,7 @@ static int en7581_clk_hw_init(struct platform_device *pdev, regmap_write(map, REG_PCIE2_MEM, 0x28000000); regmap_write(map, REG_PCIE2_MEM_MASK, 0xfc000000); - return en7581_reset_register(pdev); + return en7581_reset_register(&pdev->dev, base); } static int en7523_clk_probe(struct platform_device *pdev)