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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?skSLcWMSXox1VEF4U3S97L80LlHS?= =?utf-8?q?RAFoWZlbOjlvI+XfR8Y14rDG8XUMo6Qdg0WwiyPWqLd5hNOcq1PFodNJbyb8mTKdT?= =?utf-8?q?I2xxF3LOCLterf/XcqZrNEK7EJ7t10U8cj7RPnBZYaOkdcs9zcRqNhjKenrVwel9k?= =?utf-8?q?QnwrLtJC0nylhaSt9UWufd+fzAtdnAalvaNgn4UJeTquxYIIDP3bos3iMQVIXdCMo?= =?utf-8?q?WyGSNJLG1irgmg1JP7oU6zmiy7DnJtEJQOw0Mh+yABZ7esBdcyUamjLns/hwDR/N6?= =?utf-8?q?jaSLVu+s6XoQXMr4mqnAWpqz4Dw3VZNGW8g8rka6q/FJRn+EiP1tH5CTJXNrZilXa?= =?utf-8?q?BmtTm9PEr2YXtVOcC+xkwFbLzaavhQgq0GAmIkjWCsjs933J8e6l4LjByTZoY6Eyi?= =?utf-8?q?cpkuN62f4bK/n6EQvfB8ENP1NYGFr2/fioUVPDrN8eth4McTN2UgAWUFjJJn64Naj?= =?utf-8?q?nLH6HRbVVqvlPK3GjoEFeCGUUOQRUIbjrHdrVS3QElQyJFMKEyO69pmIvsITOT38d?= =?utf-8?q?6/KqKPuvF5LuNaIiDvu7odxz7pDFXNd8udglk1IxDbxAjE+ndp28Tmt9m1t7ed3yT?= =?utf-8?q?GBU6hRSfmJaFJyp4UZJ6JM7iv/h5tIBDcpLkGuJRyrFyso19csGqFzN/rv3kcRIxV?= =?utf-8?q?ohsEN4x6CPaeXmrA9K0qiChlh7I2qi6zsHM4wKb+opnsa3WdJjJ0szK7dTKGYV1lI?= =?utf-8?q?qqpZPUBjqBJGXcNYGiDIRsuFUzTscGEwH9oGOqq/Ns6EljRWOYHrw49GxLEu7UfTt?= =?utf-8?q?GeGaXy5vzV+44GF4AGYzbeD1getYnz5URaJI9maTqPmNyO7UoiGlzDOBLHPrAarat?= =?utf-8?q?qwtDPbKzcuqkrT4V+cIL+T8jRPB3q+apKqUBC7CSC+yZhkKaHSoQatHpo3i5yrW+8?= =?utf-8?q?X5n/bLJ8yZ3TY8LnL7BjdpbG9k+OVCArQdU6ajQXNaHRNo+AuvDbUFaVnlD4VHrHy?= =?utf-8?q?ElFyO38JIXRd5fcX4FkarL187Gn619jhPVfTvPWn8tmAzXjd4fOqYKkCca3F7LOPB?= =?utf-8?q?v5b6Oq5yvDFtEeeL21rbV2lOpanMFYcC5D0mPgyIpo/wzY+NgSk3xxJqdG04f8MLL?= =?utf-8?q?OghQgyi4h4reDcq2MGJHJ9Ir+Kb/8z/9gNClJHOmqkbsxt1o9yc+xRwE2kDpQGFQg?= =?utf-8?q?VEM+SZpGN24sgefadgDMkKR0suTv0f8Tx3iNYMSiNPfw33C/z3WNajSIPaqfaL50B?= =?utf-8?q?xZsIzgFQvAK8dwV0swR0Z7VIzxvXr5UZIlbhfWJGY9rxD9lmpdliahYEHMNgc08iC?= =?utf-8?q?kZDGdPu6xYKWG1yLzhMosIQfZKOMurYofZHk/nX2ibrM8tKGKQUu15r6QihhdVtZi?= =?utf-8?q?v8QrFRbS1kFfvhzKpHOckOtOrDsOLLi1hhVG711KmHL6X1q0Nd67KdLI2RexFpHCr?= =?utf-8?q?Hsv6EhW4FF97EVaPWsrKh3bAPsHJvH5OHWVfZYx6ltr5UwBBfPSkkWUiY2+ObhHCc?= =?utf-8?q?M1bBLrvsqzaVyTUiC/nX9CXzUYosqObiJ8jaBTUX3x6WyQ8L/HzMl63wrnwFjuksb?= =?utf-8?q?jvubyJDOAqp/?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b40740cd-4d4a-4493-e1d6-08dccb377f03 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB8459.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2024 10:10:39.5772 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /8evhjGQKVYBNfkOYgPNebJ1GalN9lm17FAYrC3x1UuFTFm+ssOsQsyoHw+SduyB0XG5WaApt2TQ53K5DCFheA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8171 From: Peng Fan With 'max-rx-timeout-ms' property added in 'Documentation/devicetree/ indings/firmware/arm,scmi.yaml', set the value for i.MX95. NXP i.MX95 SCMI Firmware designation does not allow timeout, it will not recover if the Agents use timeout design. So set a large value (5000ms) here. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index ecdc6b7b5129..7880d3efbd7e 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -294,6 +294,8 @@ scmi { #address-cells = <1>; #size-cells = <0>; + max-rx-timeout-ms = <5000>; + scmi_devpd: protocol@11 { reg = <0x11>; #power-domain-cells = <1>; From patchwork Mon Sep 2 10:19:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13786993 Received: from AM0PR83CU005.outbound.protection.outlook.com (mail-westeuropeazon11010027.outbound.protection.outlook.com [52.101.69.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D29D613CF8E for ; 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Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 7880d3efbd7e..314a45e82c38 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -301,6 +301,10 @@ scmi_devpd: protocol@11 { #power-domain-cells = <1>; }; + scmi_sys_power: protocol@12 { + reg = <0x12>; + }; + scmi_perf: protocol@13 { reg = <0x13>; #power-domain-cells = <1>; @@ -320,6 +324,13 @@ scmi_iomuxc: protocol@19 { reg = <0x19>; }; + scmi_bbm: protocol@81 { + reg = <0x81>; + }; + + scmi_misc: protocol@84 { + reg = <0x84>; + }; }; }; From patchwork Mon Sep 2 10:19:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13786994 Received: from AM0PR83CU005.outbound.protection.outlook.com (mail-westeuropeazon11010027.outbound.protection.outlook.com [52.101.69.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00574143C77 for ; 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Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 314a45e82c38..2cba7a889030 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -347,13 +347,13 @@ a55-thermal { trips { cpu_alert0: trip0 { - temperature = <85000>; + temperature = <105000>; hysteresis = <2000>; type = "passive"; }; cpu_crit0: trip1 { - temperature = <95000>; + temperature = <125000>; hysteresis = <2000>; type = "critical"; }; From patchwork Mon Sep 2 10:19:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13786995 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011048.outbound.protection.outlook.com [52.101.70.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CF50184542 for ; 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This is to add the anamix temperature thermal zone and its cooling device. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 2cba7a889030..d031b9548aaf 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -372,6 +372,38 @@ map0 { }; }; }; + + ana-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 0>; + trips { + ana_alert: trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + ana_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&ana_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 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Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index d031b9548aaf..a7e411f1daa6 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -22,12 +22,27 @@ cpus { #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <10000>; + exit-latency-us = <7000>; + min-residency-us = <27000>; + wakeup-latency-us = <15000>; + }; + }; + A55_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX95_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -45,6 +60,7 @@ A55_1: cpu@100 { reg = <0x100>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX95_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -62,6 +78,7 @@ A55_2: cpu@200 { reg = <0x200>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX95_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -79,6 +96,7 @@ A55_3: cpu@300 { reg = <0x300>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX95_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -98,6 +116,7 @@ A55_4: cpu@400 { power-domain-names = "perf"; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; i-cache-size = <32768>; i-cache-line-size = <64>; i-cache-sets = <128>; @@ -115,6 +134,7 @@ A55_5: cpu@500 { power-domain-names = "perf"; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; 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Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 37a1d4ca1b20..5101cd171e09 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -8,6 +8,15 @@ #include #include "imx95.dtsi" +#define FALLING_EDGE 1 +#define RISING_EDGE 2 + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */ + / { model = "NXP i.MX95 19X19 board"; compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; @@ -357,6 +366,14 @@ &usdhc2 { status = "okay"; }; +&scmi_misc { + nxp,ctrl-ids = ; +}; + &wdog3 { fsl,ext-reset-output; status = "okay"; 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Since we are at here, also add the alias for all lpi2c and gpio nodes. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 69 +++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 5101cd171e09..64e9caf3089e 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -22,6 +22,19 @@ / { compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; @@ -241,6 +254,42 @@ i2c4_gpio_expander_21: gpio@21 { }; }; +&lpi2c5 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c5>; + status = "okay"; + + i2c5_pcal6408: i2c5-gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3p3v>; + }; +}; + +&lpi2c6 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c6>; + status = "okay"; + + i2c6_pcal6416: i2c6-gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416>; + vcc-supply = <®_3p3v>; + }; +}; + &lpi2c7 { clock-frequency = <1000000>; pinctrl-names = "default"; @@ -427,6 +476,20 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e >; }; + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = < + IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e + IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e + >; + }; + pinctrl_lpi2c7: lpi2c7grp { fsl,pins = < IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e @@ -446,6 +509,12 @@ IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e >; }; + pinctrl_pcal6416: pcal6416grp { + fsl,pins = < + IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e + >; + }; + pinctrl_pdm: pdmgrp { fsl,pins = < IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e