From patchwork Tue Sep 3 06:42:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13788099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A217CA101E for ; Tue, 3 Sep 2024 06:44:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9PJ4kSGhbNALUtIAkRdHQ5RGYk9lhTo8AhOyYnNiol8=; b=4X5gLYy8BzBuXmFaQ1NTMnaQcE aCfZj9XFfs0MA+tV5WN4K28j0DA3RCpOkzicNYBzkG4NICcggsybpIFDCskgpQzjan/AG1nIgoNWH Mo3NuNAh49P2yCKJkoODVbwmVr2PkKJ3eJVOFp630KDqHrQdp3RbkgZk/ShkAIwCUFdQWyiAIWApS IWd9409MUarkkh7aDUa2HCUhSl7U7lJtwuasdhDtfu8hgwQQd7vG6Dtij6DfvoMXdcAtw98urj0u6 WGKNfrp+SRZC8VHjRZpIj5SAxvLjGqPzJ8yP5rM7Va34i+nyJxGC6bz9UKn7N4mY/uZI3hrHMCyy7 fjiHFU2g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNGc-0000000GVaV-1q36; Tue, 03 Sep 2024 06:43:54 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNFX-0000000GVIG-0qwr for linux-arm-kernel@lists.infradead.org; Tue, 03 Sep 2024 06:42:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1725345766; x=1756881766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xw6HVneEx8JYTYqdGhN1CmrkEfyjnYCH2FyHmFQQEfw=; b=OgE2dq+7/cflwCizlKj1X5W8IuJsmMQDogZkNBOSesARaAdbyKBz6oMH GNOUD+rBnoXRxXdw/5UtdE/4Tr0YX0PwH/hj2GU6A773gnfDMw/fBn8TI YJymCtXBLJmEVSD5c8Qmt1YfezqqTnVpCb8MGfbgDDx6QtS+FO9A5FCvb vourMu8f+gCLi2KnJWS3LuPrcmlEJFHdV1jNbGjcf4eARjQSCZDqYx6XZ eesnAXxcWsT6NtTdItHLvxPdqcO7NEb5oR7GK8HtGRCk+57lzjRYMoQ+p i1sSSbS0Kg1Kcx9YrG3S/kHuJMOCvl3vP4kAX+wRs9ZO+o9bJXbTQia0V g==; X-CSE-ConnectionGUID: q+Zs7HZmS1O4vWTV7SMIVA== X-CSE-MsgGUID: 7aGjnVWPRx+gMFhVe7bJTg== X-IronPort-AV: E=Sophos;i="6.10,197,1719903600"; d="scan'208";a="31149999" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Sep 2024 23:42:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 2 Sep 2024 23:42:29 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 2 Sep 2024 23:42:25 -0700 From: Varshini Rajendran To: , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v7 01/12] dt-bindings: atmel-ssc: add microchip,sam9x7-ssc Date: Tue, 3 Sep 2024 12:12:25 +0530 Message-ID: <20240903064225.49313-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903063913.48307-1-varshini.rajendran@microchip.com> References: <20240903063913.48307-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_234247_327277_CCF867A1 X-CRM114-Status: UNSURE ( 8.37 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add microchip,sam9x7-ssc to DT bindings documentation. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt index f9fb412642fe..894875826de9 100644 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt @@ -2,6 +2,7 @@ Required properties: - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" + or "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc" - atmel,at91rm9200-ssc: support pdc transfer - atmel,at91sam9g45-ssc: support dma transfer - reg: Should contain SSC registers location and length From patchwork Tue Sep 3 06:42:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13788100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8244CD342F for ; Tue, 3 Sep 2024 06:44:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=oZcab64f4SrpxnBJxRsepIRA6guYuu1uZa5yKoJNYq0=; b=W05PBGK+0dqApWvAdSnkXrcj30 r5BJE2aaxRsBZhd9GMcwhcwrGMX+aVxN1o2R/Tf3hwfAA9nW+QWg+mwkhWWmGNpk5g6R/BLEcx2g9 4990ODdbIIg5NWgs4k2jwrYA0qMlxYgZhbki0KDhQRl/omRUNYEsabSwo/z0beGNgn1NN0tdWzB8R c+hPrhO0I9B8IPBCKJgtSOD/INCwR630uW4NJcfIYPDb4llYj7O5hN4OqPaZFDdAQ7qNSIINUuLsS jlmD/nKGWTsqQnJ6Btl5Ku7gourHKeEL0MjAtg3uZV+4abI7EOvm/XbN8sSYH748//Ph/e+S9S7nw v1Fk35ow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNHU-0000000GVri-1vHo; Tue, 03 Sep 2024 06:44:48 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNFY-0000000GVIG-2Z9t for linux-arm-kernel@lists.infradead.org; Tue, 03 Sep 2024 06:42:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1725345768; x=1756881768; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1VQXaqXdgqyQ5EmTPgLBYwyXYe+q+1C8SSYLlJq+imQ=; b=sGTlwTNAXZcI1pFFGQLR0oDjZHPPlxWWoq4A922Jm3aimArrl9MeJKyD FZFwmhq9B8pd/HGxsWgFQ0GEGdbF0MVB1Qa1jYgxE5oTzITfMODdZ2DmU hCBtGmKBzT/7sRluyxuio7dN3Eh2P6GtJAp1jtxBbQMBBrAjpc2JtUPu/ LWASUSJfhANxoyTMYnjCXEBneaDIRVxvVFcY/kPAO7Zs9RW3ptfik/bw0 cEkoji4nV8IV/y6raDn+R3JpRX+b5SLgXtHjtqfQsR4u/hI4uHFq4uFrd EKvEHJ+4ZCCpzxW5MELUFUN59zIOyIHM4J5J/K2YhzfrIhbT7ya1OXeEh g==; X-CSE-ConnectionGUID: q+Zs7HZmS1O4vWTV7SMIVA== X-CSE-MsgGUID: xgiV5pA/QhSBElE711G20g== X-IronPort-AV: E=Sophos;i="6.10,197,1719903600"; d="scan'208";a="31150000" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Sep 2024 23:42:46 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 2 Sep 2024 23:42:36 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 2 Sep 2024 23:42:33 -0700 From: Varshini Rajendran To: , , , , , , , , CC: Subject: [PATCH v7 02/12] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x7 compatible Date: Tue, 3 Sep 2024 12:12:33 +0530 Message-ID: <20240903064233.49366-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903063913.48307-1-varshini.rajendran@microchip.com> References: <20240903063913.48307-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_234248_735560_7D69331A X-CRM114-Status: UNSURE ( 9.80 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for sam9x7 device compatible with sama5d2 compatible as the fallback as the sam9x7 SoC uses the same tcb IP as the latter. Signed-off-by: Varshini Rajendran Reviewed-by: Rob Herring (Arm) --- Changes in v7: - Elaborated the commit message with justifications to the fallback. --- .../soc/microchip/atmel,at91rm9200-tcb.yaml | 20 ++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml index a46411149571..2c7275c4503b 100644 --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml @@ -15,13 +15,19 @@ description: | properties: compatible: - items: - - enum: - - atmel,at91rm9200-tcb - - atmel,at91sam9x5-tcb - - atmel,sama5d2-tcb - - const: simple-mfd - - const: syscon + oneOf: + - items: + - enum: + - atmel,at91rm9200-tcb + - atmel,at91sam9x5-tcb + - atmel,sama5d2-tcb + - const: simple-mfd + - const: syscon + - items: + - const: microchip,sam9x7-tcb + - const: atmel,sama5d2-tcb + - const: simple-mfd + - const: syscon reg: maxItems: 1 From patchwork Tue Sep 3 06:42:40 2024 Content-Type: text/plain; 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Mon, 2 Sep 2024 23:42:45 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: Subject: [PATCH v7 03/12] dt-bindings: interrupt-controller: Add support for sam9x7 aic Date: Tue, 3 Sep 2024 12:12:40 +0530 Message-ID: <20240903064240.49415-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903063913.48307-1-varshini.rajendran@microchip.com> References: <20240903063913.48307-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_234318_821295_578B1B98 X-CRM114-Status: GOOD ( 12.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the support added for the Advanced interrupt controller(AIC) chip in the sam9x7 SoC family. New compatible is introduced to capture the differences like the number of interrupts supported in the integration of the IP to that of the previous designs. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring (Arm) --- Changes in v7: - Elaborated the commit message by explaining the difference in IP. --- .../devicetree/bindings/interrupt-controller/atmel,aic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml index d4658fe3867c..d671ed884c9e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml @@ -23,6 +23,7 @@ properties: - atmel,sama5d3-aic - atmel,sama5d4-aic - microchip,sam9x60-aic + - microchip,sam9x7-aic reg: maxItems: 1 From patchwork Tue Sep 3 06:42:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13788101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCB47CA101E for ; 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d="scan'208";a="31877353" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Sep 2024 23:43:01 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 2 Sep 2024 23:42:55 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 2 Sep 2024 23:42:52 -0700 From: Varshini Rajendran To: , , , , , CC: , Hari Prasath Subject: [PATCH v7 04/12] irqchip/atmel-aic5: Add support for sam9x7 aic Date: Tue, 3 Sep 2024 12:12:52 +0530 Message-ID: <20240903064252.49530-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903063913.48307-1-varshini.rajendran@microchip.com> References: <20240903063913.48307-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_234302_540220_88004793 X-CRM114-Status: GOOD ( 11.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Hari Prasath Add support for the Advanced interrupt controller(AIC) chip in the sam9x7. Signed-off-by: Hari Prasath Signed-off-by: Varshini Rajendran Acked-by: Nicolas Ferre --- Changes in v7: - Removed the line break in the function. --- drivers/irqchip/irq-atmel-aic5.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index 145535bd7560..f9168efa4160 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -320,6 +320,7 @@ static const struct of_device_id aic5_irq_fixups[] __initconst = { { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup }, { .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup }, { .compatible = "microchip,sam9x60", .data = sam9x60_aic_irq_fixup }, + { .compatible = "microchip,sam9x7", .data = sam9x60_aic_irq_fixup }, { /* sentinel */ }, }; @@ -406,3 +407,11 @@ static int __init sam9x60_aic5_of_init(struct device_node *node, return aic5_of_init(node, parent, NR_SAM9X60_IRQS); } IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init); 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Mon, 2 Sep 2024 23:43:00 -0700 From: Varshini Rajendran To: , , , , , , CC: , Sebastian Reichel Subject: [PATCH v7 05/12] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7 Date: Tue, 3 Sep 2024 12:12:59 +0530 Message-ID: <20240903064259.49580-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903063913.48307-1-varshini.rajendran@microchip.com> References: <20240903063913.48307-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_234333_555187_D3F13471 X-CRM114-Status: GOOD ( 10.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use sam9x7 pmc's compatible to lookup for in the SHDWC driver. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c index 959ce0dbe91d..2121d7e74e12 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = { { .compatible = "atmel,sama5d2-pmc" }, { .compatible = "microchip,sam9x60-pmc" }, { .compatible = "microchip,sama7g5-pmc" }, + { .compatible = "microchip,sam9x7-pmc" }, { /* Sentinel. */ } }; From patchwork Tue Sep 3 06:43:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13788109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF91FCD342F for ; Tue, 3 Sep 2024 06:48:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+umsjfbcDDnJSe/sKrMBkZ+Pu5vTHtMMUn5GCJkPfYE=; b=OBJQVAfxHkpSt9iUskHpM1oJ06 V7Gb27eZx3Dpan0dgoY6MWzDtKL23NWnKOmRfsdq86jvhDLZzwgg5kcoSa4RjVtrO2GEs4WEzL9z8 p8u2vxP34/KlNN+teM+I30VC/qwsP5gU1cV1498hR/QRFYbvdPTokXkCktgIlMzj+9byxMT5WKcgP Hgbd25nTRnkDHLPdp9URPmOHJhJHgciDjy2sxQJCkVlZFVhkwGRuDI+aYZvW1pb0joHytgN7J6v4y xwCguAhy3r9n6VmiGbWlnev+MGZIprWSOHHGy+r/wqnY1uJWIoi8+QBU/d6VoJyQE7h+kFlQr3R/D GNkTxLjQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNL2-0000000GWkc-104t; Tue, 03 Sep 2024 06:48:28 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNGw-0000000GVgn-2G7b for linux-arm-kernel@lists.infradead.org; Tue, 03 Sep 2024 06:44:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1725345854; x=1756881854; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8i5Z2KfBYTZAJwGXyHoxcKMWI4cBoFSSa/Wp6ippfD0=; b=ieZoPfnanqyv4ZGKjSId9kBNnsd31u+PjafN/OLgWh0DKAzoGVNyaZlH 6twNRTrAQh68xaIvx6CevV1CGCfMNizjaJUcQKTaZHc6BV1j3gfMvt+Sz ed+XC+lEenLpvTLEZVLF3aMKN7rwYiDg8wxBtD97E20lR7ZNWTrJzMJZY zqBAnFdvo9JyVgXR5CUyfV1i81OhDV/U78GrYew1xCm4h+k3eQbyJQCkF kXR9AtDE4tc3N012qT4LS1b9JfdpYo+WsYrgNo9V/0QeI/2xEhbkaUDxz Q3zClc5c4MO9ZO0JflvZujxT5w1CIF7lOwE/pJBtZyVKqNOGziUKmCYfO Q==; X-CSE-ConnectionGUID: RQ/RpB+QRjexyFExAQsyWw== X-CSE-MsgGUID: TwEtkzdtSVaZum2++WtYDQ== X-IronPort-AV: E=Sophos;i="6.10,197,1719903600"; d="scan'208";a="31877401" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Sep 2024 23:44:13 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 2 Sep 2024 23:43:36 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 2 Sep 2024 23:43:32 -0700 From: Varshini Rajendran To: , , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v7 08/12] dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7 Date: Tue, 3 Sep 2024 12:13:32 +0530 Message-ID: <20240903064332.49751-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903063913.48307-1-varshini.rajendran@microchip.com> References: <20240903063913.48307-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_234414_673844_9A3563BC X-CRM114-Status: UNSURE ( 8.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add documentation for SAM9X7 reset controller. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Philipp Zabel --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 98465d26949e..c3b33bbc7319 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -26,6 +26,10 @@ properties: - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc + - items: + - enum: + - microchip,sam9x7-rstc + - const: microchip,sam9x60-rstc reg: minItems: 1 From patchwork Tue Sep 3 06:43:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13788110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D702CA101E for ; Tue, 3 Sep 2024 06:49:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IJIYpCEXzv1HLPuRoMBr3QOkW+ySH+Ar2xS07iRYG8Y=; b=YEKxg8/kuNxoQKHtBmZ4azFimJ sZ+BcNikVwWiKiRUmZATGmWlZCYmG5Q7XSViYWFNw/5ItceCyzbUDDhbyg7ns9sopILL892yGTqLM xzyYgpDlx13O+5N+yaqytI4X5vzP8t4GraKrjFzU48r09prpxKbiVub64ABa1WpPdGuvZcveKJCNW pxNKnF1057WhgtbWZ2S707R/YKfyOAXJcGmSAlRLz8/+jfZcg8lAV+HZZlQv2/8iMkB4tVKH59g51 FCEVPGHQT8HCVdA9Hk4MoVlFAThLSx2j1NrE2LrLi78wuBK4mNMdA4fO4oNT4uctTN8XaKt2iSFga RSTHCAVg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNLu-0000000GWqb-187s; Tue, 03 Sep 2024 06:49:22 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNGx-0000000GVgn-3zbU for linux-arm-kernel@lists.infradead.org; Tue, 03 Sep 2024 06:44:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1725345855; x=1756881855; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=flQEluk5hLljQfPymWhZA5C4pdYlqlYSYYtSaCbnjQ8=; b=b3SxDxphi/2Yzpa8ttoI5ozbQlhNOGi2aZTNIx+8RFpgHlKLcXpkIEht YtegvomFt8OG338UHSkjVZsXG0m0ZtQgvZECQAGQ8hpUAPr6z6i5OnYHX 2AqvEfPJEqnpVQtjJJMAf3Ro9M9IXDNJe5/d/yXyBKSFQq9QKuViYVLSW PSMJ6QFoCcZ1a3mMAVEinUtsZlsKGaSI2MlRyGQLqPTzUTItacFNahKbA guEgTkBTzTpYebMF/y99jxEjVQHEU2fKLXwiqyFNCYfp6Os83+GwnRut6 fvjX79aJxyZJlnUE/RbZbFAVkmAsbWr++jMn5J/rdne3yCGgZqkWZt7+K A==; X-CSE-ConnectionGUID: RQ/RpB+QRjexyFExAQsyWw== X-CSE-MsgGUID: OQXgAnCTTtOTHobobvMsnA== X-IronPort-AV: E=Sophos;i="6.10,197,1719903600"; d="scan'208";a="31877404" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Sep 2024 23:44:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 2 Sep 2024 23:43:45 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 2 Sep 2024 23:43:41 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: , Krzysztof Kozlowski , Sebastian Reichel Subject: [PATCH v7 09/12] dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7 Date: Tue, 3 Sep 2024 12:13:40 +0530 Message-ID: <20240903064340.49800-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903063913.48307-1-varshini.rajendran@microchip.com> References: <20240903063913.48307-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_234416_120206_A96E7C53 X-CRM114-Status: UNSURE ( 8.12 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add shutdown controller DT bindings. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Sebastian Reichel --- .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml index 8c58e12cdb60..0735ceb7c103 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -22,6 +22,9 @@ properties: - enum: - atmel,sama5d2-shdwc - microchip,sam9x60-shdwc + - items: + - const: microchip,sam9x7-shdwc + - const: microchip,sam9x60-shdwc reg: maxItems: 1 From patchwork Tue Sep 3 06:43:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13788113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E7C2CD342F for ; Tue, 3 Sep 2024 06:51:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=dhq/IkSm9+IkexkjRV8h5vEZmkA6ay0fznLCjoyIzYA=; b=z+MODxYqvS6aaOFFvq3mNUNq0w aqsvvVwq9/dph+DyF3ZUft7QaMIlFi6myQ5CPPCiPedd9nIXYdvfK15r0/KkNowChsTHv4X6VikF8 Zvf+Dv0yg02ohgF+q9h4eqBrGNXx0/pE6Z4b8/ev814a0Uew07nP92LLiNpQnZ7uos3QfJNoPBWTP O4wlnnAM3Ez/WjDHK9UjgEQKeep6IFd8DXuzOkr7mY0Fwfwh/U0Nlpq+HWtkTeiL8jO5o1gdEb/+x q7eN8E8FajVWsikv6mXVgEReR4rXJHopDTQeFKh+buJndptG4VHZRir0bB+VR+TL/7p4bA0mDfSfe Rbm7D0bA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNNe-0000000GXK1-37c0; Tue, 03 Sep 2024 06:51:10 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1slNHk-0000000GVxw-36mP for linux-arm-kernel@lists.infradead.org; Tue, 03 Sep 2024 06:45:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1725345904; x=1756881904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lckxbndzn5SzNLl/X33gP9uFz9Zap1w5LoofaOwQ5xs=; b=o9S/VYixcyVP/m79C8k6V4ultBeMPVgfHcibM0cmf/tHLCVBpn/zNa15 7aKXq20+f0VLHntU9RwQYgce2aHKtg1Uh75urRNmAVu5tUwEi+k7I2azP yuQ081hWMS/EKhqG+Be7Uv5ww+zdgNhNTYwqOrMsE7H3fdDQCt+4tmKqI 4XIKoPIraK+4GMFCPySvHFC1b59TGaOS/TQhPWVUIGtP8GoDtXN6pgHgp gdsl/Tth3Tbf2ag3V1yCASMo69clSbIz8aTJWPUQAwn7yvYNL/hblrV60 zrTaBEkcEfhtmG+tHSyCaD4uEq9UN6AFB0/xMLpG+/mqB6xm8ByGp2DfL A==; X-CSE-ConnectionGUID: It3XBgicRp6ZNrxOO7XUJA== X-CSE-MsgGUID: foXUXSFLRCi2m+eerstmgQ== X-IronPort-AV: E=Sophos;i="6.10,197,1719903600"; d="scan'208";a="31150080" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Sep 2024 23:45:03 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 2 Sep 2024 23:44:22 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 2 Sep 2024 23:44:19 -0700 From: Varshini Rajendran To: , , , , , , , , CC: Subject: [PATCH v7 10/12] ARM: dts: at91: sam9x7: add device tree for SoC Date: Tue, 3 Sep 2024 12:13:49 +0530 Message-ID: <20240903064349.49849-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903063913.48307-1-varshini.rajendran@microchip.com> References: <20240903063913.48307-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_234505_001625_D18E2421 X-CRM114-Status: GOOD ( 14.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device tree file for SAM9X7 SoC family. Co-developed-by: Nicolas Ferre Signed-off-by: Nicolas Ferre Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v7: - Enabled TCB node to add child nodes in the dts - Removed sfr node to add it later in a different series with the right binding documentation --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 1220 +++++++++++++++++++++++ 1 file changed, 1220 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi new file mode 100644 index 000000000000..beb1f34b38d3 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -0,0 +1,1220 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Microchip SAM9X7 SoC"; + compatible = "microchip,sam9x7"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + reg = <0>; + device_type = "cpu"; + }; + }; + + clocks { + slow_xtal: clock-slowxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + main_xtal: clock-mainxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + sram: sram@300000 { + compatible = "mmio-sram"; + reg = <0x300000 0x10000>; + ranges = <0 0x300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + sdmmc0: mmc@80000000 { + compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg = <0x80000000 0x300>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 12>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + sdmmc1: mmc@90000000 { + compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg = <0x90000000 0x300>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + }; + + apb { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + flx4: flexcom@f0000000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0000000 0x200>; + ranges = <0x0 0xf0000000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + status = "disabled"; + + uart4: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx5: flexcom@f0004000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0004000 0x200>; + ranges = <0x0 0xf0004000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + status = "disabled"; + + uart5: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c5: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + dma0: dma-controller@f0008000 { + compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma"; + reg = <0xf0008000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + ssc: ssc@f0010000 { + compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; + reg = <0xf0010000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "pclk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s: i2s@f001c000 { + compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; + reg = <0xf001c000 0x100>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; + clock-names = "pclk", "gclk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + flx11: flexcom@f0020000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0020000 0x200>; + ranges = <0x0 0xf0020000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + status = "disabled"; + + uart11: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + i2c11: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx12: flexcom@f0024000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf0024000 0x200>; + ranges = <0x0 0xf0024000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + status = "disabled"; + + uart12: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + i2c12: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + pit64b0: timer@f0028000 { + compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xf0028000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names = "pclk", "gclk"; + }; + + sha: crypto@f002c000 { + compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; + reg = <0xf002c000 0x100>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "sha_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names = "tx"; + }; + + trng: rng@f0030000 { + compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng"; + reg = <0xf0030000 0x100>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + status = "disabled"; + }; + + aes: crypto@f0034000 { + compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; + reg = <0xf0034000 0x100>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "aes_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>; + dma-names = "tx", "rx"; + }; + + tdes: crypto@f0038000 { + compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; + reg = <0xf0038000 0x100>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "tdes_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names = "tx", "rx"; + }; + + classd: sound@f003c000 { + compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd"; + reg = <0xf003c000 0x100>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; + clock-names = "pclk", "gclk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>; + dma-names = "tx"; + status = "disabled"; + }; + + pit64b1: timer@f0040000 { + compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xf0040000 0x100>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names = "pclk", "gclk"; + }; + + can0: can@f8000000 { + compatible = "bosch,m_can"; + reg = <0xf8000000 0x100>, <0x300000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>, + <68 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>; + assigned-clock-rates = <480000000>, <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "bosch,m_can"; + reg = <0xf8004000 0x100>, <0x300000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>, + <69 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>; + assigned-clock-rates = <480000000>, <40000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + tcb: timer@f8008000 { + compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon"; + reg = <0xf8008000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>; + clock-names = "t0_clk", "gclk", "slow_clk"; + }; + + flx6: flexcom@f8010000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8010000 0x200>; + ranges = <0x0 0xf8010000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + status = "disabled"; + + uart6: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx7: flexcom@f8014000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8014000 0x200>; + ranges = <0x0 0xf8014000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + status = "disabled"; + + uart7: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + i2c7: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx8: flexcom@f8018000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8018000 0x200>; + ranges = <0x0 0xf8018000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + status = "disabled"; + + uart8: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + i2c8: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx0: flexcom@f801c000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf801c000 0x200>; + ranges = <0x0 0xf801c000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + status = "disabled"; + + uart0: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi0: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx1: flexcom@f8020000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8020000 0x200>; + ranges = <0x0 0xf8020000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + status = "disabled"; + + uart1: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi1: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx2: flexcom@f8024000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8024000 0x200>; + ranges = <0x0 0xf8024000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + status = "disabled"; + + uart2: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx3: flexcom@f8028000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8028000 0x200>; + ranges = <0x0 0xf8028000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + status = "disabled"; + + uart3: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + gmac: ethernet@f802c000 { + compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem"; + reg = <0xf802c000 0x1000>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ + <60 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ + <61 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 2 */ + <62 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 3 */ + <63 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 4 */ + <64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; + clock-names = "hclk", "pclk", "tx_clk", "tsu_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 67>; + assigned-clock-rates = <266666666>; + status = "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible = "microchip,sam9x7-pwm", "microchip,sam9x60-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; + #pwm-cells = <3>; + status = "disabled"; + }; + + flx9: flexcom@f8040000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8040000 0x200>; + ranges = <0x0 0xf8040000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + status = "disabled"; + + uart9: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + i2c9: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + flx10: flexcom@f8044000 { + compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xf8044000 0x200>; + ranges = <0x0 0xf8044000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + status = "disabled"; + + uart10: serial@200 { + compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = ; + status = "disabled"; + }; + + i2c10: i2c@600 { + compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + matrix: matrix@ffffde00 { + compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon"; + reg = <0xffffde00 0x200>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x300>, <0xffffe600 0x100>; + }; + + mpddrc: mpddrc@ffffe800 { + compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; + reg = <0xffffe800 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names = "ddrck", "mpddr"; + }; + + smc: smc@ffffea00 { + compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x100>; + }; + + aic: interrupt-controller@fffff100 { + compatible = "microchip,sam9x7-aic"; + reg = <0xfffff100 0x100>; + #interrupt-cells = <3>; + interrupt-controller; + atmel,external-irqs = <31>; + }; + + dbgu: serial@fffff200 { + compatible = "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names = "tx", "rx"; + atmel,usart-mode = ; + status = "disabled"; + }; + + pinctrl: pinctrl@fffff400 { + compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "simple-mfd"; + ranges = <0xfffff400 0xfffff400 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ + atmel,mux-mask = < + /* A B C D */ + 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ + 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */ + 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ + 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <26>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible = "microchip,sam9x7-pmc", "syscon"; + reg = <0xfffffc00 0x200>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells = <2>; + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names = "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: reset-controller@fffffe00 { + compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; + reg = <0xfffffe00 0x10>; + clocks = <&clk32k 0>; + }; + + poweroff: poweroff@fffffe10 { + compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; + reg = <0xfffffe10 0x10>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk32k 0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + + rtt: rtc@fffffe20 { + compatible = "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; + reg = <0xfffffe20 0x20>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + + clk32k: clock-controller@fffffe50 { + compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; + reg = <0xfffffe50 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + + gpbr: syscon@fffffe60 { + compatible = "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffe60 0x10>; + }; + + rtc: rtc@fffffea8 { + compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; + reg = <0xfffffea8 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + + watchdog: watchdog@ffffff80 { + compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; + reg = <0xffffff80 0x24>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; + }; +}; From patchwork Tue Sep 3 06:44:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13788111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C9CBCA101E for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add documentation for SAM9X75 Curiosity board. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring Reviewed-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 82f37328cc69..7160ec80ac1b 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -106,6 +106,12 @@ properties: - const: microchip,sam9x60 - const: atmel,at91sam9 + - description: Microchip SAM9X7 Evaluation Boards + items: + - const: microchip,sam9x75-curiosity + - const: microchip,sam9x7 + - const: atmel,at91sam9 + - description: Nattis v2 board with Natte v2 power board items: - const: axentia,nattis-2 From patchwork Tue Sep 3 06:44:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13788114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBDA6CA101E for ; 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d="scan'208";a="31215856" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Sep 2024 23:45:13 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 2 Sep 2024 23:44:49 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 2 Sep 2024 23:44:46 -0700 From: Varshini Rajendran To: , , , , , , , , CC: Subject: [PATCH v7 12/12] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board Date: Tue, 3 Sep 2024 12:14:38 +0530 Message-ID: <20240903064438.49975-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240903063913.48307-1-varshini.rajendran@microchip.com> References: <20240903063913.48307-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240902_234513_376837_B4E0E50A X-CRM114-Status: GOOD ( 14.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device tree file for sam9x75 curiosity board. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- Changes in v7: - Added child nodes to the tcb node. - Moved poweroff node to maintain alphabetic order. --- arch/arm/boot/dts/microchip/Makefile | 3 + .../dts/microchip/at91-sam9x75_curiosity.dts | 324 ++++++++++++++++++ 2 files changed, 327 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile index 0c45c8d17468..470fe46433a9 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -2,6 +2,7 @@ # Enables support for device-tree overlays DTC_FLAGS_at91-sam9x60_curiosity := -@ DTC_FLAGS_at91-sam9x60ek := -@ +DTC_FLAGS_at91-sam9x75_curiosity := -@ DTC_FLAGS_at91-sama5d27_som1_ek := -@ DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ DTC_FLAGS_at91-sama5d29_curiosity := -@ @@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ dtb-$(CONFIG_SOC_SAM9X60) += \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb +dtb-$(CONFIG_SOC_SAM9X7) += \ + at91-sam9x75_curiosity.dtb dtb-$(CONFIG_SOC_SAM_V7) += \ at91-kizbox2-2.dtb \ at91-kizbox3-hs.dtb \ diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts new file mode 100644 index 000000000000..1119f5d60d89 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ +/dts-v1/; +#include "sam9x7.dtsi" +#include + +/ { + model = "Microchip SAM9X75 Curiosity"; + compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9"; + + aliases { + i2c0 = &i2c6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-user { + label = "USER"; + gpios = <&pioC 9 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_red: led-red { + label = "red"; + gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_red_led_gpio_default>; + }; + + led_green: led-green { + label = "green"; + gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_green_led_gpio_default>; + }; + + led_blue: led-blue { + label = "blue"; + gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_blue_led_gpio_default>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@20000000 { + reg = <0x20000000 0x10000000>; + device_type = "memory"; + }; +}; + +&classd { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_classd_default>; + atmel,pwm-type = "diff"; + atmel,non-overlap-time = <10>; + status = "okay"; +}; + +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu_default>; + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&flx6 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&i2c6 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-mode = <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-mode = <4>; + }; + }; + + dcdc4: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2s { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_default>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&main_xtal { + clock-frequency = <24000000>; +}; + +&pinctrl { + classd { + pinctrl_classd_default: classd-default { + atmel,pins = + , + ; + }; + }; + + dbgu { + pinctrl_dbgu_default: dbgu-default { + atmel,pins = , + ; + }; + }; + + flexcom { + pinctrl_flx6_default: flx6-default { + atmel,pins = + , + ; + }; + }; + + gpio-keys { + pinctrl_key_gpio_default: key-gpio-default { + atmel,pins = ; + }; + }; + + i2s { + pinctrl_i2s_default: i2s-default { + atmel,pins = + , /* I2SCK */ + , /* I2SWS */ + , /* I2SDIN */ + , /* I2SDOUT */ + ; /* I2SMCK */ + }; + }; + + leds { + pinctrl_red_led_gpio_default: red-led-gpio-default { + atmel,pins = ; + }; + pinctrl_green_led_gpio_default: green-led-gpio-default { + atmel,pins = ; + }; + pinctrl_blue_led_gpio_default: blue-led-gpio-default { + atmel,pins = ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0-default { + atmel,pins = + , /* PA2 CK periph A with pullup */ + , /* PA1 CMD periph A with pullup */ + , /* PA0 DAT0 periph A */ + , /* PA3 DAT1 periph A with pullup */ + , /* PA4 DAT2 periph A with pullup */ + ; /* PA5 DAT3 periph A with pullup */ + }; + }; +}; /* pinctrl */ + +&poweroff { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + +&sdmmc0 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&tcb { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&trng { + status = "okay"; +}; + +&watchdog { + status = "okay"; +};