From patchwork Thu Sep 5 09:56:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrei Simion X-Patchwork-Id: 13792074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85105CD5BA3 for ; Thu, 5 Sep 2024 09:58:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=K7VKQ5oSK53kA691ZRAcrbQj8Xdu4aPdXVmpnWGssm0=; b=djlXvJXsxdHVhfi/zfjt4Diiqy Pg5Ry+owVFxhJRgfEc+gIwDjMihztziYOYJ1ds+iOSq/84xW+lT5LvQmAkE48ojxtYL+map63lz44 58U0rSER3na4hVI1cxWpjVfUCAjdWDROurs6kI2OPJ7amQ9wntyPJhg0zWzeBJ2a5fY0tyunioYBL z40KWglDsNM3wt57Gw/KgeFMYSJ+o57dMD/mwt34zAAzleIFTtwogCLP4zmXbcmP7TiBnysnGFmtb d7VYZZEAn6s8T/7FO6UdkMPiI/cSlF2Ii5tXAW+yoi6ylgbuE9AZZ0qaeALxnuK13AhH6FIKqd2vo vsT6XKuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sm9Fc-00000007rzg-1Jbk; Thu, 05 Sep 2024 09:58:04 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sm9Ee-00000007rq2-1t0M for linux-arm-kernel@lists.infradead.org; Thu, 05 Sep 2024 09:57:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1725530224; x=1757066224; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=8qoKR4OXZ7Wgy4H3AAmtUwklGSIL4J9Jd0IV6fK4sOc=; b=iOxzG4cMg/xwclgd0ESQU0x/NlfLnBgPxpXwW0dweWwewLSfOGOKz+mB zTl3ygRSvuJNF0RaSuPDCNJNI0XRvurfwfZ8D4oTZgYd+jTfaez95m++I W1ZyDK8FG4i/HkF074uqw/0ZWS09tqhPNkBwkYgq+LYJKF2meztDZ0xXb 3YiNpYtFMHatDieqjEWSEAfDXcVdlp3PO5Er04O1gYofeJ4vfVogFqbYK VVbLaMFPc3APigQSCz0PFrHrUPzjznmhdW01kXk1DNmNDYITM953zK6oE k36kfkMReTVrW3Qw1XNkyip0zmyiUrw5fzJwIAgX3hhzduAC+U7HfdyR6 A==; X-CSE-ConnectionGUID: 8AyyTrCqQSGMj104kSMPQw== X-CSE-MsgGUID: jpWvbnd4T1yvQ3SdJQSknQ== X-IronPort-AV: E=Sophos;i="6.10,204,1719903600"; d="scan'208";a="34458244" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 05 Sep 2024 02:57:03 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 5 Sep 2024 02:56:40 -0700 Received: from ROB-ULT-M76677.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 5 Sep 2024 02:56:37 -0700 From: Andrei Simion To: , , , , , , CC: , , , , Codrin Ciubotariu , Andrei Simion Subject: [PATCH] ASoC: atmel: mchp-i2s-mcc: Improve maxburst calculation for better performance Date: Thu, 5 Sep 2024 12:56:33 +0300 Message-ID: <20240905095633.113784-1-andrei.simion@microchip.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240905_025704_525047_BBADE003 X-CRM114-Status: GOOD ( 14.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Codrin Ciubotariu The period size represents the size of the DMA descriptor. To ensure all DMA descriptors start from a well-aligned address, the period size must be divided by (sample size * maxburst), not just by maxburst. This adjustment allows for computing a higher maxburst value, thereby increasing the performance of the DMA transfer. Previously, snd_pcm_lib_period_bytes() returned 0 because the runtime HW parameters are computed after the hw_params() callbacks are used. To address this, we now use params_*() functions to compute the period size accurately. This change optimizes the DMA transfer performance by ensuring proper alignment and efficient use of maxburst values. Signed-off-by: Codrin Ciubotariu [andrei.simion@microchip.com: Reword commit message and commit title. Add macros with values for maximum DMA chunk size allowed. Add DMA_BURST_ALIGNED preprocessor function to check the alignment of the DMA burst] Signed-off-by: Andrei Simion --- sound/soc/atmel/mchp-i2s-mcc.c | 38 +++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) base-commit: fdadd93817f124fd0ea6ef251d4a1068b7feceba diff --git a/sound/soc/atmel/mchp-i2s-mcc.c b/sound/soc/atmel/mchp-i2s-mcc.c index 193dd7acceb0..35a56b266b8d 100644 --- a/sound/soc/atmel/mchp-i2s-mcc.c +++ b/sound/soc/atmel/mchp-i2s-mcc.c @@ -221,6 +221,15 @@ #define MCHP_I2SMCC_MAX_CHANNELS 8 #define MCHP_I2MCC_TDM_SLOT_WIDTH 32 +/* + * ---- DMA chunk size allowed ---- + */ +#define MCHP_I2SMCC_DMA_8_WORD_CHUNK 8 +#define MCHP_I2SMCC_DMA_4_WORD_CHUNK 4 +#define MCHP_I2SMCC_DMA_2_WORD_CHUNK 2 +#define MCHP_I2SMCC_DMA_1_WORD_CHUNK 1 +#define DMA_BURST_ALIGNED(_p, _s, _w) !(_p % (_s * _w)) + static const struct regmap_config mchp_i2s_mcc_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -504,12 +513,30 @@ static int mchp_i2s_mcc_is_running(struct mchp_i2s_mcc_dev *dev) return !!(sr & (MCHP_I2SMCC_SR_TXEN | MCHP_I2SMCC_SR_RXEN)); } +static inline int mchp_i2s_mcc_period_to_maxburst(int period_size, int sample_size) +{ + int p_size = period_size; + int s_size = sample_size; + + if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_I2SMCC_DMA_8_WORD_CHUNK)) + return MCHP_I2SMCC_DMA_8_WORD_CHUNK; + if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_I2SMCC_DMA_4_WORD_CHUNK)) + return MCHP_I2SMCC_DMA_4_WORD_CHUNK; + if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_I2SMCC_DMA_2_WORD_CHUNK)) + return MCHP_I2SMCC_DMA_2_WORD_CHUNK; + return MCHP_I2SMCC_DMA_1_WORD_CHUNK; +} + static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { unsigned long rate = 0; struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai); + int sample_bytes = params_physical_width(params) / 8; + int period_bytes = params_period_size(params) * + params_channels(params) * sample_bytes; + int maxburst; u32 mra = 0; u32 mrb = 0; unsigned int channels = params_channels(params); @@ -519,9 +546,9 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream, int ret; bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); - dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", + dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u period_bytes=%d\n", __func__, params_rate(params), params_format(params), - params_width(params), params_channels(params)); + params_width(params), params_channels(params), period_bytes); switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: @@ -630,11 +657,12 @@ static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream, * We must have the same burst size configured * in the DMA transfer and in out IP */ - mrb |= MCHP_I2SMCC_MRB_DMACHUNK(channels); + maxburst = mchp_i2s_mcc_period_to_maxburst(period_bytes, sample_bytes); + mrb |= MCHP_I2SMCC_MRB_DMACHUNK(maxburst); if (is_playback) - dev->playback.maxburst = 1 << (fls(channels) - 1); + dev->playback.maxburst = maxburst; else - dev->capture.maxburst = 1 << (fls(channels) - 1); + dev->capture.maxburst = maxburst; switch (params_format(params)) { case SNDRV_PCM_FORMAT_S8: