From patchwork Thu Sep 5 11:18:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13792170 X-Patchwork-Delegate: kieran@bingham.xyz Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EF7F4155730; Thu, 5 Sep 2024 11:18:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725535122; cv=none; b=CJNREaJ73318ThltDPRu5gX5f1AEpB2yP82OL+hYK1XMj7M8sOTypNhrR6aq67GBXsJB6joldfmhvoAm7YQY8EEy5qByMlRKM7TrUJUoP7HA3QNsEseFG+NZnvfEY4Jf5r+grXMx1RnJhj1Xerh0PuHvyk8RwGzkNYyx1ZSoy3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725535122; c=relaxed/simple; bh=y3EqDBeyVCmdb0mMrYzaC93JpZi07aStyd+H8aNiG1s=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=POD6eA0WkT1TooajwRfDFlCE73SYuJb/YVz2zBbdgo1j3uLsdEQc2/3hj7rG9qcvagG9nhJ+uGdpSj+kf00n+ynP+WJ3QfhndhsWSRPkIbsdDUJSkVr7dfqsMtRrtjUMscVQdDZ5FsfIyK2cSwJhBqNoHBBRDTGeaBkP/jl2YNc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.10,204,1719846000"; d="scan'208";a="221612434" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 05 Sep 2024 20:18:33 +0900 Received: from localhost.localdomain (unknown [10.226.93.27]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A179A4007CFC; Thu, 5 Sep 2024 20:18:30 +0900 (JST) From: Biju Das To: Mauro Carvalho Chehab Cc: Biju Das , Laurent Pinchart , Hans Verkuil , Hien Huynh , Benjamin Gaignard , linux-media@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH] media: platform: rzg2l-cru: rzg2l-video: Set AXI burst max length Date: Thu, 5 Sep 2024 12:18:26 +0100 Message-ID: <20240905111828.159670-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As per the hardware manual section 35.2.3.26 'AXI Master Transfer Setting Register for CRU Image Data;, it is mentioned that to improve the transfer performance of CRU, it is recommended to use AXILEN value '0xf' for AXI burst max length setting for image data. Signed-off-by: Hien Huynh Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart --- .../media/platform/renesas/rzg2l-cru/rzg2l-video.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c index 374dc084717f..d17e3eac4177 100644 --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c @@ -52,6 +52,11 @@ #define AMnMBS 0x14c #define AMnMBS_MBSTS 0x7 +/* AXI Master Transfer Setting Register for CRU Image Data */ +#define AMnAXIATTR 0x158 +#define AMnAXIATTR_AXILEN_MASK GENMASK(3, 0) +#define AMnAXIATTR_AXILEN (0xf) + /* AXI Master FIFO Pointer Register for CRU Image Data */ #define AMnFIFOPNTR 0x168 #define AMnFIFOPNTR_FIFOWPNTR GENMASK(7, 0) @@ -278,6 +283,7 @@ static void rzg2l_cru_fill_hw_slot(struct rzg2l_cru_dev *cru, int slot) static void rzg2l_cru_initialize_axi(struct rzg2l_cru_dev *cru) { unsigned int slot; + u32 amnaxiattr; /* * Set image data memory banks. @@ -287,6 +293,11 @@ static void rzg2l_cru_initialize_axi(struct rzg2l_cru_dev *cru) for (slot = 0; slot < cru->num_buf; slot++) rzg2l_cru_fill_hw_slot(cru, slot); + + /* Set AXI burst max length to recommended setting */ + amnaxiattr = rzg2l_cru_read(cru, AMnAXIATTR) & ~AMnAXIATTR_AXILEN_MASK; + amnaxiattr |= AMnAXIATTR_AXILEN; + rzg2l_cru_write(cru, AMnAXIATTR, amnaxiattr); } static void rzg2l_cru_csi2_setup(struct rzg2l_cru_dev *cru, bool *input_is_yuv,