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Thu, 5 Sep 2024 09:33:18 -0400 (EDT) From: Jiaxun Yang Date: Thu, 05 Sep 2024 14:33:05 +0100 Subject: [PATCH v2 1/3] rust: Introduce HAVE_GENERATE_RUST_TARGET config option Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240905-mips-rust-v2-1-409d66819418@flygoat.com> References: <20240905-mips-rust-v2-0-409d66819418@flygoat.com> In-Reply-To: <20240905-mips-rust-v2-0-409d66819418@flygoat.com> To: Masahiro Yamada , Nathan Chancellor , Nicolas Schier , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Thomas Bogendoerfer , Steven Rostedt , Masami Hiramatsu , Mark Rutland , Jonathan Corbet , Alex Shi , Yanteng Si , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org, rust-for-linux@vger.kernel.org, linux-mips@vger.kernel.org, linux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4405; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=q9PK02pd92y+v95I+RdQsTEBNzvKFSGnPjB2K/vbR1o=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrSbm8WZX2o4zdgxVyZfmPWpzcW7/39KRB/htN5QpH9If eOqrW9/dJSyMIhxMciKKbKECCj1bWi8uOD6g6w/MHNYmUCGMHBxCsBEPFkYGdaoZFjN/TVR8sSp hWK3ZWLWFqvr9p4Tjn/lcuuZ8Jp7K8wZGe5GJrZPidTY8fb3KsaNHVolOa+WCTmGOZ17yFpbmPl 1BhcA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 scripts/generate_rust_target.rs is used by several architectures to generate target.json target spec file. However the enablement of this feature was controlled by target specific Makefile pieces spreading everywhere. Introduce HAVE_GENERATE_RUST_TARGET config option as a centralized switch to control the per-arch usage of generate_rust_target.rs. Signed-off-by: Jiaxun Yang --- v2: - Reword Kconfig help - Remove x86 specific condition for UM --- Makefile | 3 +++ arch/Kconfig | 8 ++++++++ arch/um/Kconfig | 1 + arch/x86/Makefile | 1 - arch/x86/Makefile.um | 1 - rust/Makefile | 2 +- scripts/Makefile | 4 +--- 7 files changed, 14 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 2c1db7a6f793..b183855c34ea 100644 --- a/Makefile +++ b/Makefile @@ -807,6 +807,9 @@ KBUILD_CFLAGS += -Os KBUILD_RUSTFLAGS += -Copt-level=s endif +ifdef CONFIG_HAVE_GENERATE_RUST_TARGET +KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json +endif # Always set `debug-assertions` and `overflow-checks` because their default # depends on `opt-level` and `debug-assertions`, respectively. KBUILD_RUSTFLAGS += -Cdebug-assertions=$(if $(CONFIG_RUST_DEBUG_ASSERTIONS),y,n) diff --git a/arch/Kconfig b/arch/Kconfig index 4e2eaba9e305..0865ff4796e7 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -377,6 +377,14 @@ config HAVE_RUST This symbol should be selected by an architecture if it supports Rust. +config HAVE_GENERATE_RUST_TARGET + bool + depends on HAVE_RUST + help + This symbol should be selected by an architecture if it + needs generating Rust target.json file with + scripts/generate_rust_target.rs. + config HAVE_FUNCTION_ARG_ACCESS_API bool help diff --git a/arch/um/Kconfig b/arch/um/Kconfig index dca84fd6d00a..6b1c8ae2422d 100644 --- a/arch/um/Kconfig +++ b/arch/um/Kconfig @@ -32,6 +32,7 @@ config UML select TTY # Needed for line.c select HAVE_ARCH_VMAP_STACK select HAVE_RUST + select HAVE_GENERATE_RUST_TARGET select ARCH_HAS_UBSAN config MMU diff --git a/arch/x86/Makefile b/arch/x86/Makefile index a1883a30a5d8..cbd707f88a63 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -75,7 +75,6 @@ export BITS # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53383 # KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx -KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json KBUILD_RUSTFLAGS += -Ctarget-feature=-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2 # diff --git a/arch/x86/Makefile.um b/arch/x86/Makefile.um index a46b1397ad01..2106a2bd152b 100644 --- a/arch/x86/Makefile.um +++ b/arch/x86/Makefile.um @@ -9,7 +9,6 @@ core-y += arch/x86/crypto/ # ifeq ($(CONFIG_CC_IS_CLANG),y) KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx -KBUILD_RUSTFLAGS += --target=$(objtree)/scripts/target.json KBUILD_RUSTFLAGS += -Ctarget-feature=-sse,-sse2,-sse3,-ssse3,-sse4.1,-sse4.2,-avx,-avx2 endif diff --git a/rust/Makefile b/rust/Makefile index 99204e33f1dd..fe3640b98011 100644 --- a/rust/Makefile +++ b/rust/Makefile @@ -378,7 +378,7 @@ $(obj)/core.o: private rustc_objcopy = $(foreach sym,$(redirect-intrinsics),--re $(obj)/core.o: private rustc_target_flags = $(core-cfgs) $(obj)/core.o: $(RUST_LIB_SRC)/core/src/lib.rs FORCE +$(call if_changed_rule,rustc_library) -ifneq ($(or $(CONFIG_X86_64),$(CONFIG_X86_32)),) +ifdef CONFIG_HAVE_GENERATE_RUST_TARGET $(obj)/core.o: scripts/target.json endif diff --git a/scripts/Makefile b/scripts/Makefile index dccef663ca82..33258a856a1a 100644 --- a/scripts/Makefile +++ b/scripts/Makefile @@ -12,13 +12,11 @@ hostprogs-always-$(CONFIG_SYSTEM_EXTRA_CERTIFICATE) += insert-sys-cert hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_builder hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_gen -ifneq ($(or $(CONFIG_X86_64),$(CONFIG_X86_32)),) -always-$(CONFIG_RUST) += target.json +always-$(CONFIG_HAVE_GENERATE_RUST_TARGET) += target.json filechk_rust_target = $< < include/config/auto.conf $(obj)/target.json: scripts/generate_rust_target include/config/auto.conf FORCE $(call filechk,rust_target) -endif hostprogs += generate_rust_target generate_rust_target-rust := y From patchwork Thu Sep 5 13:33:06 2024 Content-Type: text/plain; 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Thu, 5 Sep 2024 09:33:22 -0400 (EDT) From: Jiaxun Yang Date: Thu, 05 Sep 2024 14:33:06 +0100 Subject: [PATCH v2 2/3] MIPS: Rename mips_instruction type to workaround bindgen issue Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240905-mips-rust-v2-2-409d66819418@flygoat.com> References: <20240905-mips-rust-v2-0-409d66819418@flygoat.com> In-Reply-To: <20240905-mips-rust-v2-0-409d66819418@flygoat.com> To: Masahiro Yamada , Nathan Chancellor , Nicolas Schier , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Thomas Bogendoerfer , Steven Rostedt , Masami Hiramatsu , Mark Rutland , Jonathan Corbet , Alex Shi , Yanteng Si , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org, rust-for-linux@vger.kernel.org, linux-mips@vger.kernel.org, linux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=6623; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=3K6o6Y8Ib1fJ7SBPgZmUC+L5hQTpFLi2ds4RhATIGXI=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrSbm8WdVK9V5xz5aygReSNuw6mU0DcnMi6Eru0zOrTLe 0pilWJ8RykLgxgXg6yYIkuIgFLfhsaLC64/yPoDM4eVCWQIAxenAEyk2ZGR4W/ywviWDQnXtuRG zMt6/J556pQLkY6c12unHT/tsziB8yojw+fu/Z1+G7Zm9+h+6A4RON69jd/l/cdWs0PzWUN1+iP +cgAA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 We have a union and a type both named after mips_instruction, rust bindgen is not happy with this kind of naming alias. Given that union mips_instruction is a part of UAPI, the best thing we can do is to rename mips_instruction type. Rename it as mips_insn, which is not conflicting with anything and aligned with struct name here. Signed-off-by: Jiaxun Yang --- v2: Reword commit messsage --- arch/mips/include/asm/dsemul.h | 2 +- arch/mips/include/asm/inst.h | 6 +++--- arch/mips/kernel/ftrace.c | 2 +- arch/mips/kernel/kprobes.c | 2 +- arch/mips/math-emu/cp1emu.c | 18 +++++++++--------- arch/mips/math-emu/dsemul.c | 8 ++++---- 6 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/mips/include/asm/dsemul.h b/arch/mips/include/asm/dsemul.h index 08bfe8fa3b40..870597d6d1ad 100644 --- a/arch/mips/include/asm/dsemul.h +++ b/arch/mips/include/asm/dsemul.h @@ -34,7 +34,7 @@ struct task_struct; * * Return: Zero on success, negative if ir is a NOP, signal number on failure. */ -extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, +extern int mips_dsemul(struct pt_regs *regs, mips_insn ir, unsigned long branch_pc, unsigned long cont_pc); /** diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index 2f98ced30263..0616b8eb7401 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h @@ -71,12 +71,12 @@ #define I_FMA_FFMT_SFT 0 #define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000007) -typedef unsigned int mips_instruction; +typedef unsigned int mips_insn; /* microMIPS instruction decode structure. Do NOT export!!! */ struct mm_decoded_insn { - mips_instruction insn; - mips_instruction next_insn; + mips_insn insn; + mips_insn next_insn; int pc_inc; int next_pc_inc; int micro_mips_mode; diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index 8c401e42301c..153c9666a77c 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c @@ -248,7 +248,7 @@ int ftrace_disable_ftrace_graph_caller(void) #define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */ #define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */ -unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long +static long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long old_parent_ra, unsigned long parent_ra_addr, unsigned long fp) { unsigned long sp, ip, tmp; diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c index dc39f5b3fb83..7a1b1c3674da 100644 --- a/arch/mips/kernel/kprobes.c +++ b/arch/mips/kernel/kprobes.c @@ -90,7 +90,7 @@ int arch_prepare_kprobe(struct kprobe *p) } if (copy_from_kernel_nofault(&prev_insn, p->addr - 1, - sizeof(mips_instruction)) == 0 && + sizeof(kprobe_opcode_t)) == 0 && insn_has_delayslot(prev_insn)) { pr_notice("Kprobes for branch delayslot are not supported\n"); ret = -EINVAL; diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 265bc57819df..bcd6a6f0034c 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -43,10 +43,10 @@ /* Function which emulates a floating point instruction. */ static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, - mips_instruction); + mips_insn); static int fpux_emu(struct pt_regs *, - struct mips_fpu_struct *, mips_instruction, void __user **); + struct mips_fpu_struct *, mips_insn, void __user **); /* Control registers */ @@ -846,7 +846,7 @@ do { \ * Emulate a CFC1 instruction. */ static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - mips_instruction ir) + mips_insn ir) { u32 fcr31 = ctx->fcr31; u32 value = 0; @@ -903,7 +903,7 @@ static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * Emulate a CTC1 instruction. */ static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - mips_instruction ir) + mips_insn ir) { u32 fcr31 = ctx->fcr31; u32 value; @@ -973,7 +973,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, { unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; unsigned int cond, cbit, bit0; - mips_instruction ir; + mips_insn ir; int likely, pc_inc; union fpureg *fpr; u32 __user *wva; @@ -1461,7 +1461,7 @@ DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - mips_instruction ir, void __user **fault_addr) + mips_insn ir, void __user **fault_addr) { unsigned int rcsr = 0; /* resulting csr */ @@ -1680,7 +1680,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, * Emulate a single COP1 arithmetic instruction. */ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, - mips_instruction ir) + mips_insn ir) { int rfmt; /* resulting format */ unsigned int rcsr = 0; /* resulting csr */ @@ -2899,9 +2899,9 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, dec_insn.micro_mips_mode = 1; } else { if ((get_user(dec_insn.insn, - (mips_instruction __user *) xcp->cp0_epc)) || + (mips_insn __user *) xcp->cp0_epc)) || (get_user(dec_insn.next_insn, - (mips_instruction __user *)(xcp->cp0_epc+4)))) { + (mips_insn __user *)(xcp->cp0_epc+4)))) { MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index e02bd20b60a6..d4ea2cf89006 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -61,8 +61,8 @@ * couldn't already. */ struct emuframe { - mips_instruction emul; - mips_instruction badinst; + mips_insn emul; + mips_insn badinst; }; static const int emupage_frame_count = PAGE_SIZE / sizeof(struct emuframe); @@ -206,11 +206,11 @@ void dsemul_mm_cleanup(struct mm_struct *mm) bitmap_free(mm_ctx->bd_emupage_allocmap); } -int mips_dsemul(struct pt_regs *regs, mips_instruction ir, +int mips_dsemul(struct pt_regs *regs, mips_insn ir, unsigned long branch_pc, unsigned long cont_pc) { int isa16 = get_isa16_mode(regs->cp0_epc); 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Thu, 5 Sep 2024 09:33:27 -0400 (EDT) From: Jiaxun Yang Date: Thu, 05 Sep 2024 14:33:07 +0100 Subject: [PATCH v2 3/3] rust: Enable for MIPS Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240905-mips-rust-v2-3-409d66819418@flygoat.com> References: <20240905-mips-rust-v2-0-409d66819418@flygoat.com> In-Reply-To: <20240905-mips-rust-v2-0-409d66819418@flygoat.com> To: Masahiro Yamada , Nathan Chancellor , Nicolas Schier , Richard Weinberger , Anton Ivanov , Johannes Berg , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Thomas Bogendoerfer , Steven Rostedt , Masami Hiramatsu , Mark Rutland , Jonathan Corbet , Alex Shi , Yanteng Si , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org, rust-for-linux@vger.kernel.org, linux-mips@vger.kernel.org, linux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5800; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=dVkj/exm1KSiU0b/0TGp9u+BBn+LGdFz9eAdIeMiN8A=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhrSbm8Xny0wpaS6zMgrh3PNl5YuLz+8Zsv5d7N0mF9oho p24+WxwRykLgxgXg6yYIkuIgFLfhsaLC64/yPoDM4eVCWQIAxenAExEIJaRoe9RxA3OG0se3WJ6 lOPL4i1dUTfX6Kdsc/8qDvWVAusyXjAydDeeWrP5vHfo5tqXnse38Po/+p/++EsJD/+NDq7tRj0 H+AE= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Enable rust for linux by implement generate_rust_target.rs and select relevant Kconfig options. We don't use builtin target as there is no sutiable baremetal target for us that can cover all ISA variants supported by kernel. Link: https://github.com/Rust-for-Linux/linux/issues/107 Signed-off-by: Jiaxun Yang --- v2: - Add micromips flags - Sync issues with upstream --- Documentation/rust/arch-support.rst | 1 + .../translations/zh_CN/rust/arch-support.rst | 1 + arch/mips/Kconfig | 2 + scripts/generate_rust_target.rs | 68 ++++++++++++++++++++++ 4 files changed, 72 insertions(+) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst index 750ff371570a..ab6c0ae5a407 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -17,6 +17,7 @@ Architecture Level of support Constraints ============= ================ ============================================== ``arm64`` Maintained Little Endian only. ``loongarch`` Maintained \- +``mips`` Maintained \- ``riscv`` Maintained ``riscv64`` only. ``um`` Maintained \- ``x86`` Maintained ``x86_64`` only. diff --git a/Documentation/translations/zh_CN/rust/arch-support.rst b/Documentation/translations/zh_CN/rust/arch-support.rst index abd708d48f82..1eaa6c3297ac 100644 --- a/Documentation/translations/zh_CN/rust/arch-support.rst +++ b/Documentation/translations/zh_CN/rust/arch-support.rst @@ -21,6 +21,7 @@ ============= ================ ============================================== ``arm64`` Maintained 只有小端序 ``loongarch`` Maintained \- +``mips`` Maintained \- ``riscv`` Maintained 只有 ``riscv64`` ``um`` Maintained 只有 ``x86_64`` ``x86`` Maintained 只有 ``x86_64`` diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 43da6d596e2b..a91f0a4fd8e9 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -90,6 +90,8 @@ config MIPS select HAVE_PERF_USER_STACK_DUMP select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RSEQ + select HAVE_RUST + select HAVE_GENERATE_RUST_TARGET select HAVE_SPARSE_SYSCALL_NR select HAVE_STACKPROTECTOR select HAVE_SYSCALL_TRACEPOINTS diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs index 863720777313..bbdf8a4dd169 100644 --- a/scripts/generate_rust_target.rs +++ b/scripts/generate_rust_target.rs @@ -141,6 +141,13 @@ fn has(&self, option: &str) -> bool { let option = "CONFIG_".to_owned() + option; self.0.contains_key(&option) } + + /// Returns the value of the option in the configuration. + /// The argument must be passed without the `CONFIG_` prefix. + fn get(&self, option: &str) -> Option<&String> { + let option = "CONFIG_".to_owned() + option; + self.0.get(&option) + } } fn main() { @@ -203,6 +210,67 @@ fn main() { ts.push("target-pointer-width", "32"); } else if cfg.has("LOONGARCH") { panic!("loongarch uses the builtin rustc loongarch64-unknown-none-softfloat target"); + } else if cfg.has("MIPS") { + let mut features = "+soft-float,+noabicalls".to_string(); + + if cfg.has("CPU_MICROMIPS") { + features += ",+micromips"; + } + + if cfg.has("64BIT") { + ts.push("arch", "mips64"); + ts.push("abi", "abi64"); + cfg.get("TARGET_ISA_REV").map(|isa_rev| { + let feature = match isa_rev.as_str() { + "1" => ",+mips64", + "2" => ",+mips64r2", + "5" => ",+mips64r5", + "6" => ",+mips64r6", + _ => ",+mips3", + }; + features += feature; + }); + + ts.push("features", features); + if cfg.has("CPU_BIG_ENDIAN") { + ts.push( + "data-layout", + "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128", + ); + ts.push("llvm-target", "mips64-unknown-linux-gnuabi64"); + } else { + ts.push( + "data-layout", + "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128", + ); + ts.push("llvm-target", "mips64el-unknown-linux-gnuabi64"); + } + ts.push("target-pointer-width", "64"); + } else { + ts.push("arch", "mips"); + cfg.get("TARGET_ISA_REV").map(|isa_rev| { + let feature = match isa_rev.as_str() { + "1" => ",+mips32", + "2" => ",+mips32r2", + "5" => ",+mips32r5", + "6" => ",+mips32r6", + _ => ",+mips2", + }; + features += feature; + }); + + ts.push("features", features); + if cfg.has("CPU_BIG_ENDIAN") { + ts.push("data-layout", + "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); + ts.push("llvm-target", "mips-unknown-linux-gnu"); + } else { + ts.push("data-layout", + "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); + ts.push("llvm-target", "mipsel-unknown-linux-gnu"); + } + ts.push("target-pointer-width", "32"); + } } else { panic!("Unsupported architecture"); }