From patchwork Fri Sep 6 08:25:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 13793678 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 725E4158538; Fri, 6 Sep 2024 08:25:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725611123; cv=none; b=lx+2q4hpOpS4AV+yOuZZtBBoCa58iz2y4QvKvxG+SDbe3nXzeaOX8S4dWlSP15ATwtdGaqgr+RGzad/rVXzONSoD0oAiqCXxohDQkGXSgRZK42K2Y+mDsa16UiFmX1QQ95HknD1ErEpuZhcBTpsosxULDXmDjB/kB7TeEF+zI5c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725611123; c=relaxed/simple; bh=aFR7tnhmuKRaAKDJZCHPL+0HzSPymvIBsaXDCAKTrJg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ox5/+B/nDbxB+hzo/CnULtMNQKj94PjJXqYMOoekWZSbJOgfDLSUVccLKVa4nWF4g+wyX7lHWb9ry0zEVQvPbdHDXxv0GCR5Z8twzkiXCzE+9+DRxOaHRbRPLM71umTDz6/Zx7+ViSZ6icxyTSg4LoQsG65t0V80pvRcV7y6RHY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=DjQGJgq/; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="DjQGJgq/" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=QLt5ROu80qBeLulyysZjT7aHie2yMAENhMSfHIXMOWc=; b=DjQGJgq/ozrgD2AaOtIPaA5vBH nJ849xmtFv3gWbWX/w/rMplyVT8U77tAIPar4rP2kJ68acfvOrVGkyE+QwKO/d0yhIiB41VU46KI3 0fi+l+6o3vXqW/bEWyqdEvhQER1iNUJLwdk2TeOciZNq/XBlC59onC9mFs+SiNnhVm790pcRD+Pnq 7f5BxJfFRfFQgViHPjxk2YpgNNirVH6Y84gsx9+dgNkc6CUzg75MslfQSVWzc5CUnn/OAcwQWsC2v ydliDLTnoNMTm7K2FA1K/6Lg97cw+H2b5ccrmemIMoYefA9KlTSvpGzbgp0VLdvffGuvlSpTvcL6v 8t6wxXmw==; Received: from i5e860d0f.versanet.de ([94.134.13.15] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1smUHO-0000jF-Pt; Fri, 06 Sep 2024 10:25:18 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Conor Dooley Subject: [PATCH v4 1/5] dt-bindings: clocks: add binding for gated-fixed-clocks Date: Fri, 6 Sep 2024 10:25:07 +0200 Message-ID: <20240906082511.2963890-2-heiko@sntech.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240906082511.2963890-1-heiko@sntech.de> References: <20240906082511.2963890-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In contrast to fixed clocks that are described as ungateable, boards sometimes use additional oscillators for things like PCIe reference clocks, that need actual supplies to get enabled and enable-gpios to be toggled for them to work. This adds a binding for such oscillators that are not configurable themself, but need to handle supplies for them to work. In schematics they often can be seen as ---------------- Enable - | 100MHz,3.3V, | - VDD | 3225 | GND - | | - OUT ---------------- or similar. The enable pin might be separate but can also just be tied to the vdd supply, hence it is optional in the binding. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring (Arm) Reviewed-by: Conor Dooley --- .../bindings/clock/gated-fixed-clock.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml b/Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml new file mode 100644 index 000000000000..d3e0faf3c64d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gated-fixed-clock.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gated-fixed-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gated Fixed clock + +maintainers: + - Heiko Stuebner + +properties: + compatible: + const: gated-fixed-clock + + "#clock-cells": + const: 0 + + clock-frequency: true + + clock-output-names: + maxItems: 1 + + enable-gpios: + description: + Contains a single GPIO specifier for the GPIO that enables and disables + the oscillator. + maxItems: 1 + + vdd-supply: + description: handle of the regulator that provides the supply voltage + +required: + - compatible + - "#clock-cells" + - clock-frequency + - vdd-supply + +additionalProperties: false + +examples: + - | + clock-1000000000 { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + vdd-supply = <®_vdd>; + }; +... From patchwork Fri Sep 6 08:25:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 13793679 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 216F015853A; Fri, 6 Sep 2024 08:25:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725611123; cv=none; b=tQt3v5a9s4319mw2QFmb8LZ5PQ7jAXE3Jb04oxDEjhFyINSCSBSkDI1aSR/YhNw55ASur3dcPyE72veuZ3hOPVP7MeweE539xN8FccIShZVDSHOcylUQhg2Xm+uOhhl648fJRxoLrySeoS0lDJNS5to5mtFnTLf+onq9qDyMdVY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725611123; c=relaxed/simple; bh=CApMsTqccAwD+CzsW7wWwohVHNh5WbVaiWrgACe4r3I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HfthscuM0XhBUz3PUXJ/0/iSW0cui8GXQX0/Ax4uZVrxd2ehyemHHhcIu0lRhx6aOGMwK/QaaVyHiCQtmpsrV4XSWdQkYd4QJSKKIv4fzWdNaMUYJh514rJZ/jhRTm8Llfy+543szFUuQaziIXvkq5g9/OCLNRFn0yVbXgZEeyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=goaq85ud; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="goaq85ud" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=yGq3JneIJdLWkKicCiB7nkPv7xgVLix/YDHDBEAt+dY=; b=goaq85udzdVSmxwu1bYO4dwi7M BEQz2255HQOnPEC6AVicypFep6WFSmVM2QuKV2pqGeLFgEOmAbGbuiXNKtF4/X/CQQhkbH9Is6bSL NCueNsAzH6MgkMooQA8CjMcWv7e45PrXYcELVKNqUPJv7HxelhtBZA4V/mH809jBq+RaaCXxZugaw sVLS0JSsJnA6BEF7y3jjGEvLq4XAYSh9cQSeYUMwQoFSBpR3dn2DDk7WSXGONeyXrL9qKM31SC0Cs BbpMmAvP6uQAUTAuLWxg4fPOHSogR33uZaF8MKpTkCopwz2WQFvz8BOXYWD5TnUP0alxE9VG9kORP gxx9cU2A==; Received: from i5e860d0f.versanet.de ([94.134.13.15] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1smUHP-0000jF-A0; Fri, 06 Sep 2024 10:25:19 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 2/5] clk: clk-gpio: update documentation for gpio-gate clock Date: Fri, 6 Sep 2024 10:25:08 +0200 Message-ID: <20240906082511.2963890-3-heiko@sntech.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240906082511.2963890-1-heiko@sntech.de> References: <20240906082511.2963890-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The main documentation block seems to be from a time before the driver handled sleeping and non-sleeping gpios and with that change it seems updating the doc was overlooked. So do that now. Signed-off-by: Heiko Stuebner --- drivers/clk/clk-gpio.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index 5b114043771d..98415782f9a2 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -22,8 +22,9 @@ * DOC: basic gpio gated clock which can be enabled and disabled * with gpio output * Traits of this clock: - * prepare - clk_(un)prepare only ensures parent is (un)prepared - * enable - clk_enable and clk_disable are functional & control gpio + * prepare - clk_(un)prepare are functional and control a gpio that can sleep + * enable - clk_enable and clk_disable are functional & control + * non-sleeping gpio * rate - inherits rate from parent. No clk_set_rate support * parent - fixed parent. No clk_set_parent support */ From patchwork Fri Sep 6 08:25:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 13793680 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FDD4158548; Fri, 6 Sep 2024 08:25:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725611123; cv=none; b=mSEB2wtDw6hnlTGru0XG8iaLLS3fb6qlDhI2bXFYeXaFh23Bp708G3jAJr4XAGEY9tv1Cp+78Mycafg7MBjQh28xSZVPTMokdLBxLNTG2VfAh/TtnGy1UwHqUUokIHFmmlaU/4AsgicLV3uscfGQPPgNJcLwbpT6uzgShZ5zuYw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725611123; c=relaxed/simple; bh=O8N26FIu+js1B7eU91uGZOCbPHACJf17XHhbShcXMoQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LTvYwSSMJcjxTnWa8FYztcVZZMiEEGsKoJmpNZ7hB/9wHBaBttKbK4O6oBpuAekaxi1k9MWnUocTODOjnluNioM4BeoeI5MiT4DDZCkqogkCv8Nvklr548Ufg9fSkGKxb4ui13cxoabj1ysCqXsw+zNAXKVDbRwXYRz/RdjLqUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=LrwR39eW; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="LrwR39eW" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=TqxynQHVtMcMYcTlZ9c4J6WTyfOvhuPEE/JTjaFof8c=; b=LrwR39eWNErCClWorqwywiKGQ/ 1GEu1mZ94vd80Hw7neS0f8eUCbl3DgBfeBqcdxTnKpTKQL28GB1vF5QWgDCqewuxA3KsR5Wxl0Izk my12JGWFhQqsVU+SDODqWcMVUOPVL13eMDsqWdbQVK7Pcs/hOBYThYJBme8dzGX6slp767eMHngMk Szz2KFavkd9JuLMHV4di7wPMs91JjUjr1Eu1nfgMtYFls1jGqRN9ygN7zkdPSrJZv8YQ4p6K8FTFz SutLlTk9IhKQxaGvV6ZrVhCXm4mot1uNguWCU/SLCZB2F/YGiqUyHfRbsxMAWHaRVnc/Ldyh7IzWP TPcCTkAw==; Received: from i5e860d0f.versanet.de ([94.134.13.15] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1smUHP-0000jF-R6; Fri, 06 Sep 2024 10:25:19 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 3/5] clk: clk-gpio: use dev_err_probe for gpio-get failure Date: Fri, 6 Sep 2024 10:25:09 +0200 Message-ID: <20240906082511.2963890-4-heiko@sntech.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240906082511.2963890-1-heiko@sntech.de> References: <20240906082511.2963890-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This is a real driver and dev_err_probe will hide the distinction between EPROBE_DEFER and other errors automatically, so there is no need to open-code this. Signed-off-by: Heiko Stuebner --- drivers/clk/clk-gpio.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index 98415782f9a2..cda362a2eca0 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -200,7 +200,6 @@ static int gpio_clk_driver_probe(struct platform_device *pdev) struct gpio_desc *gpiod; struct clk_hw *hw; bool is_mux; - int ret; is_mux = of_device_is_compatible(node, "gpio-mux-clock"); @@ -212,17 +211,9 @@ static int gpio_clk_driver_probe(struct platform_device *pdev) gpio_name = is_mux ? "select" : "enable"; gpiod = devm_gpiod_get(dev, gpio_name, GPIOD_OUT_LOW); - if (IS_ERR(gpiod)) { - ret = PTR_ERR(gpiod); - if (ret == -EPROBE_DEFER) - pr_debug("%pOFn: %s: GPIOs not yet available, retry later\n", - node, __func__); - else - pr_err("%pOFn: %s: Can't get '%s' named GPIO property\n", - node, __func__, - gpio_name); - return ret; - } + if (IS_ERR(gpiod)) + return dev_err_probe(dev, PTR_ERR(gpiod), + "Can't get '%s' named GPIO property\n", gpio_name); if (is_mux) hw = clk_hw_register_gpio_mux(dev, gpiod); From patchwork Fri Sep 6 08:25:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 13793682 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA9E015854A; Fri, 6 Sep 2024 08:25:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725611124; cv=none; b=Z5FqSIkoJb/wDrjjf33tv4Zi7kE3SA3XfOxyowjYpakNntoIHS7hVS5/4sXp1kNW1zmeX6utJnDRsrc2rIIg81VkaG2pFZ8s/LBwvE5kSwrHt4ViMALvWgOVx0pq3E5U27Z+aILAhbrAOuRyshUlivxMn0nuv/ccwPAqNAuia+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725611124; c=relaxed/simple; bh=tRdRr/QErLxG9jQmLJyDACsa3C73d3fuYxjKJe56PEU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m5k353oHuc7e2Luo1VDaf9acpxSS6OObaWOvqPU+Tr0XEAepBFCEDMLDhcMKNRUOPZpZx4K8YFRGaKY717rPcVlb3Vx+8Az4dFp+gWiZpAOBEJ3pjVf9whaAORYw8PfJl+magwh1Pj2UMMUKlNXxi6hmAyfrxPc/V9T8WPJJJKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=rRlDaVqZ; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="rRlDaVqZ" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=iUDhu/ZGJnFLW++ZXEMrIwbiwMU6+cDB7edRKWs0gRc=; b=rRlDaVqZmUA8QNc0SgcyJqCyzs +U3L9pI/eCeaplP8s8RhSe+i0T2uZEpvjwmqgwaJ7ykTtac3fsW2EP8zlMKT8hmYIxnZ0TCR9Fg2O hGEMqvbzQsFQ2RrBJYuhL0f1Tq4KxuXpfSsQQLK1DzM8+sRFKr7QukejhKE4Hln23FextEJnK/PiQ eg6X3jdQlkf/yqCsWGN7Vt+7Zr4M3UUjWh0JRczogoJEmdBzEvpZxlz3UEIBVX0EHQmU+f4FXY1mM uShjs2ykBi2HCJhZxy30JsCWKiPIUcIfxc+hdvMysbIk3kJTPZxnRPLlnlqtSOGr6i1frg0UonRhp uzoy/+cA==; Received: from i5e860d0f.versanet.de ([94.134.13.15] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1smUHQ-0000jF-Al; Fri, 06 Sep 2024 10:25:20 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 4/5] clk: clk-gpio: add driver for gated-fixed-clocks Date: Fri, 6 Sep 2024 10:25:10 +0200 Message-ID: <20240906082511.2963890-5-heiko@sntech.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240906082511.2963890-1-heiko@sntech.de> References: <20240906082511.2963890-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In contrast to fixed clocks that are described as ungateable, boards sometimes use additional oscillators for things like PCIe reference clocks, that need actual supplies to get enabled and enable-gpios to be toggled for them to work. This adds a driver for those generic gated-fixed-clocks that can show up in schematics looking like ---------------- Enable - | 100MHz,3.3V, | - VDD | 3225 | GND - | | - OUT ---------------- The new driver gets grouped together with the existing gpio-gate and gpio-mux, as it for one re-uses a lot of the gpio-gate functions and also in its core it's just another gpio-controlled clock, just with a fixed rate and a regulator-supply added in. The regulator-API provides function stubs for the !CONFIG_REGULATOR case, so no special handling is necessary. Signed-off-by: Heiko Stuebner --- drivers/clk/clk-gpio.c | 186 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 186 insertions(+) diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index cda362a2eca0..3a215f91ad55 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -17,6 +17,7 @@ #include #include #include +#include /** * DOC: basic gpio gated clock which can be enabled and disabled @@ -239,3 +240,188 @@ static struct platform_driver gpio_clk_driver = { }, }; builtin_platform_driver(gpio_clk_driver); + +/** + * DOC: gated fixed clock, controlled with a gpio output and a regulator + * Traits of this clock: + * prepare - clk_prepare and clk_unprepare are function & control regulator + * optionally a gpio that can sleep + * enable - clk_enable and clk_disable are functional & control gpio + * rate - rate is fixed and set on clock registration + * parent - fixed clock is a root clock and has no parent + */ + +/** + * struct clk_gate_fixed - gated-fixed-clock + * + * clk_gpio: instance of clk_gpio for gate-gpio + * supply: supply regulator + * rate: fixed rate + */ +struct clk_gated_fixed { + struct clk_gpio clk_gpio; + struct regulator *supply; + unsigned long rate; +}; + +#define to_clk_gated_fixed(_clk_gpio) container_of(_clk_gpio, struct clk_gated_fixed, clk_gpio) + +static unsigned long clk_gated_fixed_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return to_clk_gated_fixed(to_clk_gpio(hw))->rate; +} + +static int clk_gated_fixed_prepare(struct clk_hw *hw) +{ + struct clk_gated_fixed *clk = to_clk_gated_fixed(to_clk_gpio(hw)); + + if (!clk->supply) + return 0; + + return regulator_enable(clk->supply); +} + +static void clk_gated_fixed_unprepare(struct clk_hw *hw) +{ + struct clk_gated_fixed *clk = to_clk_gated_fixed(to_clk_gpio(hw)); + + if (!clk->supply) + return; + + regulator_disable(clk->supply); +} + +static int clk_gated_fixed_is_prepared(struct clk_hw *hw) +{ + struct clk_gated_fixed *clk = to_clk_gated_fixed(to_clk_gpio(hw)); + + if (!clk->supply) + return true; + + return regulator_is_enabled(clk->supply); +} + +/* + * Fixed gated clock with non-sleeping gpio. + * + * Prepare operation turns on the supply regulator + * and the enable operation switches the enable-gpio. + */ +static const struct clk_ops clk_gated_fixed_ops = { + .prepare = clk_gated_fixed_prepare, + .unprepare = clk_gated_fixed_unprepare, + .is_prepared = clk_gated_fixed_is_prepared, + .enable = clk_gpio_gate_enable, + .disable = clk_gpio_gate_disable, + .is_enabled = clk_gpio_gate_is_enabled, + .recalc_rate = clk_gated_fixed_recalc_rate, +}; + +static int clk_sleeping_gated_fixed_prepare(struct clk_hw *hw) +{ + int ret; + + ret = clk_gated_fixed_prepare(hw); + if (ret) + return ret; + + ret = clk_sleeping_gpio_gate_prepare(hw); + if (ret) + clk_gated_fixed_unprepare(hw); + + return ret; +} + +static void clk_sleeping_gated_fixed_unprepare(struct clk_hw *hw) +{ + clk_gated_fixed_unprepare(hw); + clk_sleeping_gpio_gate_unprepare(hw); +} + +/* + * Fixed gated clock with non-sleeping gpio. + * + * Enabling the supply regulator and switching the enable-gpio happens + * both in the prepare step. + * is_prepared only needs to check the gpio state, as toggling the + * gpio is the last step when preparing. + */ +static const struct clk_ops clk_sleeping_gated_fixed_ops = { + .prepare = clk_sleeping_gated_fixed_prepare, + .unprepare = clk_sleeping_gated_fixed_unprepare, + .is_prepared = clk_sleeping_gpio_gate_is_prepared, + .recalc_rate = clk_gated_fixed_recalc_rate, +}; + +static int clk_gated_fixed_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk_gated_fixed *clk; + const struct clk_ops *ops; + const char *clk_name; + u32 rate; + int ret; + + clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); + if (!clk) + return -ENOMEM; + + ret = device_property_read_u32(dev, "clock-frequency", &rate); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clock-frequency\n"); + clk->rate = rate; + + ret = device_property_read_string(dev, "clock-output-names", &clk_name); + if (ret) + clk_name = fwnode_get_name(dev->fwnode); + + clk->supply = devm_regulator_get_optional(dev, "vdd"); + if (IS_ERR(clk->supply)) { + if (PTR_ERR(clk->supply) != -ENODEV) + return dev_err_probe(dev, PTR_ERR(clk->supply), + "Failed to get regulator\n"); + clk->supply = NULL; + } + + clk->clk_gpio.gpiod = devm_gpiod_get_optional(dev, "enable", + GPIOD_OUT_LOW); + if (IS_ERR(clk->clk_gpio.gpiod)) + return dev_err_probe(dev, PTR_ERR(clk->clk_gpio.gpiod), + "Failed to get gpio\n"); + + if (gpiod_cansleep(clk->clk_gpio.gpiod)) + ops = &clk_sleeping_gated_fixed_ops; + else + ops = &clk_gated_fixed_ops; + + clk->clk_gpio.hw.init = CLK_HW_INIT_NO_PARENT(clk_name, ops, 0); + + /* register the clock */ + ret = devm_clk_hw_register(dev, &clk->clk_gpio.hw); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register clock\n"); + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &clk->clk_gpio.hw); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register clock provider\n"); + + return 0; +} + +static const struct of_device_id gated_fixed_clk_match_table[] = { + { .compatible = "gated-fixed-clock" }, + { /* sentinel */ }, +}; + +static struct platform_driver gated_fixed_clk_driver = { + .probe = clk_gated_fixed_probe, + .driver = { + .name = "gated-fixed-clk", + .of_match_table = gated_fixed_clk_match_table, + }, +}; +builtin_platform_driver(gated_fixed_clk_driver); From patchwork Fri Sep 6 08:25:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 13793683 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 816AB1586CF; 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Received: from i5e860d0f.versanet.de ([94.134.13.15] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1smUHQ-0000jF-RE; Fri, 06 Sep 2024 10:25:20 +0200 From: Heiko Stuebner To: mturquette@baylibre.com, sboyd@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 5/5] arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX Date: Fri, 6 Sep 2024 10:25:11 +0200 Message-ID: <20240906082511.2963890-6-heiko@sntech.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240906082511.2963890-1-heiko@sntech.de> References: <20240906082511.2963890-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its SATA controller with 2 lanes each. The supply for the refclk oscillator is the same that supplies the M.2 slot, but the SATA controller port is supplied by a different rail. This leads to the effect that if the PCIe30x4 controller for the M.2 probes first, everything works normally. But if the PCIe30x2 controller that is connected to the SATA controller probes first, it will hang on the first DBI read as nothing will have enabled the refclock before. Fix this by describing the clock generator with its supplies so that both controllers can reference it as needed. Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5-itx.dts | 38 ++++++++++++++++++- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index d0b922b8d67e..2d0bcf90bf0f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -72,6 +72,15 @@ hdd-led2 { }; }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_05>; + }; + fan0: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; @@ -146,13 +155,14 @@ vcc3v3_lan: vcc3v3_lan_phy2: regulator-vcc3v3-lan { vin-supply = <&vcc_3v3_s3>; }; - vcc3v3_mkey: regulator-vcc3v3-mkey { + /* The PCIE30x4_PWREN_H controls two regulators */ + vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { compatible = "regulator-fixed"; enable-active-high; gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_pwren_h>; - regulator-name = "vcc3v3_mkey"; + regulator-name = "vcc3v3_pi6c_05"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <5000>; @@ -513,6 +523,18 @@ &pcie30phy { /* ASMedia ASM1164 Sata controller */ &pcie3x2 { + /* + * The board has a "pcie_refclk" oscillator that needs enabling, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>, + <&pcie30_port1_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2_perstn_m1_l>; reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; @@ -522,6 +544,18 @@ &pcie3x2 { /* M.2 M.key */ &pcie3x4 { + /* + * The board has a "pcie_refclk" oscillator that needs enabling, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie30_port0_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; num-lanes = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_perstn_m1_l>;