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Fri, 06 Sep 2024 06:09:33 -0700 (PDT) Received: from CWMV1S3.bytedance.net ([203.208.167.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-206aea55b05sm42764465ad.202.2024.09.06.06.09.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 06:09:33 -0700 (PDT) From: Haiwang Fu To: akpm@linux-foundation.org, ryan.roberts@arm.com, mark.rutland@arm.com, catalin.marinas@arm.com, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, fuhaiwang@bytedance.com Subject: [PATCH] mm/vmalloc:arm64 support cont-pte huge vmalloc mapping Date: Fri, 6 Sep 2024 21:09:19 +0800 Message-Id: <20240906130919.3765401-1-fuhaiwang@bytedance.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240906_060942_442243_7A5DFF55 X-CRM114-Status: GOOD ( 11.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: fuhaiwang Arm64 support contiguous bit which is used to increase the mapping size at the pmd and pte level. Now huge vmalloc support PMD and PTE level mapping, and support multi size at pte level. arm64: implement the fllowing interface on arm64 to support cont-pte huge vmalloc mapping. arch_vmap_pte_supported_shift(*) arch_vmap_pte_range_map_size(*) Signed-off-by: fuhaiwang --- arch/arm64/include/asm/pgtable.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index c329ea061dc9..3f32e3150680 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -1814,6 +1814,34 @@ static inline void clear_young_dirty_ptes(struct vm_area_struct *vma, #endif /* CONFIG_ARM64_CONTPTE */ +static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, unsigned long end, + u64 pfn, unsigned int max_page_shift) +{ + if (end - addr < CONT_PTE_SIZE) + return PAGE_SIZE; + + if ((1UL << max_page_shift) < CONT_PTE_SIZE) + return PAGE_SIZE; + + if (!IS_ALIGNED(addr, CONT_PTE_SIZE)) + return PAGE_SIZE; + + if (!IS_ALIGNED(PFN_PHYS(pfn), CONT_PTE_SIZE)) + return PAGE_SIZE; + + return CONT_PTE_SIZE; +} +#define arch_vmap_pte_range_map_size arch_vmap_pte_range_map_size + +static inline int arch_vmap_pte_supported_shift(unsigned long size) +{ + if (size >= CONT_PTE_SIZE) + return CONT_PTE_SHIFT; + else + return PAGE_SHIFT; +} +#define arch_vmap_pte_supported_shift arch_vmap_pte_supported_shift + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_PGTABLE_H */