From patchwork Fri Sep 6 16:59:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 13794467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D14B5E6FE34 for ; Fri, 6 Sep 2024 17:09:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KTx9T0QsthgtMWPrZGO+mOSHexmLZhoXS2lkiJJqmPw=; b=YV+hN/sJ2NSJziRC6e1bt7UZB4 XCXULeua0Vw11qOtgvTFzuGWEVvetTnZmVb3wqTglnW/g8zAzhvmq6+Kysgs4uT567pBR7toTpYsH VD0KercUUIbUA69SYbiMlUo4dEevsVOBDnvpmaAxgs/CgAj6et1H7Zo08V/G99m+lj+eftt3YjHUe 19+CNq+Y18eKYEC4cjMlMKn+RYkpChIsLQzulq7Qb8RV/A4KfJ0/ysjloj0laJ9Wsq3BBo00Gig1B zefxWogMRqPb2jOJCC9f+Q8oSWm+JuZmQdsYuD2WA1uVU1caleeEQNKilmyYfNw42dpiVm3a0fFSp skmxANIw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1smcSK-0000000D4IO-3c1i; Fri, 06 Sep 2024 17:09:08 +0000 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1smcQO-0000000D3jl-3KZi for linux-arm-kernel@lists.infradead.org; Fri, 06 Sep 2024 17:07:10 +0000 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-206bd1c6ccdso22417995ad.3 for ; Fri, 06 Sep 2024 10:07:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725642427; x=1726247227; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KTx9T0QsthgtMWPrZGO+mOSHexmLZhoXS2lkiJJqmPw=; b=l2n1n+xzc0ymdr/dILf+rWsRUYjj2J3kEcmgYTTA0xJAvIoU5XpKL1SDWPy0rno1wF AGz8N1hCM8N/7QbgD+o86outLOWwM0ARzE2NJ8c7SX+6KCmZA8LOxsTyj5cdKoyfrcab WErZjhZT09g+FBckGVdcurxF8BpMS74ldBH2AGMkJsGkezAFYsKqJl1sFkI6gVIZY1C+ FgjlUOBUtLPWbmQwshq9ZPcURZ6VCTJ88TIwiGIdZL27dhSkyg/nkzxNXG8hX8yqm7fD 3TIhhETBJztvCg4XFvu173R1z0NzSq/Xw6pZwRfzhuP5VaItKawLcC8iksvIwrkggBD/ 3i0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725642427; x=1726247227; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KTx9T0QsthgtMWPrZGO+mOSHexmLZhoXS2lkiJJqmPw=; b=uPWz3XQDxK9su/JXLMpILdILq34LfpWBu9tIeCTFV/uP3hesZVXOpUmvKd0t5bIijh W1dKyaMZ8nrfLuJVh0OIWZO5acL0RGc8wYwS3fCdeaQ0dZK+kUJtz1ZEblBwYGZd0Jzk aGZWnL/PRjJWXnzw4Np4HgSyKOToeifpCIDTpcRRWdLDuRuz6EuithOC2pz/PIxbK3M2 /Bj0u6CI3qXpAEvV+BmA1MHqRtsEn4ZZInAvzRBYEhBvObP9vgNe7zdGDPB1TUKLzvwy RjCVrq9+as+F0Rp8orJ39wRmroZ/9oGO+1suFM2AG7K53HXKr94lnsw74bYqb5yJdPQv j1NQ== X-Forwarded-Encrypted: i=1; AJvYcCWftMgt09+kNkqs/d+42GQOdLiW5sLMWWh6OWDer4spLKAMtWpK5o1gVPz8V8LUx3/6JSjhwByUdxnRIcOqk3mO@lists.infradead.org X-Gm-Message-State: AOJu0Yzq0Ns6Usfsw33PtavQKQFw9dsdkVnejb01/DWUkpcsL56WIsJL 0AWXohUIvsivb6fRkpfzUYonLEwc19dRuo4KTVjJi8RoSIMyu4sN X-Google-Smtp-Source: AGHT+IERTbesUX7/1yBRFhwFuSYJdRTeKIeNqOki4t1RHxe3gyPAAVRGKR0xZE0hpM1Bk0E8U8IsCQ== X-Received: by 2002:a17:902:d4c8:b0:206:9519:1821 with SMTP id d9443c01a7336-206f04e17admr29475445ad.14.1725642427514; Fri, 06 Sep 2024 10:07:07 -0700 (PDT) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-206ae965b58sm45317185ad.118.2024.09.06.10.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 10:07:07 -0700 (PDT) From: Nick Chan To: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: asahi@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nick Chan Subject: [PATCH 1/2] arm64: cputype: Add CPU types for A7-A11, T2 SoCs Date: Sat, 7 Sep 2024 00:59:38 +0800 Message-ID: <20240906170648.323759-2-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240906170648.323759-1-towinchenmi@gmail.com> References: <20240906170648.323759-1-towinchenmi@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240906_100708_861278_C36B1C7A X-CRM114-Status: GOOD ( 12.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A10(X), T2 types will be used soon, and the rest are added for documentation purposes. The A9 is made in two different fabs and those have different part numbers, and the TSMC cores are also used in A9X, so it cannot use the usual naming scheme. The A10(X), T2 performance/efficiency core pairs appears as single logical cores to software, so both the performance and efficiency core codenames needs to be included. Signed-off-by: Nick Chan --- arch/arm64/include/asm/cputype.h | 42 +++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 5a7dfeb8e8eb..f1720158a54f 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -129,18 +129,27 @@ #define HISI_CPU_PART_TSV110 0xD01 -#define APPLE_CPU_PART_M1_ICESTORM 0x022 -#define APPLE_CPU_PART_M1_FIRESTORM 0x023 -#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 -#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 -#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 -#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 -#define APPLE_CPU_PART_M2_BLIZZARD 0x032 -#define APPLE_CPU_PART_M2_AVALANCHE 0x033 -#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034 -#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035 -#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 -#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 +#define APPLE_CPU_PART_A7_CYCLONE 0x1 +#define APPLE_CPU_PART_A8_TYPHOON 0x2 +#define APPLE_CPU_PART_A8X_TYPHOON 0x3 +#define APPLE_CPU_PART_SAMSUNG_TWISTER 0x4 /* Used in Samsung A9 */ +#define APPLE_CPU_PART_TSMC_TWISTER 0x5 /* Used in TSMC A9 and A9X */ +#define APPLE_CPU_PART_A10_T2_HURRICANE_ZEPHYR 0x6 +#define APPLE_CPU_PART_A10X_HURRICANE_ZEPHYR 0x7 +#define APPLE_CPU_PART_A11_MONSOON 0x8 +#define APPLE_CPU_PART_A11_MISTRAL 0x9 +#define APPLE_CPU_PART_M1_ICESTORM 0x022 +#define APPLE_CPU_PART_M1_FIRESTORM 0x023 +#define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024 +#define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025 +#define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028 +#define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029 +#define APPLE_CPU_PART_M2_BLIZZARD 0x032 +#define APPLE_CPU_PART_M2_AVALANCHE 0x033 +#define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034 +#define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035 +#define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 +#define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 #define AMPERE_CPU_PART_AMPERE1 0xAC3 #define AMPERE_CPU_PART_AMPERE1A 0xAC4 @@ -200,6 +209,15 @@ #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) +#define MIDR_APPLE_A7_CYCLONE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A7_CYCLONE) +#define MIDR_APPLE_A8_TYPHOON MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A8_TYPHOON) +#define MIDR_APPLE_A8X_TYPHOON MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A8X_TYPHOON) +#define MIDR_APPLE_SAMSUNG_TWISTER MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_SAMSUNG_TWISTER) +#define MIDR_APPLE_TSMC_TWISTER MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_TSMC_TWISTER) +#define MIDR_APPLE_A10_T2_HURRICANE_ZEPHYR MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A10_T2_HURRICANE_ZEPHYR) +#define MIDR_APPLE_A10X_HURRICANE_ZEPHYR MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A10X_HURRICANE_ZEPHYR) +#define MIDR_APPLE_A11_MONSOON MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A11_MONSOON) +#define MIDR_APPLE_A11_MISTRAL MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_A11_MISTRAL) #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO) From patchwork Fri Sep 6 16:59:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 13794468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C0F4E6FE33 for ; Fri, 6 Sep 2024 17:10:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=C2Awb8QHiwgK4hQKj8EI8RJlryPJ8iCefANxC9lVPtM=; b=m+lS6eOfUGQL/2MMHNxNF6i+Qz ciIVFZfWk7BuD0iKCBO4b6kSs3/bGv5MqTrpJyzzUdjAhu8beZv5jmTfbbllJsVl64nfXoAW8Z+SI mg7XqZ8cBTDj44aa9DUhevQ9puFEkBensIPN6ernn5GhlUQGLocorQqle2R51KPR+op/532e0gwb0 aZMuKk24dCTZvO30JbYD2ABLhOdsssb4zi90r/7GnEmyOkO0RQ0go7ZyE4kw7IybW/8JOiYHQbVgO ESORY1n6v6VzUk1EFsKwep2blL2yzEZHAvDB7JeF6hHoJNU1eJspulMhROW6p1OhdqtZ/8IUPDVOU bTQ7DSgw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1smcTI-0000000D4Ra-0Qln; Fri, 06 Sep 2024 17:10:08 +0000 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1smcQS-0000000D3lo-3Iyn for linux-arm-kernel@lists.infradead.org; Fri, 06 Sep 2024 17:07:14 +0000 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-20551e2f1f8so22832465ad.2 for ; Fri, 06 Sep 2024 10:07:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725642432; x=1726247232; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C2Awb8QHiwgK4hQKj8EI8RJlryPJ8iCefANxC9lVPtM=; b=jc2q3rJ2yzweAHxBTKJhUb5xJIBXDYmDXCoQPoHPhb5O8AR+880AZ6L3J9DpvxnaC0 zF/qrrs4M5agsH14lsz4X04ybRQgu0gf3jMNVSmrTX7G+gfhz5JTfEFELIj29BFHddi0 27p/zOWG4Nq/U2ZmWBrsGbdCBYYXDDlz/1vpmyVGTRsKljGh10fKNOXPKt/vl4Nk9/f8 F41xnDH5tb5fxAwB0kDR/1Qz+wk2JEX3j1vnGSU9/un2hteQaOlBYUw7qynKizPayW0e mhoLjzC81Em7KCcOQOkAGrJGBNrBO+63enXUAmItkw4C/luH1FlGkvejIJnZ6PmEmFF3 SmAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725642432; x=1726247232; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C2Awb8QHiwgK4hQKj8EI8RJlryPJ8iCefANxC9lVPtM=; b=IBOyMVBz0swZ/hUazvgAGjYXgQUZCfZpy2Hw1yBVqpO/le7mxwmqic6etH+y+znTH5 kA6/6UVKPsiTx1YK0pyqyDELigNLeXLcre+C9DrfqiXPAAbhICRFxBo6ioXoIY2lmFAq +B+aQ1hzxmS0vFo7ueeIK6Bbk7GnsQ1inGb0AZYeFVIJa+4ChZP0LrZ2Lr9OC1TTzIax Yd2v6VgzOVoON7l1hiFOBisiyh8EaKt26FQaT8BpgVpp6IDjrpIuvNSoKfwE6JEidXQ6 7rrpmHn2c8f8mBfRtAa/fwbLl9B4mygFaYFnAhhjJjD4lgxzvGl+s/NGTz+jQE6u19im 9mPg== X-Forwarded-Encrypted: i=1; AJvYcCW3F7us8RViw84pU+3pm6yq/YK9RYaywJpg460SCVTQKnaGepbdj2179kQ2u9RDUCNcCNbgvXwSQBt4/cC4rILm@lists.infradead.org X-Gm-Message-State: AOJu0YyEdq6Z8c5oAWMohkF26EkjRVSI+TGs/zq97yt8WpZH7+DlmUYL pXACM30ieo6dXbgiNS65KIB5ptSulbPh48rnEjxIboKM1Qo6TaRT X-Google-Smtp-Source: AGHT+IFzWBC72QoGzj8kbBobKI6Ww4r0XzwjrJiOcmr9ev3ZyRUXQKrGkjvpbp2VTVfHowtN+JDMZQ== X-Received: by 2002:a17:902:da92:b0:205:6c5f:e3ca with SMTP id d9443c01a7336-206f05faf58mr27842755ad.53.1725642431812; Fri, 06 Sep 2024 10:07:11 -0700 (PDT) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-206ae965b58sm45317185ad.118.2024.09.06.10.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 10:07:11 -0700 (PDT) From: Nick Chan To: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: asahi@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nick Chan Subject: [PATCH 2/2] arm64: cpufeature: Pretend that Apple A10(X), T2 does not support 32-bit EL0 Date: Sat, 7 Sep 2024 00:59:39 +0800 Message-ID: <20240906170648.323759-3-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240906170648.323759-1-towinchenmi@gmail.com> References: <20240906170648.323759-1-towinchenmi@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240906_100712_904510_9069989D X-CRM114-Status: GOOD ( 14.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Apple A10(X), T2 consists of logical cores that can switch between P-mode and E-mode based on the frequency. However, only P-mode supported 32-bit EL0. Trying to support 32-bit EL0 on a CPU that can only execute it in certain states is a bad idea. The A10(X), T2 only supports 16KB page size anyway so many AArch32 executables won't run anyways. Pretend that it does not support 32-bit EL0 at all. Signed-off-by: Nick Chan --- arch/arm64/kernel/cpufeature.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 718728a85430..458bcbc4f328 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3529,6 +3529,29 @@ void __init setup_boot_cpu_features(void) setup_boot_cpu_capabilities(); } +static void __init bad_aarch32_el0_fixup(void) +{ +#ifdef CONFIG_ARCH_APPLE + static const struct midr_range bad_aarch32_el0[] = { + MIDR_ALL_VERSIONS(MIDR_APPLE_A10_T2_HURRICANE_ZEPHYR), + MIDR_ALL_VERSIONS(MIDR_APPLE_A10X_HURRICANE_ZEPHYR), + {} + }; + + if (is_midr_in_range_list(read_cpuid_id(), bad_aarch32_el0)) { + struct arm64_ftr_reg *regp; + + regp = get_arm64_ftr_reg(SYS_ID_AA64PFR0_EL1); + if (!regp) + return; + u64 val = (regp->sys_val & ~ID_AA64PFR0_EL1_EL0_MASK) + | ID_AA64PFR0_EL1_EL0_IMP; + + update_cpu_ftr_reg(regp, val); + } +#endif +} + static void __init setup_system_capabilities(void) { /* @@ -3562,6 +3585,8 @@ static void __init setup_system_capabilities(void) void __init setup_system_features(void) { + bad_aarch32_el0_fixup(); + setup_system_capabilities(); kpti_install_ng_mappings();