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Fri, 6 Sep 2024 19:14:43 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 41bv8mxy1h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2024 19:14:43 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 486JEgbr013060; Fri, 6 Sep 2024 19:14:42 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.213.110.207]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 486JEgai013059 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2024 19:14:42 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 429934) id AA3DE24186; Sat, 7 Sep 2024 00:44:41 +0530 (+0530) From: Mukesh Kumar Savaliya To: konrad.dybcio@linaro.org, andersson@kernel.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, conor+dt@kernel.org, agross@kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org, linux@treblig.org, dan.carpenter@linaro.org, Frank.Li@nxp.com, konradybcio@kernel.org Cc: quic_vdadhani@quicinc.com, Mukesh Kumar Savaliya Subject: [PATCH v2 1/4] dt-bindindgs: i2c: qcom,i2c-geni: Document shared flag Date: Sat, 7 Sep 2024 00:44:35 +0530 Message-Id: <20240906191438.4104329-2-quic_msavaliy@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240906191438.4104329-1-quic_msavaliy@quicinc.com> References: <20240906191438.4104329-1-quic_msavaliy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: sXxg6jZ62EotY6s4uyvpkLZKfr5lCXrx X-Proofpoint-GUID: sXxg6jZ62EotY6s4uyvpkLZKfr5lCXrx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_04,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409060141 Adds qcom,shared-se flag usage. Use this when particular I2C serial controller needs to be shared between two subsystems. SE = Serial Engine, meant for I2C controller here. TRE = Transfer Ring Element, refers to Queued Descriptor. Example : Two clients from different SS can share an I2C SE for same slave device OR their owned slave devices. Assume I2C Slave EEPROM device connected with I2C controller. Each client from ADSP SS and APPS Linux SS can perform i2c transactions. This gets serialized by lock TRE + DMA Transfers + Unlock TRE at HW level. Signed-off-by: Mukesh Kumar Savaliya --- Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index 9f66a3bb1f80..ae423127f736 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -60,6 +60,10 @@ properties: power-domains: maxItems: 1 + qcom,shared-se: + description: True if I2C needs to be shared between two or more subsystems. + type: boolean + reg: maxItems: 1 From patchwork Fri Sep 6 19:14:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Kumar Savaliya X-Patchwork-Id: 13794697 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 507961D2780; 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Fri, 06 Sep 2024 19:14:55 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 486JEhDc013068; Fri, 6 Sep 2024 19:14:52 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 41bv8mxy2b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2024 19:14:52 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 486JEpEG013100; Fri, 6 Sep 2024 19:14:51 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.213.110.207]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 486JEpQ4013099 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2024 19:14:51 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 429934) id 91D4D240F3; Sat, 7 Sep 2024 00:44:50 +0530 (+0530) From: Mukesh Kumar Savaliya To: konrad.dybcio@linaro.org, andersson@kernel.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, conor+dt@kernel.org, agross@kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org, linux@treblig.org, dan.carpenter@linaro.org, Frank.Li@nxp.com, konradybcio@kernel.org Cc: quic_vdadhani@quicinc.com, Mukesh Kumar Savaliya Subject: [PATCH v2 2/4] dma: gpi: Add Lock and Unlock TRE support to access SE exclusively Date: Sat, 7 Sep 2024 00:44:36 +0530 Message-Id: <20240906191438.4104329-3-quic_msavaliy@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240906191438.4104329-1-quic_msavaliy@quicinc.com> References: <20240906191438.4104329-1-quic_msavaliy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: qacERFxV8NF3UoCz9nw5v33i2Cz7TMLO X-Proofpoint-GUID: qacERFxV8NF3UoCz9nw5v33i2Cz7TMLO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_04,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409060141 GSI DMA provides specific TREs namely Lock and Unlock TRE, which provides mutual exclusive access to SE from any of the subsystem (E.g. Apps, TZ, ADSP etc). Lock prevents other subsystems from concurrently performing DMA transfers and avoids disturbance to data path. Basically lock the SE for particular subsystem, complete the transfer, unlock the SE. Apply Lock TRE for the first transfer of shared SE and Apply Unlock TRE for the last transfer. Also change MAX_TRE macro to 5 from 3 because of the two additional TREs. TRE = Tranfser Ring Element, refers to the queued descriptor. Signed-off-by: Mukesh Kumar Savaliya --- drivers/dma/qcom/gpi.c | 37 +++++++++++++++++++++++++++++++- include/linux/dma/qcom-gpi-dma.h | 6 ++++++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index e6ebd688d746..ba11b2641ab6 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020, Linaro Limited + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -65,6 +66,14 @@ /* DMA TRE */ #define TRE_DMA_LEN GENMASK(23, 0) +/* Lock TRE */ +#define TRE_I2C_LOCK BIT(0) +#define TRE_MINOR_TYPE GENMASK(19, 16) +#define TRE_MAJOR_TYPE GENMASK(23, 20) + +/* Unlock TRE */ +#define TRE_I2C_UNLOCK BIT(8) + /* Register offsets from gpi-top */ #define GPII_n_CH_k_CNTXT_0_OFFS(n, k) (0x20000 + (0x4000 * (n)) + (0x80 * (k))) #define GPII_n_CH_k_CNTXT_0_EL_SIZE GENMASK(31, 24) @@ -516,7 +525,7 @@ struct gpii { bool ieob_set; }; -#define MAX_TRE 3 +#define MAX_TRE 5 struct gpi_desc { struct virt_dma_desc vd; @@ -1637,6 +1646,19 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, struct gpi_tre *tre; unsigned int i; + /* create lock tre for first tranfser */ + if (i2c->shared_se && i2c->first_msg) { + tre = &desc->tre[tre_idx]; + tre_idx++; + + tre->dword[0] = 0; + tre->dword[1] = 0; + tre->dword[2] = 0; + tre->dword[3] = u32_encode_bits(1, TRE_I2C_LOCK); + tre->dword[3] |= u32_encode_bits(0, TRE_MINOR_TYPE); + tre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE); + } + /* first create config tre if applicable */ if (i2c->set_config) { tre = &desc->tre[tre_idx]; @@ -1695,6 +1717,19 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); } + /* Unlock tre for last transfer */ + if (i2c->shared_se && i2c->last_msg && i2c->op != I2C_READ) { + tre = &desc->tre[tre_idx]; + tre_idx++; + + tre->dword[0] = 0; + tre->dword[1] = 0; + tre->dword[2] = 0; + tre->dword[3] = u32_encode_bits(1, TRE_I2C_UNLOCK); + tre->dword[3] |= u32_encode_bits(1, TRE_MINOR_TYPE); + tre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE); + } + for (i = 0; i < tre_idx; i++) dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]); diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-dma.h index 6680dd1a43c6..8589c711afae 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -65,6 +65,9 @@ enum i2c_op { * @rx_len: receive length for buffer * @op: i2c cmd * @muli-msg: is part of multi i2c r-w msgs + * @shared_se: bus is shared between subsystems + * @bool first_msg: use it for tracking multimessage xfer + * @bool last_msg: use it for tracking multimessage xfer */ struct gpi_i2c_config { u8 set_config; @@ -78,6 +81,9 @@ struct gpi_i2c_config { u32 rx_len; enum i2c_op op; bool multi_msg; + bool shared_se; + bool first_msg; + bool last_msg; }; #endif /* QCOM_GPI_DMA_H */ From patchwork Fri Sep 6 19:14:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Kumar Savaliya X-Patchwork-Id: 13794698 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 012C41D2780; Fri, 6 Sep 2024 19:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725650112; cv=none; b=NIq21Bb//XEAZkjfN1YLUczUplH0bkFIUO0IlWKP6cJGWp4/nj2xQOZfXaru9rHIeajo8NK8mbnB8IVg2G6PAEENBw6bKTQiemHtezgC/ifaL3AQ7kFDLNruxtsYJe4UYJu2sJekkWAKFrXDH6cIGdHj+/Ax+10dQYnFmaaZU3M= ARC-Message-Signature: i=1; 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Fri, 6 Sep 2024 19:15:00 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 41bv8mxy2y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2024 19:14:59 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 486JExuV013140; Fri, 6 Sep 2024 19:14:59 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.213.110.207]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 486JExLs013137 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2024 19:14:59 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 429934) id 6CEE624186; Sat, 7 Sep 2024 00:44:58 +0530 (+0530) From: Mukesh Kumar Savaliya To: konrad.dybcio@linaro.org, andersson@kernel.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, conor+dt@kernel.org, agross@kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org, linux@treblig.org, dan.carpenter@linaro.org, Frank.Li@nxp.com, konradybcio@kernel.org Cc: quic_vdadhani@quicinc.com, Mukesh Kumar Savaliya Subject: [PATCH v2 3/4] soc: qcom: geni-se: Export function geni_se_clks_off() Date: Sat, 7 Sep 2024 00:44:37 +0530 Message-Id: <20240906191438.4104329-4-quic_msavaliy@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240906191438.4104329-1-quic_msavaliy@quicinc.com> References: <20240906191438.4104329-1-quic_msavaliy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Xzlg97264dNVa-vEgMwWXT4761v1KjnX X-Proofpoint-GUID: Xzlg97264dNVa-vEgMwWXT4761v1KjnX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_04,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409060141 Currently the driver provides a function called geni_serial_resources_off() to turn off resources like clocks and pinctrl. We don't have a function to control clocks separately hence, export the function geni_se_clks_off() to turn off clocks separately without disturbing GPIO. Client drivers like I2C require this function for use-cases where the I2C SE is shared between two subsystems. Signed-off-by: Mukesh Kumar Savaliya --- drivers/soc/qcom/qcom-geni-se.c | 4 +++- include/linux/soc/qcom/geni-se.h | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 2e8f24d5da80..20166c8fc919 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +// Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ #define __DISABLE_TRACE_MMIO__ @@ -482,13 +483,14 @@ void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, } EXPORT_SYMBOL_GPL(geni_se_config_packing); -static void geni_se_clks_off(struct geni_se *se) +void geni_se_clks_off(struct geni_se *se) { struct geni_wrapper *wrapper = se->wrapper; clk_disable_unprepare(se->clk); clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); } +EXPORT_SYMBOL_GPL(geni_se_clks_off); /** * geni_se_resources_off() - Turn off resources associated with the serial diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 0f038a1a0330..caf2c0c4505b 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _LINUX_QCOM_GENI_SE @@ -494,6 +495,8 @@ int geni_se_resources_off(struct geni_se *se); int geni_se_resources_on(struct geni_se *se); +void geni_se_clks_off(struct geni_se *se); + int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl); int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, From patchwork Fri Sep 6 19:14:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Kumar Savaliya X-Patchwork-Id: 13794699 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30E7113B584; Fri, 6 Sep 2024 19:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Fri, 06 Sep 2024 19:15:27 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 486JEphf013106; Fri, 6 Sep 2024 19:15:08 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 41bv8mxy5d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2024 19:15:08 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 486JF7vu013798; Fri, 6 Sep 2024 19:15:07 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.213.110.207]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 486JF7fS013791 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 06 Sep 2024 19:15:07 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 429934) id 8AAEE240F3; Sat, 7 Sep 2024 00:45:06 +0530 (+0530) From: Mukesh Kumar Savaliya To: konrad.dybcio@linaro.org, andersson@kernel.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, conor+dt@kernel.org, agross@kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org, linux@treblig.org, dan.carpenter@linaro.org, Frank.Li@nxp.com, konradybcio@kernel.org Cc: quic_vdadhani@quicinc.com, Mukesh Kumar Savaliya Subject: [PATCH v2 4/4] i2c: i2c-qcom-geni: Enable i2c controller sharing between two subsystems Date: Sat, 7 Sep 2024 00:44:38 +0530 Message-Id: <20240906191438.4104329-5-quic_msavaliy@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240906191438.4104329-1-quic_msavaliy@quicinc.com> References: <20240906191438.4104329-1-quic_msavaliy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: CtMxmfcneIp82Sx1nyZUES6IfpRXLTk0 X-Proofpoint-GUID: CtMxmfcneIp82Sx1nyZUES6IfpRXLTk0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_04,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409060142 Add support to share I2C SE by two Subsystems in a mutually exclusive way. Use "qcom,shared-se" flag in a particular i2c instance node if the usecase requires i2c controller to be shared. I2C driver just need to mark first_msg and last_msg flag to help indicate GPI driver to take lock and unlock TRE there by protecting from concurrent access from other EE or Subsystem. gpi_create_i2c_tre() function at gpi.c will take care of adding Lock and Unlock TRE for the respective transfer operations. Since the GPIOs are also shared for the i2c bus between two SS, do not touch GPIO configuration during runtime suspend and only turn off the clocks. This will allow other SS to continue to transfer the data without any disturbance over the IO lines. Signed-off-by: Mukesh Kumar Savaliya --- drivers/i2c/busses/i2c-qcom-geni.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index eebb0cbb6ca4..ee2e431601a6 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +// Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. #include #include @@ -99,6 +100,7 @@ struct geni_i2c_dev { struct dma_chan *rx_c; bool gpi_mode; bool abort_done; + bool is_shared; }; struct geni_i2c_desc { @@ -602,6 +604,7 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], i peripheral.clk_div = itr->clk_div; peripheral.set_config = 1; peripheral.multi_msg = false; + peripheral.shared_se = gi2c->is_shared; for (i = 0; i < num; i++) { gi2c->cur = &msgs[i]; @@ -612,6 +615,8 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], i if (i < num - 1) peripheral.stretch = 1; + peripheral.first_msg = (i == 0); + peripheral.last_msg = (i == num - 1); peripheral.addr = msgs[i].addr; ret = geni_i2c_gpi(gi2c, &msgs[i], &config, @@ -631,8 +636,11 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], i dma_async_issue_pending(gi2c->tx_c); time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); - if (!time_left) + if (!time_left) { + dev_err(gi2c->se.dev, "I2C timeout gpi flags:%d addr:0x%x\n", + gi2c->cur->flags, gi2c->cur->addr); gi2c->err = -ETIMEDOUT; + } if (gi2c->err) { ret = gi2c->err; @@ -800,6 +808,11 @@ static int geni_i2c_probe(struct platform_device *pdev) gi2c->clk_freq_out = KHZ(100); } + if (of_property_read_bool(pdev->dev.of_node, "qcom,shared-se")) { + gi2c->is_shared = true; + dev_dbg(&pdev->dev, "Shared SE Usecase\n"); + } + if (has_acpi_companion(dev)) ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); @@ -962,14 +975,16 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); disable_irq(gi2c->irq); - ret = geni_se_resources_off(&gi2c->se); - if (ret) { - enable_irq(gi2c->irq); - return ret; - + if (gi2c->is_shared) { + geni_se_clks_off(&gi2c->se); } else { - gi2c->suspended = 1; + ret = geni_se_resources_off(&gi2c->se); + if (ret) { + enable_irq(gi2c->irq); + return ret; + } } + gi2c->suspended = 1; clk_disable_unprepare(gi2c->core_clk);