From patchwork Mon Sep 9 09:26:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 13796552 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2FE71B142F; Mon, 9 Sep 2024 09:32:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725874350; cv=none; b=JFqXWdO4RyrrsmWRD/ENzKh9PYbITS1tunnBUaXrO853aGsV63YUBS7oydTFnYw60waz8aFvqxvbpdhQqt+tn9WvdIqbQrzBMfSvVwRSSojR4vNG218i3pFJ32I1GCCYciLptMoNNmwXb17MXSz8M9b5PA7h7ED1NqgTVOCj5Fg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725874350; c=relaxed/simple; bh=hKCQYKKvrT0BTjC1HdEelx0g32L60/TI+ek06m8hv3o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NI/ysuLcYf33+Anglw7mEc6cXOgUMWmGxVWsf4rnCUt+UMPwWnOe0gEA+4jhCzYWRaBodo3NtI+rhL/D4wcImmc4L8EKaptr+NER0XL1j/mFvD/mWU3+U02vwF1iSQecA6+lZq2OZ21xrtNa4EJ8ofrRGWX5FqU+O0T2gfWhIUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Mjl3piMY; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Mjl3piMY" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4899KOfl030931; Mon, 9 Sep 2024 09:27:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kIxJpoKToWHEk37OVZzpMmSUqmveUzu6daAQAhHwmcA=; b=Mjl3piMYQCeMESDD WbV4/qyKG9aY+mtum86gNRS6FdvJNVyMX3CZf1rH5hU5aznDeRK+SBo2A1W3qb4d rN4L92lKTwujrhgjf4q21sEI0SQN39NoAJljtt6iZzcVRAg9tegEgGps3WgBEy1H unYFmYPwzVNbM8Gfzr/QFXmdzo7h7kO261bQSOjtzv2uti2FoBVatB2uAiW9318r Hy9nVmnprr2TH3XVO7KY+klHY4va629JJV90bfXYqMBTygCxdJbRYagNrusORz+Z GdlKQX6hNbQiObt3urW/yGHLJObBK7wiO8o+oNZFGLWjS1C479PuZFIJ69Aowe+G Bmm0Sg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 41gy59tchc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 09 Sep 2024 09:27:15 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4899RFWI002765 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Sep 2024 09:27:15 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Sep 2024 02:27:09 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 01/11] dmaengine: qcom: bam_dma: Add bam_sw_version register read Date: Mon, 9 Sep 2024 14:56:22 +0530 Message-ID: <20240909092632.2776160-2-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240909092632.2776160-1-quic_mdalam@quicinc.com> References: <20240909092632.2776160-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: pfoZM60noFcL-rk-T8BV_qFo2r_4aOMX X-Proofpoint-ORIG-GUID: pfoZM60noFcL-rk-T8BV_qFo2r_4aOMX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 bulkscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 clxscore=1015 adultscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409090074 Add bam_sw_version register read. This will help to differentiate b/w some new BAM features across multiple BAM IP, feature like LOCK/UNLOCK of BAM pipe. Signed-off-by: Md Sadre Alam --- change in [v4] * Added BAM_SW_VERSION register read change in [v3] * This patch was not included in [v3] change in [v2] * This patch was not included in [v2] change in [v1] * This patch was not included in [v1] drivers/dma/qcom/bam_dma.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index d43a881e43b9..3a2965939531 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -80,6 +80,7 @@ struct bam_async_desc { enum bam_reg { BAM_CTRL, BAM_REVISION, + BAM_SW_VERSION, BAM_NUM_PIPES, BAM_DESC_CNT_TRSHLD, BAM_IRQ_SRCS, @@ -114,6 +115,7 @@ struct reg_offset_data { static const struct reg_offset_data bam_v1_3_reg_info[] = { [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 }, [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 }, + [BAM_SW_VERSION] = { 0x0F88, 0x00, 0x00, 0x00 }, [BAM_NUM_PIPES] = { 0x0FBC, 0x00, 0x00, 0x00 }, [BAM_DESC_CNT_TRSHLD] = { 0x0F88, 0x00, 0x00, 0x00 }, [BAM_IRQ_SRCS] = { 0x0F8C, 0x00, 0x00, 0x00 }, @@ -143,6 +145,7 @@ static const struct reg_offset_data bam_v1_3_reg_info[] = { static const struct reg_offset_data bam_v1_4_reg_info[] = { [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 }, + [BAM_SW_VERSION] = { 0x0008, 0x00, 0x00, 0x00 }, [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 }, [BAM_DESC_CNT_TRSHLD] = { 0x0008, 0x00, 0x00, 0x00 }, [BAM_IRQ_SRCS] = { 0x000C, 0x00, 0x00, 0x00 }, @@ -172,6 +175,7 @@ static const struct reg_offset_data bam_v1_4_reg_info[] = { static const struct reg_offset_data bam_v1_7_reg_info[] = { [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 }, [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 }, + [BAM_SW_VERSION] = { 0x01004, 0x00, 0x00, 0x00 }, [BAM_NUM_PIPES] = { 0x01008, 0x00, 0x00, 0x00 }, [BAM_DESC_CNT_TRSHLD] = { 0x00008, 0x00, 0x00, 0x00 }, [BAM_IRQ_SRCS] = { 0x03010, 0x00, 0x00, 0x00 }, @@ -390,6 +394,7 @@ struct bam_device { bool controlled_remotely; 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Mon, 09 Sep 2024 09:27:20 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4899RK56002807 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Sep 2024 09:27:20 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Sep 2024 02:27:15 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 02/11] dmaengine: qcom: bam_dma: add LOCK & UNLOCK flag support Date: Mon, 9 Sep 2024 14:56:23 +0530 Message-ID: <20240909092632.2776160-3-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240909092632.2776160-1-quic_mdalam@quicinc.com> References: <20240909092632.2776160-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TzvIPbOpt_S89LUvXp6DBHaQSgf_8Gwo X-Proofpoint-GUID: TzvIPbOpt_S89LUvXp6DBHaQSgf_8Gwo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxscore=0 phishscore=0 bulkscore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409090074 Add lock and unlock flag support on command descriptor. Once lock set in requester pipe, then the bam controller will lock all others pipe and process the request only from requester pipe. Unlocking only can be performed from the same pipe. If DMA_PREP_LOCK flag passed in command descriptor then requester of this transaction wanted to lock the BAM controller for this transaction so BAM driver should set LOCK bit for the HW descriptor. If DMA_PREP_UNLOCK flag passed in command descriptor then requester of this transaction wanted to unlock the BAM controller.so BAM driver should set UNLOCK bit for the HW descriptor. BAM IP version 1.4.0 and above only supports this LOCK/UNLOCK feature. So adding check for the same and setting bam_pipe_lock based on BAM SW Version. Signed-off-by: Md Sadre Alam --- Change in [v4] * Added BAM_SW_VERSION read for major & minor version * Added bam_pipe_lock flag Change in [v3] * Moved lock/unlock bit set inside loop Change in [v2] * No change Change in [v1] * Added initial support for BAM pipe lock/unlock drivers/dma/qcom/bam_dma.c | 25 ++++++++++++++++++++++++- include/linux/dmaengine.h | 6 ++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 3a2965939531..d30416a26d8e 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -53,11 +53,20 @@ struct bam_desc_hw { #define BAM_DMA_AUTOSUSPEND_DELAY 100 +#define SW_VERSION_MAJOR_SHIFT 28 +#define SW_VERSION_MINOR_SHIFT 16 +#define SW_VERSION_MAJOR_MASK (0xf << SW_VERSION_MAJOR_SHIFT) +#define SW_VERSION_MINOR_MASK 0xf +#define SW_MAJOR_1 0x1 +#define SW_VERSION_4 0x4 + #define DESC_FLAG_INT BIT(15) #define DESC_FLAG_EOT BIT(14) #define DESC_FLAG_EOB BIT(13) #define DESC_FLAG_NWD BIT(12) #define DESC_FLAG_CMD BIT(11) +#define DESC_FLAG_LOCK BIT(10) +#define DESC_FLAG_UNLOCK BIT(9) struct bam_async_desc { struct virt_dma_desc vd; @@ -393,6 +402,7 @@ struct bam_device { u32 ee; bool controlled_remotely; bool powered_remotely; + bool bam_pipe_lock; u32 active_channels; u32 bam_sw_version; @@ -696,9 +706,15 @@ static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, unsigned int curr_offset = 0; do { - if (flags & DMA_PREP_CMD) + if (flags & DMA_PREP_CMD) { desc->flags |= cpu_to_le16(DESC_FLAG_CMD); + if (bdev->bam_pipe_lock && flags & DMA_PREP_LOCK) + desc->flags |= cpu_to_le16(DESC_FLAG_LOCK); + else if (bdev->bam_pipe_lock && flags & DMA_PREP_UNLOCK) + desc->flags |= cpu_to_le16(DESC_FLAG_UNLOCK); + } + desc->addr = cpu_to_le32(sg_dma_address(sg) + curr_offset); @@ -1242,6 +1258,7 @@ static int bam_dma_probe(struct platform_device *pdev) { struct bam_device *bdev; const struct of_device_id *match; + u32 sw_major, sw_minor; int ret, i; bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL); @@ -1305,6 +1322,12 @@ static int bam_dma_probe(struct platform_device *pdev) bdev->bam_sw_version = readl_relaxed(bam_addr(bdev, 0, BAM_SW_VERSION)); dev_info(bdev->dev, "BAM software version:0x%08x\n", bdev->bam_sw_version); + sw_major = (bdev->bam_sw_version & SW_VERSION_MAJOR_MASK) >> SW_VERSION_MAJOR_SHIFT; + sw_minor = (bdev->bam_sw_version >> SW_VERSION_MINOR_SHIFT) & SW_VERSION_MINOR_MASK; + + if (sw_major == SW_MAJOR_1 && sw_minor >= SW_VERSION_4) + bdev->bam_pipe_lock = true; + ret = bam_init(bdev); if (ret) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index b137fdb56093..70f23068bfdc 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -200,6 +200,10 @@ struct dma_vec { * transaction is marked with DMA_PREP_REPEAT will cause the new transaction * to never be processed and stay in the issued queue forever. The flag is * ignored if the previous transaction is not a repeated transaction. + * @DMA_PREP_LOCK: tell the driver that there is a lock bit set on command + * descriptor. + * @DMA_PREP_UNLOCK: tell the driver that there is a un-lock bit set on command + * descriptor. */ enum dma_ctrl_flags { DMA_PREP_INTERRUPT = (1 << 0), @@ -212,6 +216,8 @@ enum dma_ctrl_flags { DMA_PREP_CMD = (1 << 7), DMA_PREP_REPEAT = (1 << 8), DMA_PREP_LOAD_EOT = (1 << 9), + DMA_PREP_LOCK = (1 << 10), + DMA_PREP_UNLOCK = (1 << 11), }; /** From patchwork Mon Sep 9 09:26:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 13796531 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 329081B375C; Mon, 9 Sep 2024 09:27:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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This will use for command descriptor support for crypto register r/w via BAM/DMA. Signed-off-by: Md Sadre Alam --- Change in [v4] * Added error handling path for dma_map_resource() Change in [v3] * Added dma_unmap_resource() in qce_crypto_remove() Change in [v2] * Added crypto added read from device tree Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/core.c | 14 ++++++++++++-- drivers/crypto/qce/core.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index 28b5fd823827..2236a057f45c 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -192,6 +192,7 @@ static int qce_crypto_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct qce_device *qce; + struct resource *res; int ret; qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL); @@ -201,7 +202,7 @@ static int qce_crypto_probe(struct platform_device *pdev) qce->dev = dev; platform_set_drvdata(pdev, qce); - qce->base = devm_platform_ioremap_resource(pdev, 0); + qce->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(qce->base)) return PTR_ERR(qce->base); @@ -261,7 +262,12 @@ static int qce_crypto_probe(struct platform_device *pdev) if (ret) goto err_dma; - return 0; + qce->base_dma = dma_map_resource(dev, res->start, + resource_size(res), + DMA_BIDIRECTIONAL, 0); + ret = dma_mapping_error(dev, qce->base_dma); + if (!ret) + return 0; err_dma: qce_dma_release(&qce->dma); @@ -280,6 +286,7 @@ static int qce_crypto_probe(struct platform_device *pdev) static void qce_crypto_remove(struct platform_device *pdev) { struct qce_device *qce = platform_get_drvdata(pdev); + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); tasklet_kill(&qce->done_tasklet); qce_unregister_algs(qce); @@ -287,6 +294,9 @@ static void qce_crypto_remove(struct platform_device *pdev) clk_disable_unprepare(qce->bus); clk_disable_unprepare(qce->iface); clk_disable_unprepare(qce->core); + + dma_unmap_resource(&pdev->dev, qce->base_dma, resource_size(res), + DMA_BIDIRECTIONAL, 0); } static const struct of_device_id qce_crypto_of_match[] = { diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 228fcd69ec51..25e2af45c047 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -39,6 +39,7 @@ struct qce_device { struct qce_dma_data dma; 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Mon, 9 Sep 2024 09:27:29 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Sep 2024 02:27:24 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 04/11] crypto: qce - Add bam dma support for crypto register r/w Date: Mon, 9 Sep 2024 14:56:25 +0530 Message-ID: <20240909092632.2776160-5-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240909092632.2776160-1-quic_mdalam@quicinc.com> References: <20240909092632.2776160-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rq6IimvAMOP2BkoSuXJuA3O7pFiQNeN4 X-Proofpoint-GUID: rq6IimvAMOP2BkoSuXJuA3O7pFiQNeN4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 bulkscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409090074 Add BAM/DMA support for crypto register read/write. With this change multiple crypto register will get Written/Read using bam in one go. Signed-off-by: Md Sadre Alam --- Change in [v4] * No change Change in [v3] * Fixed alignment issue * Removed type casting in qce_read_reg_dma() and qce_write_reg_dma() Change in [v2] * Added initial support for bam api for register read/write Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/core.h | 9 ++ drivers/crypto/qce/dma.c | 227 ++++++++++++++++++++++++++++++++++++++ drivers/crypto/qce/dma.h | 24 +++- 3 files changed, 259 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index 25e2af45c047..bf28dedd1509 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -40,6 +40,8 @@ struct qce_device { int burst_size; unsigned int pipe_pair_id; dma_addr_t base_dma; + __le32 *reg_read_buf; + dma_addr_t reg_buf_phys; int (*async_req_enqueue)(struct qce_device *qce, struct crypto_async_request *req); void (*async_req_done)(struct qce_device *qce, int ret); @@ -59,4 +61,11 @@ struct qce_algo_ops { int (*async_req_handle)(struct crypto_async_request *async_req); }; +int qce_write_reg_dma(struct qce_device *qce, unsigned int offset, u32 val, + int cnt); +int qce_read_reg_dma(struct qce_device *qce, unsigned int offset, void *buff, + int cnt); +void qce_clear_bam_transaction(struct qce_device *qce); +int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags); +struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma); #endif /* _CORE_H_ */ diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 46db5bf366b4..e4e672d65302 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -4,12 +4,214 @@ */ #include +#include #include +#include "core.h" #include "dma.h" +#define QCE_REG_BUF_DMA_ADDR(qce, vaddr) \ + ((qce)->reg_buf_phys + \ + ((uint8_t *)(vaddr) - (uint8_t *)(qce)->reg_read_buf)) + +void qce_clear_bam_transaction(struct qce_device *qce) +{ + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; + + memset(&qce_bam_txn->qce_bam_ce_index, 0, sizeof(u32) * 8); +} + +static int qce_dma_prep_cmd_sg(struct qce_device *qce, struct dma_chan *chan, + struct scatterlist *qce_bam_sgl, + int qce_sgl_cnt, unsigned long flags, + enum dma_transfer_direction dir_eng, + dma_async_tx_callback cb, void *cb_param) +{ + struct dma_async_tx_descriptor *dma_desc; + struct qce_desc_info *desc; + dma_cookie_t cookie; + + desc = qce->dma.qce_bam_txn->qce_desc; + + if (dir_eng == DMA_MEM_TO_DEV) + desc->dir = DMA_TO_DEVICE; + if (dir_eng == DMA_DEV_TO_MEM) + desc->dir = DMA_FROM_DEVICE; + + if (!qce_bam_sgl || !qce_sgl_cnt) + return -EINVAL; + + if (!dma_map_sg(qce->dev, qce_bam_sgl, + qce_sgl_cnt, desc->dir)) { + dev_err(qce->dev, "failure in mapping sgl for cmd desc\n"); + return -ENOMEM; + } + + dma_desc = dmaengine_prep_slave_sg(chan, qce_bam_sgl, qce_sgl_cnt, + dir_eng, flags); + if (!dma_desc) { + pr_err("%s:failure in prep cmd desc\n", __func__); + dma_unmap_sg(qce->dev, qce_bam_sgl, qce_sgl_cnt, desc->dir); + kfree(desc); + return -EINVAL; + } + + desc->dma_desc = dma_desc; + desc->dma_desc->callback = cb; + desc->dma_desc->callback_param = cb_param; + + cookie = dmaengine_submit(desc->dma_desc); + + return dma_submit_error(cookie); +} + +int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) +{ + struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn; + struct dma_chan *chan = qce->dma.rxchan; + unsigned long desc_flags; + int ret = 0; + + desc_flags = DMA_PREP_CMD; + + /* For command descriptor always use consumer pipe + * it recomended as per HPG + */ + + if (qce_bam_txn->qce_read_sgl_cnt) { + ret = qce_dma_prep_cmd_sg(qce, chan, qce_bam_txn->qce_reg_read_sgl, + qce_bam_txn->qce_read_sgl_cnt, + desc_flags, DMA_DEV_TO_MEM, + NULL, NULL); + if (ret) { + pr_err("error while submiting cmd desc for rx\n"); + return ret; + } + } + + if (qce_bam_txn->qce_write_sgl_cnt) { + ret = qce_dma_prep_cmd_sg(qce, chan, qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + desc_flags, DMA_MEM_TO_DEV, + NULL, NULL); + } + + if (ret) { + pr_err("error while submiting cmd desc for tx\n"); + return ret; + } + + qce_dma_issue_pending(&qce->dma); + + if (qce_bam_txn->qce_read_sgl_cnt) + dma_unmap_sg(qce->dev, qce_bam_txn->qce_reg_read_sgl, + qce_bam_txn->qce_read_sgl_cnt, + DMA_FROM_DEVICE); + if (qce_bam_txn->qce_write_sgl_cnt) + dma_unmap_sg(qce->dev, qce_bam_txn->qce_reg_write_sgl, + qce_bam_txn->qce_write_sgl_cnt, + DMA_TO_DEVICE); + + return ret; +} + +static void qce_prep_dma_command_desc(struct qce_device *qce, struct qce_dma_data *dma, + bool read, unsigned int addr, void *buff, int size) +{ + struct qce_bam_transaction *qce_bam_txn = dma->qce_bam_txn; + struct bam_cmd_element *qce_bam_ce_buffer; + int qce_bam_ce_size, cnt, index; + + index = qce_bam_txn->qce_bam_ce_index; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce[index]; + if (read) + bam_prep_ce(qce_bam_ce_buffer, addr, BAM_READ_COMMAND, + QCE_REG_BUF_DMA_ADDR(qce, + (unsigned int *)buff)); + else + bam_prep_ce_le32(qce_bam_ce_buffer, addr, BAM_WRITE_COMMAND, + *((__le32 *)buff)); + + if (read) { + cnt = qce_bam_txn->qce_read_sgl_cnt; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce + [qce_bam_txn->qce_pre_bam_ce_index]; + qce_bam_txn->qce_bam_ce_index += size; + qce_bam_ce_size = (qce_bam_txn->qce_bam_ce_index - + qce_bam_txn->qce_pre_bam_ce_index) * + sizeof(struct bam_cmd_element); + + sg_set_buf(&qce_bam_txn->qce_reg_read_sgl[cnt], + qce_bam_ce_buffer, + qce_bam_ce_size); + + ++qce_bam_txn->qce_read_sgl_cnt; + qce_bam_txn->qce_pre_bam_ce_index = + qce_bam_txn->qce_bam_ce_index; + } else { + cnt = qce_bam_txn->qce_write_sgl_cnt; + qce_bam_ce_buffer = &qce_bam_txn->qce_bam_ce + [qce_bam_txn->qce_pre_bam_ce_index]; + qce_bam_txn->qce_bam_ce_index += size; + qce_bam_ce_size = (qce_bam_txn->qce_bam_ce_index - + qce_bam_txn->qce_pre_bam_ce_index) * + sizeof(struct bam_cmd_element); + + sg_set_buf(&qce_bam_txn->qce_reg_write_sgl[cnt], + qce_bam_ce_buffer, + qce_bam_ce_size); + + ++qce_bam_txn->qce_write_sgl_cnt; + qce_bam_txn->qce_pre_bam_ce_index = + qce_bam_txn->qce_bam_ce_index; + } +} + +int qce_write_reg_dma(struct qce_device *qce, + unsigned int offset, u32 val, int cnt) +{ + qce_prep_dma_command_desc(qce, &qce->dma, false, (qce->base_dma + offset), + &val, cnt); + return 0; +} + +int qce_read_reg_dma(struct qce_device *qce, + unsigned int offset, void *buff, int cnt) +{ + qce_prep_dma_command_desc(qce, &qce->dma, true, (qce->base_dma + offset), + qce->reg_read_buf, cnt); + memcpy(buff, qce->reg_read_buf, 4); + + return 0; +} + +struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma) +{ + struct qce_bam_transaction *qce_bam_txn; + + dma->qce_bam_txn = kmalloc(sizeof(*qce_bam_txn), GFP_KERNEL); + if (!dma->qce_bam_txn) + return NULL; + + dma->qce_bam_txn->qce_desc = kzalloc(sizeof(*dma->qce_bam_txn->qce_desc), + GFP_KERNEL); + if (!dma->qce_bam_txn->qce_desc) { + kfree(dma->qce_bam_txn); + return NULL; + } + + sg_init_table(dma->qce_bam_txn->qce_reg_write_sgl, + QCE_BAM_CMD_SGL_SIZE); + + sg_init_table(dma->qce_bam_txn->qce_reg_read_sgl, + QCE_BAM_CMD_SGL_SIZE); + + return dma->qce_bam_txn; +} + int qce_dma_request(struct device *dev, struct qce_dma_data *dma) { + struct qce_device *qce = container_of(dma, struct qce_device, dma); int ret; dma->txchan = dma_request_chan(dev, "tx"); @@ -31,7 +233,22 @@ int qce_dma_request(struct device *dev, struct qce_dma_data *dma) dma->ignore_buf = dma->result_buf + QCE_RESULT_BUF_SZ; + dma->qce_bam_txn = qce_alloc_bam_txn(dma); + if (!dma->qce_bam_txn) { + pr_err("Failed to allocate bam transaction\n"); + return -ENOMEM; + } + + qce->reg_read_buf = dmam_alloc_coherent(qce->dev, QCE_MAX_REG_READ * + sizeof(*qce->reg_read_buf), + &qce->reg_buf_phys, GFP_KERNEL); + if (!qce->reg_read_buf) { + pr_err("Failed to allocate reg_read_buf\n"); + return -ENOMEM; + } + return 0; + error_nomem: dma_release_channel(dma->rxchan); error_rx: @@ -41,9 +258,19 @@ int qce_dma_request(struct device *dev, struct qce_dma_data *dma) void qce_dma_release(struct qce_dma_data *dma) { + struct qce_device *qce = container_of(dma, + struct qce_device, dma); + dma_release_channel(dma->txchan); dma_release_channel(dma->rxchan); kfree(dma->result_buf); + if (qce->reg_read_buf) + dmam_free_coherent(qce->dev, QCE_MAX_REG_READ * + sizeof(*qce->reg_read_buf), + qce->reg_read_buf, + qce->reg_buf_phys); + kfree(dma->qce_bam_txn->qce_desc); + kfree(dma->qce_bam_txn); } struct scatterlist * diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index 786402169360..f10991590b3f 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -7,6 +7,7 @@ #define _DMA_H_ #include +#include /* maximum data transfer block size between BAM and CE */ #define QCE_BAM_BURST_SIZE 64 @@ -14,6 +15,10 @@ #define QCE_AUTHIV_REGS_CNT 16 #define QCE_AUTH_BYTECOUNT_REGS_CNT 4 #define QCE_CNTRIV_REGS_CNT 4 +#define QCE_BAM_CMD_SGL_SIZE 64 +#define QCE_BAM_CMD_ELEMENT_SIZE 64 +#define QCE_DMA_DESC_FLAG_BAM_NWD (0x0004) +#define QCE_MAX_REG_READ 8 struct qce_result_dump { u32 auth_iv[QCE_AUTHIV_REGS_CNT]; @@ -27,13 +32,30 @@ struct qce_result_dump { #define QCE_RESULT_BUF_SZ \ ALIGN(sizeof(struct qce_result_dump), QCE_BAM_BURST_SIZE) +struct qce_bam_transaction { + struct bam_cmd_element qce_bam_ce[QCE_BAM_CMD_ELEMENT_SIZE]; + struct scatterlist qce_reg_write_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct scatterlist qce_reg_read_sgl[QCE_BAM_CMD_SGL_SIZE]; + struct qce_desc_info *qce_desc; + u32 qce_bam_ce_index; + u32 qce_pre_bam_ce_index; + u32 qce_write_sgl_cnt; + u32 qce_read_sgl_cnt; +}; + struct qce_dma_data { struct dma_chan *txchan; struct dma_chan *rxchan; struct qce_result_dump *result_buf; + struct qce_bam_transaction *qce_bam_txn; void *ignore_buf; }; +struct qce_desc_info { + struct dma_async_tx_descriptor *dma_desc; + enum dma_data_direction dir; +}; + int qce_dma_request(struct device *dev, struct qce_dma_data *dma); void qce_dma_release(struct qce_dma_data *dma); int qce_dma_prep_sgs(struct qce_dma_data *dma, struct scatterlist *sg_in, @@ -44,5 +66,5 @@ int qce_dma_terminate_all(struct qce_dma_data *dma); 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Mon, 9 Sep 2024 09:27:34 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Sep 2024 02:27:29 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 05/11] crypto: qce - Convert register r/w for skcipher via BAM/DMA Date: Mon, 9 Sep 2024 14:56:26 +0530 Message-ID: <20240909092632.2776160-6-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240909092632.2776160-1-quic_mdalam@quicinc.com> References: <20240909092632.2776160-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WjpE7RMNCtE85ABPhXjrU9NF7YgB7Uvm X-Proofpoint-GUID: WjpE7RMNCtE85ABPhXjrU9NF7YgB7Uvm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409090074 Convert register read/write for skcipher via BAM/DMA. with this change all the crypto register configuration will be done via BAM/DMA. This change will prepare command descriptor for all register and write it once. Signed-off-by: Md Sadre Alam --- Change in [v4] * No change Change in [v3] * No change Change in [v2] * Added initial support to read/write crypto register via BAM for skcipher Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/common.c | 42 ++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 04253a8d3340..d1da6b1938f3 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -34,7 +34,7 @@ static inline void qce_write_array(struct qce_device *qce, u32 offset, int i; for (i = 0; i < len; i++) - qce_write(qce, offset + i * sizeof(u32), val[i]); + qce_write_reg_dma(qce, offset + i * sizeof(u32), val[i], 1); } static inline void @@ -43,7 +43,7 @@ qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len) int i; for (i = 0; i < len; i++) - qce_write(qce, offset + i * sizeof(u32), 0); + qce_write_reg_dma(qce, offset + i * sizeof(u32), 0, 1); } static u32 qce_config_reg(struct qce_device *qce, int little) @@ -86,16 +86,16 @@ static void qce_setup_config(struct qce_device *qce) config = qce_config_reg(qce, 0); /* clear status */ - qce_write(qce, REG_STATUS, 0); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_STATUS, 0, 1); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); } static inline void qce_crypto_go(struct qce_device *qce, bool result_dump) { if (result_dump) - qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT)); + qce_write_reg_dma(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT), 1); else - qce_write(qce, REG_GOPROC, BIT(GO_SHIFT)); + qce_write_reg_dma(qce, REG_GOPROC, BIT(GO_SHIFT), 1); } #if defined(CONFIG_CRYPTO_DEV_QCE_SHA) || defined(CONFIG_CRYPTO_DEV_QCE_AEAD) @@ -308,7 +308,7 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey, /* Set data unit size to cryptlen. Anything else causes * crypto engine to return back incorrect results. */ - qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen); + qce_write_reg_dma(qce, REG_ENCR_XTS_DU_SIZE, cryptlen, 1); } static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) @@ -325,7 +325,9 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) u32 encr_cfg = 0, auth_cfg = 0, config; unsigned int ivsize = rctx->ivsize; unsigned long flags = rctx->flags; + int ret; + qce_clear_bam_transaction(qce); qce_setup_config(qce); if (IS_XTS(flags)) @@ -336,7 +338,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) qce_cpu_to_be32p_array(enckey, ctx->enc_key, keylen); enckey_words = keylen / sizeof(u32); - qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1); encr_cfg = qce_encr_cfg(flags, keylen); @@ -369,25 +371,31 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req) if (IS_ENCRYPT(flags)) encr_cfg |= BIT(ENCODE_SHIFT); - qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); - qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); - qce_write(qce, REG_ENCR_SEG_START, 0); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, encr_cfg, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_START, 0, 1); if (IS_CTR(flags)) { - qce_write(qce, REG_CNTR_MASK, ~0); - qce_write(qce, REG_CNTR_MASK0, ~0); - qce_write(qce, REG_CNTR_MASK1, ~0); - qce_write(qce, REG_CNTR_MASK2, ~0); + qce_write_reg_dma(qce, REG_CNTR_MASK, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK0, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK1, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK2, ~0, 1); } - qce_write(qce, REG_SEG_SIZE, rctx->cryptlen); + qce_write_reg_dma(qce, REG_SEG_SIZE, rctx->cryptlen, 1); /* get little endianness */ config = qce_config_reg(qce, 1); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); qce_crypto_go(qce, true); + ret = qce_submit_cmd_desc(qce, 0); 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This change will prepare command descriptor for all register and write it once. Signed-off-by: Md Sadre Alam --- Change in [v4] * No change Change in [v3] * No change Change in [v2] * Added initial support to read/write crypto register via BAM for SHA Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/common.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index d1da6b1938f3..d485762a3fdc 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -157,17 +157,19 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req) __be32 mackey[QCE_SHA_HMAC_KEY_SIZE / sizeof(__be32)] = {0}; u32 auth_cfg = 0, config; unsigned int iv_words; + int ret; /* if not the last, the size has to be on the block boundary */ if (!rctx->last_blk && req->nbytes % blocksize) return -EINVAL; + qce_clear_bam_transaction(qce); qce_setup_config(qce); if (IS_CMAC(rctx->flags)) { - qce_write(qce, REG_AUTH_SEG_CFG, 0); - qce_write(qce, REG_ENCR_SEG_CFG, 0); - qce_write(qce, REG_ENCR_SEG_SIZE, 0); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, 0, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, 0, 1); qce_clear_array(qce, REG_AUTH_IV0, 16); qce_clear_array(qce, REG_AUTH_KEY0, 16); qce_clear_array(qce, REG_AUTH_BYTECNT0, 4); @@ -213,18 +215,24 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req) auth_cfg &= ~BIT(AUTH_FIRST_SHIFT); go_proc: - qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); - qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes); - qce_write(qce, REG_AUTH_SEG_START, 0); - qce_write(qce, REG_ENCR_SEG_CFG, 0); - qce_write(qce, REG_SEG_SIZE, req->nbytes); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1); + qce_write_reg_dma(qce, REG_AUTH_SEG_SIZE, req->nbytes, 1); + qce_write_reg_dma(qce, REG_AUTH_SEG_START, 0, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, 0, 1); + qce_write_reg_dma(qce, REG_SEG_SIZE, req->nbytes, 1); /* get little endianness */ config = qce_config_reg(qce, 1); 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This change will prepare command descriptor for all register and write it once. Signed-off-by: Md Sadre Alam --- Change in [v4] * No change Change in [v3] * No change Change in [v2] * Added initial support to read/write crypto register via BAM for aead Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/common.c | 38 ++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index d485762a3fdc..ff96f6ba1fc5 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -454,7 +454,9 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) unsigned long flags = rctx->flags; u32 encr_cfg, auth_cfg, config, totallen; u32 iv_last_word; + int ret; + qce_clear_bam_transaction(qce); qce_setup_config(qce); /* Write encryption key */ @@ -467,12 +469,12 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) if (IS_CCM(rctx->flags)) { iv_last_word = enciv[enciv_words - 1]; - qce_write(qce, REG_CNTR3_IV3, iv_last_word + 1); + qce_write_reg_dma(qce, REG_CNTR3_IV3, iv_last_word + 1, 1); qce_write_array(qce, REG_ENCR_CCM_INT_CNTR0, (u32 *)enciv, enciv_words); - qce_write(qce, REG_CNTR_MASK, ~0); - qce_write(qce, REG_CNTR_MASK0, ~0); - qce_write(qce, REG_CNTR_MASK1, ~0); - qce_write(qce, REG_CNTR_MASK2, ~0); + qce_write_reg_dma(qce, REG_CNTR_MASK, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK0, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK1, ~0, 1); + qce_write_reg_dma(qce, REG_CNTR_MASK2, ~0, 1); } /* Clear authentication IV and KEY registers of previous values */ @@ -508,7 +510,7 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) encr_cfg = qce_encr_cfg(flags, enc_keylen); if (IS_ENCRYPT(flags)) encr_cfg |= BIT(ENCODE_SHIFT); - qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg); + qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, encr_cfg, 1); /* Set up AUTH_SEG_CFG */ auth_cfg = qce_auth_cfg(rctx->flags, auth_keylen, ctx->authsize); @@ -525,34 +527,40 @@ static int qce_setup_regs_aead(struct crypto_async_request *async_req) else auth_cfg |= AUTH_POS_BEFORE << AUTH_POS_SHIFT; } - qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg); + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1); totallen = rctx->cryptlen + rctx->assoclen; /* Set the encryption size and start offset */ if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags)) - qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen + ctx->authsize, 1); else - qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen); - qce_write(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff); + qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen, 1); + qce_write_reg_dma(qce, REG_ENCR_SEG_START, rctx->assoclen & 0xffff, 1); /* Set the authentication size and start offset */ - qce_write(qce, REG_AUTH_SEG_SIZE, totallen); - qce_write(qce, REG_AUTH_SEG_START, 0); + qce_write_reg_dma(qce, REG_AUTH_SEG_SIZE, totallen, 1); + qce_write_reg_dma(qce, REG_AUTH_SEG_START, 0, 1); /* Write total length */ if (IS_CCM(rctx->flags) && IS_DECRYPT(rctx->flags)) - qce_write(qce, REG_SEG_SIZE, totallen + ctx->authsize); + qce_write_reg_dma(qce, REG_SEG_SIZE, totallen + ctx->authsize, 1); else - qce_write(qce, REG_SEG_SIZE, totallen); + qce_write_reg_dma(qce, REG_SEG_SIZE, totallen, 1); /* get little endianness */ config = qce_config_reg(qce, 1); - qce_write(qce, REG_CONFIG, config); + qce_write_reg_dma(qce, REG_CONFIG, config, 1); /* Start the process */ qce_crypto_go(qce, !IS_CCM(flags)); + ret = qce_submit_cmd_desc(qce, 0); + if (ret) { + dev_err(qce->dev, "Error in aead cmd descriptor\n"); + return ret; + } + return 0; } #endif From patchwork Mon Sep 9 09:26:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 13796536 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7D5C1B2EF5; Mon, 9 Sep 2024 09:28:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 09 Sep 2024 09:28:06 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4899RoiB010347 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Sep 2024 09:27:50 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Sep 2024 02:27:46 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 08/11] crypto: qce - Add LOCK and UNLOCK flag support Date: Mon, 9 Sep 2024 14:56:29 +0530 Message-ID: <20240909092632.2776160-9-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240909092632.2776160-1-quic_mdalam@quicinc.com> References: <20240909092632.2776160-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: VNKSFYDRR6fTRj0FBHHfTMZtm-oZeOrc X-Proofpoint-GUID: VNKSFYDRR6fTRj0FBHHfTMZtm-oZeOrc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409090075 Add LOCK and UNLOCK flag support while preapring command descriptor for writing crypto register. added qce_bam_acquire_lock() and qce_bam_release_lock() which will do dummy write to a crypto register for acquiring lock and releaseing lock. Signed-off-by: Md Sadre Alam --- Change in [v4] * Added qce_bam_acquire_lock() and qce_bam_release_lock() api Change in [v3] * No change Change in [v2] * Added initial support for LOCK/UNLOCK flag on command descriptor Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/common.c | 35 +++++++++++++++++++++++++++++++++++ drivers/crypto/qce/core.h | 2 ++ drivers/crypto/qce/dma.c | 7 ++++++- drivers/crypto/qce/dma.h | 2 ++ 4 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index ff96f6ba1fc5..dad12e15905f 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -588,6 +588,41 @@ int qce_start(struct crypto_async_request *async_req, u32 type) #define STATUS_ERRORS \ (BIT(SW_ERR_SHIFT) | BIT(AXI_ERR_SHIFT) | BIT(HSD_ERR_SHIFT)) +int qce_bam_acquire_lock(struct qce_device *qce) +{ + int ret; + + qce_clear_bam_transaction(qce); + + /* This is just a dummy write to acquire lock on bam pipe */ + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1); + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_LOCK); + if (ret) { + dev_err(qce->dev, "Error in Locking cmd descriptor\n"); + return ret; + } + + return 0; +} + +int qce_bam_release_lock(struct qce_device *qce) +{ + int ret; + + qce_clear_bam_transaction(qce); + + /* This just dummy write to release lock on bam pipe*/ + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1); + + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_UNLOCK); + if (ret) { + dev_err(qce->dev, "Error in Un-Locking cmd descriptor\n"); + return ret; + } + + return 0; +} + int qce_check_status(struct qce_device *qce, u32 *status) { int ret = 0; diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index bf28dedd1509..d01d810b60ad 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -68,4 +68,6 @@ int qce_read_reg_dma(struct qce_device *qce, unsigned int offset, void *buff, void qce_clear_bam_transaction(struct qce_device *qce); int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags); struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma); +int qce_bam_acquire_lock(struct qce_device *qce); +int qce_bam_release_lock(struct qce_device *qce); #endif /* _CORE_H_ */ diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index e4e672d65302..93d455d1d5b4 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -72,7 +72,12 @@ int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) unsigned long desc_flags; int ret = 0; - desc_flags = DMA_PREP_CMD; + if (flags & QCE_DMA_DESC_FLAG_LOCK) + desc_flags = DMA_PREP_CMD | DMA_PREP_LOCK; + else if (flags & QCE_DMA_DESC_FLAG_UNLOCK) + desc_flags = DMA_PREP_CMD | DMA_PREP_UNLOCK; + else + desc_flags = DMA_PREP_CMD; /* For command descriptor always use consumer pipe * it recomended as per HPG diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index f10991590b3f..ad8a18a720b1 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -19,6 +19,8 @@ #define QCE_BAM_CMD_ELEMENT_SIZE 64 #define QCE_DMA_DESC_FLAG_BAM_NWD (0x0004) #define QCE_MAX_REG_READ 8 +#define QCE_DMA_DESC_FLAG_LOCK (0x0002) +#define QCE_DMA_DESC_FLAG_UNLOCK (0x0001) struct qce_result_dump { u32 auth_iv[QCE_AUTHIV_REGS_CNT]; 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Mon, 9 Sep 2024 09:27:56 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Sep 2024 02:27:50 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 09/11] crypto: qce - Add support for lock/unlock in skcipher Date: Mon, 9 Sep 2024 14:56:30 +0530 Message-ID: <20240909092632.2776160-10-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240909092632.2776160-1-quic_mdalam@quicinc.com> References: <20240909092632.2776160-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: LZWc3Wrawb4nGf4Rias4EuD47xlrLEka X-Proofpoint-GUID: LZWc3Wrawb4nGf4Rias4EuD47xlrLEka X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1015 phishscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409090075 Add support for lock/unlock on bam pipe in skcipher. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- Change in [v4] * No change Change in [v3] * Move qce_bam_release_lock() after qca_dma_terminate_all() api Change in [v2] * Added qce_bam_acquire_lock() and qce_bam_release_lock() api for skcipher Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/skcipher.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c index 5b493fdc1e74..a4e09562b5f4 100644 --- a/drivers/crypto/qce/skcipher.c +++ b/drivers/crypto/qce/skcipher.c @@ -52,6 +52,8 @@ static void qce_skcipher_done(void *data) sg_free_table(&rctx->dst_tbl); + qce_bam_release_lock(qce); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "skcipher operation error (%x)\n", status); @@ -82,6 +84,8 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req) dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? 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Mon, 9 Sep 2024 09:28:00 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Sep 2024 02:27:56 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 10/11] crypto: qce - Add support for lock/unlock in sha Date: Mon, 9 Sep 2024 14:56:31 +0530 Message-ID: <20240909092632.2776160-11-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240909092632.2776160-1-quic_mdalam@quicinc.com> References: <20240909092632.2776160-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PltVsEUzTzP7_aUhKIifteAo1BkIk_Yz X-Proofpoint-GUID: PltVsEUzTzP7_aUhKIifteAo1BkIk_Yz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 malwarescore=0 clxscore=1015 phishscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409090075 Add support for lock/unlock on bam pipe in sha. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- Change in [v4] * No change Change in [v3] * Move qce_bam_release_lock() after qca_dma_terminate_all() api Change in [v2] * Added qce_bam_acquire_lock() and qce_bam_release_lock() api for SHA Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/sha.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c index fc72af8aa9a7..abfa63ff18d7 100644 --- a/drivers/crypto/qce/sha.c +++ b/drivers/crypto/qce/sha.c @@ -60,6 +60,8 @@ static void qce_ahash_done(void *data) rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]); rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]); + qce_bam_release_lock(qce); + error = qce_check_status(qce, &status); if (error < 0) dev_dbg(qce->dev, "ahash operation error (%x)\n", status); @@ -90,6 +92,8 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req) rctx->authklen = AES_KEYSIZE_128; } + qce_bam_acquire_lock(qce); + rctx->src_nents = sg_nents_for_len(req->src, req->nbytes); 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If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- Change in [v4] * No change Change in [v3] * Move qce_bam_release_lock() after qca_dma_terminate_all() api Change in [v2] * Added qce_bam_acquire_lock() and qce_bam_release_lock() api for aead Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/aead.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index 7d811728f047..13fb7af69f54 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -63,6 +63,8 @@ static void qce_aead_done(void *data) sg_free_table(&rctx->dst_tbl); } + qce_bam_release_lock(qce); + error = qce_check_status(qce, &status); if (error < 0 && (error != -EBADMSG)) dev_err(qce->dev, "aead operation error (%x)\n", status); @@ -433,6 +435,8 @@ qce_aead_async_req_handle(struct crypto_async_request *async_req) else rctx->assoclen = req->assoclen; + qce_bam_acquire_lock(qce); + diff_dst = (req->src != req->dst) ? true : false; dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;