From patchwork Thu Mar 7 14:14:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 10842977 X-Patchwork-Delegate: neil.armstrong@linaro.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 713EF1823 for ; Thu, 7 Mar 2019 14:15:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5BDE828867 for ; Thu, 7 Mar 2019 14:15:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4FC2B28948; Thu, 7 Mar 2019 14:15:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 99DDC288EA for ; Thu, 7 Mar 2019 14:15:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vvlKLdGM5no0MrEks02lekubSE43U2mLjE6Oc/4ZwZA=; b=V0gqd/t1jvKo13 qLoZ4/MagBwXLLLRazTAuhyV8HdS7FXnPT6ybR9691cKzjGOa/HPVMihVpyCyJxOd8ay7Auesi8JX 2dzAZyBbKFsRsAE4s5AHJksjxbQ44Mmsyfa2gDCIaziHO3vcskhr8QAvzas2ns6/uTPv/mvzSbq51 ujqVhNjhSEdr5BP5zhbTEiYcOTSG+iRffH84moO8PdpqDt3PItgu+m626JL1qUXVIIW3RMzvPuM7a qgL7r1Q7NnHI03wPZMNOfFKjGg3olzXzirDSkci3nKvw6NCUsYBpXLOalOIkyiSGGg96voGc43+7t bBBm+IBoQjG0YBQ/mHqQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h1tnn-0002Si-PP; Thu, 07 Mar 2019 14:15:15 +0000 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h1tnX-0000zw-Rj for linux-amlogic@lists.infradead.org; Thu, 07 Mar 2019 14:15:01 +0000 Received: by mail-wr1-x442.google.com with SMTP id l12so1153094wrp.6 for ; Thu, 07 Mar 2019 06:14:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6xv40rDikhpGj1gO+S5PFI70OqXKcih9FYV8He3Os+U=; b=gdtYuN9ZjvzhNAHkBVQiTohpzwLRLXb3p4HybLzFzTj9g69tpeYIYGLqlaR2nPKnXY JbaPCdZwaYN4VckyAgm9advhTTKTi4radONdytGWX6sf33nrw4HY5xMJKocjQJYThxY4 awrdLTJg+HspXIPMg8K9DbsZWTuK4CW+KsgaghB05bbp0Z6CDcPUvao2pJE0tQ9etYTG 06Qr1b28YtJCktq53t239Fl6QN0y1QdyOBdaQzEETKV2viTK3doLE5FG9WcQmGeMWx07 lMLeaoUvr8tCGZ35u8YV4dAfYLjdeViyILVZNrSDKUB/F9a+9jE8J2ur1g8GS1t2K+bZ ea1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6xv40rDikhpGj1gO+S5PFI70OqXKcih9FYV8He3Os+U=; b=OHY8sNsSvwYL8/C10Z6Uopzb2LMOXTeq7/4MAro+ih9r18haaCoNi7McnK0xjrNNno 5rCT2PgvlygIpIlJhHAZQRZ6QbbrDKkphLzhIPgQNF6M77vK54uXVpSOKlDSxgG6pScs qt7B+PETzSksLndmr4fiNFwf/S+6OsMuroTtxrks+7807GYEv4n28fx3Oqj/usOey7ql m92hY2viJylTWu/ZQDThGeIiNyQmhdGvTulkiDFIl1sSj5WnOxy1nFWnFGcf+M+Psv6X WT5SFQlbh89l2zUMW+RO181zik6q7yODqcl4DIn+QMJo/ezd0XM9gXY/m8z7nMfSwOn5 WPwQ== X-Gm-Message-State: APjAAAV/POcQrEqTe2pRzJD2Dd/0KGlEfmAowPPV3OT8bzjqcAkghh1o HREphMmFtvz3FYaD1zl2bId4Ig== X-Google-Smtp-Source: APXvYqy+AuFiNJYSmMvWEPg7Pi/wMomf0boO0z0jA8J7VfuGSwtbXOlRqPiMtY+z0E3SxcqpOM8JeA== X-Received: by 2002:a5d:6744:: with SMTP id l4mr2398130wrw.226.1551968098338; Thu, 07 Mar 2019 06:14:58 -0800 (PST) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id h9sm9679304wrv.11.2019.03.07.06.14.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Mar 2019 06:14:57 -0800 (PST) From: Neil Armstrong To: jbrunet@baylibre.com Subject: [PATCH 1/3] clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL Date: Thu, 7 Mar 2019 15:14:53 +0100 Message-Id: <20190307141455.23879-2-narmstrong@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307141455.23879-1-narmstrong@baylibre.com> References: <20190307141455.23879-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190307_061459_894481_7E71B552 X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Meson G12A PCIE PLL is fined tuned to deliver a very precise 100MHz reference clock for the PCIe Analog PHY, and thus requires a strict register sequence to enable the PLL. To simplify, use the _init() op to enable the PLL and keep the other ops except set_rate since the rate is fixed. Signed-off-by: Neil Armstrong --- drivers/clk/meson/clk-pll.c | 26 ++++++++++++++++++++++++++ drivers/clk/meson/clk-pll.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 41e16dd7272a..6a88dd75ccf0 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -303,6 +303,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) return 1; } +static int meson_clk_pcie_pll_enable(struct clk_hw *hw) +{ + meson_clk_pll_init(hw); + + if (meson_clk_pll_wait_lock(hw)) + return -EIO; + + return 0; +} + static int meson_clk_pll_enable(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); @@ -387,6 +397,22 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +/* + * The Meson G12A PCIE PLL is fined tuned to deliver a very precise + * 100MHz reference clock for the PCIe Analog PHY, and thus requires + * a strict register sequence to enable the PLL. + * To simplify, re-use the _init() op to enable the PLL and keep + * the other ops except set_rate since the rate is fixed. + */ +const struct clk_ops meson_clk_pcie_pll_ops = { + .recalc_rate = meson_clk_pll_recalc_rate, + .round_rate = meson_clk_pll_round_rate, + .is_enabled = meson_clk_pll_is_enabled, + .enable = meson_clk_pcie_pll_enable, + .disable = meson_clk_pll_disable +}; +EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops); + const struct clk_ops meson_clk_pll_ops = { .init = meson_clk_pll_init, .recalc_rate = meson_clk_pll_recalc_rate, diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 55af2e285b1b..367efd0f6410 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -45,5 +45,6 @@ struct meson_clk_pll_data { extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; +extern const struct clk_ops meson_clk_pcie_pll_ops; #endif /* __MESON_CLK_PLL_H */ From patchwork Thu Mar 7 14:14:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 10842983 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 51DD81515 for ; Thu, 7 Mar 2019 14:15:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3B96428867 for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id h9sm9679304wrv.11.2019.03.07.06.14.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Mar 2019 06:14:59 -0800 (PST) From: Neil Armstrong To: jbrunet@baylibre.com, devicetree@vger.kernel.org Subject: [PATCH 2/3] dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID Date: Thu, 7 Mar 2019 15:14:54 +0100 Message-Id: <20190307141455.23879-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307141455.23879-1-narmstrong@baylibre.com> References: <20190307141455.23879-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190307_061501_141225_F8808D86 X-CRM114-Status: GOOD ( 10.25 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add a clock ID for the reference clock feeding the USB3+PCIe Combo PHY. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- include/dt-bindings/clock/g12a-clkc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index d7bf0830c87d..30303728fe09 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -132,5 +132,6 @@ #define CLKID_MALI 175 #define CLKID_MPLL_5OM 177 #define CLKID_CPU_CLK 187 +#define CLKID_PCIE_PLL 201 #endif /* __G12A_CLKC_H */ From patchwork Thu Mar 7 14:14:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 10842987 X-Patchwork-Delegate: neil.armstrong@linaro.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6022A139A for ; Thu, 7 Mar 2019 14:15:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4901428867 for ; Thu, 7 Mar 2019 14:15:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3D04D288EA; Thu, 7 Mar 2019 14:15:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BCF8E28867 for ; Thu, 7 Mar 2019 14:15:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3QwVE/YKyqfG1edG+TfgHCAepwjMlFhGaqfw+WwOhAM=; b=AUtB+kG9aKiT7C /psM8VpVgblBzPubO+xbjEn+uSZiGIR0XDPXMksGL46Dd+V0f1PvxQBeu5+6jRYrOohEgSwJ6XlWF eyhtrVHiKmyXx4VDI2FYPAMV0XzqRP86BsS1RkwTJv2r9h6hlFYrQBpE9NUeFO0Lp5Gjm2qH8OwcO znMh7aV4Fc3Ke0SfLUFnHSiDGZAl1Eu1GpQ0BUkvHPHOdShgOcqT5die2CIAHTwEJx8BAzjcmr+zT GLwonk0lhTPyFIieUL2BFWTcnSRa4qiKyqQ4Mi1ArBvp5S6FOC47Na7b4gzV7LOq1oGhb2cZ8sHmR HuQdBVz7qQDPNWhin5Gw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h1toF-000320-5V; Thu, 07 Mar 2019 14:15:43 +0000 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h1tna-000117-4e for linux-amlogic@lists.infradead.org; Thu, 07 Mar 2019 14:15:10 +0000 Received: by mail-wm1-x343.google.com with SMTP id x7so9436849wmj.0 for ; Thu, 07 Mar 2019 06:15:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h5CtO0ucQaulmciUoQ1fe7VqyscuYbd4ACXEONNNHhk=; b=ZUspskAcoOBQ9Zw+aOrkAlKFkDg3Ol2NeiZeR/1Ts9nXbRT1nanWnblrfX3dxDtcnJ ZU94YcCc3LFQaOjiUgBBJ6s9rOiir13pQGpTeFp/hjFmDBZ4lFUOjx99Zd6p65JbMqSH sEo5p6uryHipH3S1c/T7lxhlEjsyKJ5zGjuDNyOz7pjP8xivbVdcx2HFe4aE9uorYL8Z enA7HuqLYRqn5DHivGj8IuY2SNB1cY6teTtjbANhRB0WbEy4keJqOXVpg2jiHw/Y1rUg 5LAnRBl3UU6iEnKNPu85lgyxDjDaT1rlys0+HFVtsFz2h/cVrvb2nZ00Zirea94YKcez TmMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h5CtO0ucQaulmciUoQ1fe7VqyscuYbd4ACXEONNNHhk=; b=eCN3a6LuOt5U3Q4O90SjoJEJwIfZ7qvRGhze2XTLRL9Wenyunhi45AuXS7eSAjk/ss 4+plOPWhrPHq6gTcp2P9FB/tk45hUcw/TBmDjNgrmpqjcGtw4Rl4YHNLzqwzoRXxV7SL 9FZPqze01caXQT2oWN6alJdf8xP3p9zWS+4lICPuVctEwkcrKF1RgkMpFDETPZvpNk0f g7MX4UWPNuPj9YQl5KGqjvleLgft1Xpzh1DEovbk/PuMH6keTGeIsXjbdZOTev9F1rnN B9vldV9U7W+bw3Xw2eIRkOnTPYGzqwNJvJ2PWnhxRFmXkH6+AmtKX4qo5sXOC8eb9DbS gccw== X-Gm-Message-State: APjAAAUEiMhwoIaZVhshCu1QcINMnnTW6s0xdgSjqyZjhCc2Wl6Eo+O5 8LgPfwUwvqgh4r7q7zWzb2NAzw== X-Google-Smtp-Source: APXvYqx47eIbcTjMk6Nn35k9CidruU+6YKtfm6BsPjVMrD06M9mHbte9SBUh+BRyTVETzrfS4KZpPg== X-Received: by 2002:a1c:39d5:: with SMTP id g204mr6128818wma.17.1551968100586; Thu, 07 Mar 2019 06:15:00 -0800 (PST) Received: from bender.baylibre.local (lmontsouris-657-1-212-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id h9sm9679304wrv.11.2019.03.07.06.14.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Mar 2019 06:15:00 -0800 (PST) From: Neil Armstrong To: jbrunet@baylibre.com Subject: [PATCH 3/3] clk: meson-g12a: add PCIE PLL clocks Date: Thu, 7 Mar 2019 15:14:55 +0100 Message-Id: <20190307141455.23879-4-narmstrong@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190307141455.23879-1-narmstrong@baylibre.com> References: <20190307141455.23879-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190307_061502_422991_866AAB98 X-CRM114-Status: GOOD ( 13.76 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the PCIe reference clock feeding the USB3 + PCIE combo PHY. This PLL needs a very precise register sequence to permit to be locked, thus using the specific clk-pll pcie ops. The PLL is then followed by : - a fixed /2 divider - a 5-bit 1-based divider - a final /2 divider This reference clock is fixed to 100MHz, thus only a single PLL setup is added. Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 118 +++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 5 +- 2 files changed, 122 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 80a7172df2a6..d382c21a29e5 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -614,6 +614,118 @@ static struct clk_regmap g12a_hifi_pll = { }, }; +/* + * The Meson G12A PCIE PLL is fined tuned to deliver a very precise + * 100MHz reference clock for the PCIe Analog PHY, and thus requires + * a strict register sequence to enable the PLL. + */ +static const struct reg_sequence g12a_pcie_pll_init_regs[] = { + { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 }, + { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 }, + { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 }, + { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 }, + { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 }, + { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 }, + { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 }, + { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 }, + { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 }, + { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 }, + { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 }, + { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 }, +}; + +/* Keep a single entry table for recalc/round_rate() ops */ +static const struct pll_params_table g12a_pcie_pll_table[] = { + PLL_PARAMS(150, 1), + {0, 0}, +}; + +static struct clk_regmap g12a_pcie_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 10, + .width = 5, + }, + .frac = { + .reg_off = HHI_PCIE_PLL_CNTL1, + .shift = 0, + .width = 12, + }, + .l = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_PCIE_PLL_CNTL0, + .shift = 29, + .width = 1, + }, + .table = g12a_pcie_pll_table, + .init_regs = g12a_pcie_pll_init_regs, + .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_dco", + .ops = &meson_clk_pcie_pll_ops, + .parent_names = (const char *[]){ IN_PREFIX "xtal" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_dco_div2", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "pcie_pll_dco" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap g12a_pcie_pll_od = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_PCIE_PLL_CNTL0, + .shift = 16, + .width = 5, + .flags = CLK_DIVIDER_ROUND_CLOSEST | + CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, + }, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_od", + .ops = &clk_regmap_divider_ops, + .parent_names = (const char *[]){ "pcie_pll_dco_div2" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor g12a_pcie_pll = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_pll", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "pcie_pll_od" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap g12a_hdmi_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { @@ -2499,6 +2611,10 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, + [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, + [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, + [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, + [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -2685,6 +2801,8 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &g12a_cpu_clk_axi, &g12a_cpu_clk_trace_div, &g12a_cpu_clk_trace, + &g12a_pcie_pll_od, + &g12a_pcie_pll_dco, }; static const struct meson_eeclkc_data g12a_clkc_data = { diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 70aa469ca1cf..1393a09730a6 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -186,8 +186,11 @@ #define CLKID_CPU_CLK_AXI 195 #define CLKID_CPU_CLK_TRACE_DIV 196 #define CLKID_CPU_CLK_TRACE 197 +#define CLKID_PCIE_PLL_DCO 198 +#define CLKID_PCIE_PLL_DCO_DIV2 199 +#define CLKID_PCIE_PLL_OD 200 -#define NR_CLKS 198 +#define NR_CLKS 202 /* include the CLKIDs that have been made part of the DT binding */ #include