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From: "Andrei Cherechesu (OSS)" To: xen-devel@lists.xenproject.org Cc: S32@nxp.com, andrei.cherechesu@oss.nxp.com, Andrei Cherechesu , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Jan Beulich Subject: [PATCH v1 1/5] xen/arm: Add NXP LINFlexD UART Driver Date: Tue, 10 Sep 2024 17:34:07 +0300 Message-ID: <20240910143411.178704-2-andrei.cherechesu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240910143411.178704-1-andrei.cherechesu@oss.nxp.com> References: <20240910143411.178704-1-andrei.cherechesu@oss.nxp.com> X-ClientProxiedBy: AM0P190CA0019.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::29) To PA4PR04MB9565.eurprd04.prod.outlook.com (2603:10a6:102:26b::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PA4PR04MB9565:EE_|AS8PR04MB7557:EE_ X-MS-Office365-Filtering-Correlation-Id: c1152014-a353-4ce6-6f1b-08dcd1a5b011 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|52116014|376014|38350700014; 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S32G3 Reference Manual: https://www.nxp.com/webapp/Download?colCode=RMS32G3. Signed-off-by: Andrei Cherechesu Signed-off-by: Peter van der Perk --- xen/arch/arm/include/asm/linflex-uart.h | 62 ++++ xen/drivers/char/Kconfig | 8 + xen/drivers/char/Makefile | 1 + xen/drivers/char/linflex-uart.c | 365 ++++++++++++++++++++++++ 4 files changed, 436 insertions(+) create mode 100644 xen/arch/arm/include/asm/linflex-uart.h create mode 100644 xen/drivers/char/linflex-uart.c diff --git a/xen/arch/arm/include/asm/linflex-uart.h b/xen/arch/arm/include/asm/linflex-uart.h new file mode 100644 index 0000000000..62dc54d155 --- /dev/null +++ b/xen/arch/arm/include/asm/linflex-uart.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * xen/arch/arm/include/asm/linflex-uart.h + * + * Common constant definition between early printk and the UART driver + * for NXP LINFlexD UART. + * + * Andrei Cherechesu + * Copyright 2018, 2021, 2024 NXP + */ + +#ifndef __ASM_ARM_LINFLEX_UART_H +#define __ASM_ARM_LINFLEX_UART_H + +/* 32-bit register offsets */ +#define LINCR1 (0x0) +#define LINIER (0x4) +#define LINSR (0x8) +#define UARTCR (0x10) +#define UARTSR (0x14) +#define LINFBRR (0x24) +#define LINIBRR (0x28) +#define BDRL (0x38) +#define BDRM (0x3C) +#define UARTPTO (0x50) + +#define LINCR1_INIT BIT(0, U) +#define LINCR1_MME BIT(4, U) +#define LINCR1_BF BIT(7, U) + +#define LINSR_LINS GENMASK(15, 12) +#define LINSR_LINS_INIT BIT(12, U) + +#define LINIER_DRIE BIT(2, U) +#define LINIER_DTIE BIT(1, U) + +#define UARTCR_UART BIT(0, U) +#define UARTCR_WL0 BIT(1, U) +#define UARTCR_PC0 BIT(3, U) +#define UARTCR_TXEN BIT(4, U) +#define UARTCR_RXEN BIT(5, U) +#define UARTCR_PC1 BIT(6, U) +#define UARTCR_TFBM BIT(8, U) +#define UARTCR_RFBM BIT(9, U) +#define UARTCR_RDFLRFC GENMASK(12, 10) +#define UARTCR_TDFLTFC GENMASK(15, 13) +#define UARTCR_ROSE BIT(23, U) +#define UARTCR_OSR GENMASK(27, 24) + +#define UARTSR_DTFTFF BIT(1, U) +#define UARTSR_DRFRFE BIT(2, U) + +#endif /* __ASM_ARM_LINFLEX_UART_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig index 3f836ab301..e175d07c02 100644 --- a/xen/drivers/char/Kconfig +++ b/xen/drivers/char/Kconfig @@ -13,6 +13,14 @@ config HAS_CADENCE_UART This selects the Xilinx Zynq Cadence UART. If you have a Xilinx Zynq based board, say Y. +config HAS_LINFLEX + bool "NXP LINFlexD UART driver" + default y + depends on ARM_64 + help + This selects the NXP LINFlexD UART. If you have an NXP S32G or S32R + based board, say Y. + config HAS_IMX_LPUART bool "i.MX LPUART driver" default y diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile index e7e374775d..d3b987da1d 100644 --- a/xen/drivers/char/Makefile +++ b/xen/drivers/char/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_HAS_SCIF) += scif-uart.o obj-$(CONFIG_HAS_EHCI) += ehci-dbgp.o obj-$(CONFIG_XHCI) += xhci-dbc.o obj-$(CONFIG_HAS_IMX_LPUART) += imx-lpuart.o +obj-$(CONFIG_HAS_LINFLEX) += linflex-uart.o obj-$(CONFIG_ARM) += arm-uart.o obj-y += serial.o obj-$(CONFIG_XEN_GUEST) += xen_pv_console.o diff --git a/xen/drivers/char/linflex-uart.c b/xen/drivers/char/linflex-uart.c new file mode 100644 index 0000000000..4ca8f732ae --- /dev/null +++ b/xen/drivers/char/linflex-uart.c @@ -0,0 +1,365 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * xen/drivers/char/linflex-uart.c + * + * Driver for NXP LINFlexD UART. + * + * Andrei Cherechesu + * Copyright 2018, 2021-2022, 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LINFLEX_CLK_FREQ (125000000) +#define LINFLEX_BAUDRATE (115200) +#define LINFLEX_LDIV_MULTIPLIER (16) + +static struct linflex_uart { + uint32_t baud, clock_hz; + uint32_t irq; + char __iomem *regs; + struct irqaction irqaction; + struct vuart_info vuart; +} linflex_com; + +static uint32_t linflex_uart_readl(struct linflex_uart *uart, uint32_t off) +{ + return readl(uart->regs + off); +} + +static void linflex_uart_writel(struct linflex_uart *uart, uint32_t off, + uint32_t val) +{ + writel(val, uart->regs + off); +} + +static void linflex_uart_writeb(struct linflex_uart *uart, uint32_t off, + uint8_t val) +{ + writeb(val, uart->regs + off); +} + +static uint32_t linflex_uart_get_osr(uint32_t uartcr) +{ + return (uartcr & UARTCR_OSR) >> 24; +} + +static uint32_t linflex_uart_tx_fifo_mode(struct linflex_uart *uart) +{ + return linflex_uart_readl(uart, UARTCR) & UARTCR_TFBM; +} + +static uint32_t linflex_uart_rx_fifo_mode(struct linflex_uart *uart) +{ + return linflex_uart_readl(uart, UARTCR) & UARTCR_RFBM; +} + +static uint32_t linflex_uart_ldiv_multiplier(struct linflex_uart *uart) +{ + uint32_t uartcr, mul = LINFLEX_LDIV_MULTIPLIER; + + uartcr = linflex_uart_readl(uart, UARTCR); + if ( uartcr & UARTCR_ROSE ) + mul = linflex_uart_get_osr(uartcr); + + return mul; +} + +static void linflex_uart_flush(struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + + if ( linflex_uart_tx_fifo_mode(uart) ) + while ( linflex_uart_readl(uart, UARTCR) & UARTCR_TDFLTFC ); + cpu_relax(); + + if ( linflex_uart_rx_fifo_mode(uart) ) + while ( linflex_uart_readl(uart, UARTCR) & UARTCR_RDFLRFC ); + cpu_relax(); +} + +static void __init linflex_uart_init_preirq(struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + uint32_t ibr, fbr, divisr, dividr, ctrl; + + /* Disable RX/TX before init mode */ + ctrl = linflex_uart_readl(uart, UARTCR); + ctrl &= ~(UARTCR_RXEN | UARTCR_TXEN); + linflex_uart_writel(uart, UARTCR, ctrl); + + /* + * Smoothen the transition from early_printk by waiting + * for all pending characters to transmit + */ + linflex_uart_flush(port); + + /* Init mode */ + ctrl = LINCR1_INIT; + linflex_uart_writel(uart, LINCR1, ctrl); + + /* Waiting for init mode entry */ + while ( (linflex_uart_readl(uart, LINSR) & LINSR_LINS) != LINSR_LINS_INIT ) + cpu_relax(); + + /* Set Master Mode */ + ctrl |= LINCR1_MME; + linflex_uart_writel(uart, LINCR1, ctrl); + + /* Provide data bits, parity, stop bit, etc */ + divisr = uart->clock_hz; + dividr = (uint32_t)(uart->baud * linflex_uart_ldiv_multiplier(uart)); + + ibr = (uint32_t)(divisr / dividr); + fbr = (uint32_t)((divisr % dividr) * 16 / dividr) & 0xF; + + linflex_uart_writel(uart, LINIBRR, ibr); + linflex_uart_writel(uart, LINFBRR, fbr); + + /* Set preset timeout register value */ + linflex_uart_writel(uart, UARTPTO, 0xF); + + /* Setting UARTCR[UART] bit is required for writing other bits in UARTCR */ + linflex_uart_writel(uart, UARTCR, UARTCR_UART); + + /* 8 bit data, no parity, UART mode, Buffer mode */ + linflex_uart_writel(uart, UARTCR, UARTCR_PC1 | UARTCR_PC0 | UARTCR_WL0 | + UARTCR_UART); + + /* end init mode */ + ctrl = linflex_uart_readl(uart, LINCR1); + ctrl &= ~LINCR1_INIT; + linflex_uart_writel(uart, LINCR1, ctrl); + + /* Enable RX/TX after exiting init mode */ + ctrl = linflex_uart_readl(uart, UARTCR); + ctrl |= UARTCR_RXEN | UARTCR_TXEN; + linflex_uart_writel(uart, UARTCR, ctrl); +} + +static void linflex_uart_interrupt(int irq, void *data) +{ + struct serial_port *port = data; + struct linflex_uart *uart = port->uart; + uint32_t sts; + + sts = linflex_uart_readl(uart, UARTSR); + + if ( sts & UARTSR_DRFRFE ) + serial_rx_interrupt(port); + + if ( sts & UARTSR_DTFTFF ) + serial_tx_interrupt(port); +} + +static void __init linflex_uart_init_postirq(struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + uint32_t temp; + + uart->irqaction.handler = linflex_uart_interrupt; + uart->irqaction.name = "linflex_uart"; + uart->irqaction.dev_id = port; + + if ( setup_irq(uart->irq, 0, &uart->irqaction) != 0 ) + { + dprintk(XENLOG_ERR, "Failed to allocate linflex_uart IRQ %d\n", + uart->irq); + return; + } + + /* Enable interrupts */ + temp = linflex_uart_readl(uart, LINIER); + temp |= (LINIER_DRIE | LINIER_DTIE); + linflex_uart_writel(uart, LINIER, temp); + dprintk(XENLOG_DEBUG, "IRQ %d enabled\n", uart->irq); +} + +static int linflex_uart_tx_ready(struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + + if ( linflex_uart_tx_fifo_mode(uart) ) + return (linflex_uart_readl(uart, UARTSR) & UARTSR_DTFTFF) == 0 ? 1 : 0; + + /* + * Buffer Mode => TX is waited to be ready after sending a char, + * so we can assume it is always ready before. + */ + return 1; +} + +static void linflex_uart_putc(struct serial_port *port, char c) +{ + struct linflex_uart *uart = port->uart; + uint32_t uartsr; + + if ( c == '\n' ) + linflex_uart_putc(port, '\r'); + + linflex_uart_writeb(uart, BDRL, c); + + /* Buffer Mode */ + if ( !linflex_uart_tx_fifo_mode(uart) ) + { + while ( (linflex_uart_readl(uart, UARTSR) & UARTSR_DTFTFF) == 0 ) + cpu_relax(); + + uartsr = linflex_uart_readl(uart, UARTSR) | (UARTSR_DTFTFF); + linflex_uart_writel(uart, UARTSR, uartsr); + } +} + +static int linflex_uart_getc(struct serial_port *port, char *pc) +{ + struct linflex_uart *uart = port->uart; + uint32_t ch, uartsr, rx_fifo_mode; + + rx_fifo_mode = linflex_uart_rx_fifo_mode(uart); + + if ( rx_fifo_mode ) + while ( linflex_uart_readl(uart, UARTSR) & UARTSR_DRFRFE ) + cpu_relax(); + else + while ( !(linflex_uart_readl(uart, UARTSR) & UARTSR_DRFRFE) ) + cpu_relax(); + + ch = linflex_uart_readl(uart, BDRM); + *pc = ch & 0xff; + + if ( !rx_fifo_mode ) { + uartsr = linflex_uart_readl(uart, UARTSR) | UARTSR_DRFRFE; + linflex_uart_writel(uart, UARTSR, uartsr); + } + + return 1; +} + +static int __init linflex_uart_irq(struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + + return ((uart->irq > 0) ? uart->irq : -1); +} + +static const struct vuart_info *linflex_uart_vuart_info( + struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + + return &uart->vuart; +} + +static void linflex_uart_start_tx(struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + uint32_t temp; + + temp = linflex_uart_readl(uart, LINIER); + linflex_uart_writel(uart, LINIER, temp | LINIER_DTIE); +} + +static void linflex_uart_stop_tx(struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + uint32_t temp; + + temp = linflex_uart_readl(uart, LINIER); + temp &= ~(LINIER_DTIE); + linflex_uart_writel(uart, LINIER, temp); +} + +static struct uart_driver __read_mostly linflex_uart_driver = { + .init_preirq = linflex_uart_init_preirq, + .init_postirq = linflex_uart_init_postirq, + .tx_ready = linflex_uart_tx_ready, + .putc = linflex_uart_putc, + .flush = linflex_uart_flush, + .getc = linflex_uart_getc, + .irq = linflex_uart_irq, + .start_tx = linflex_uart_start_tx, + .stop_tx = linflex_uart_stop_tx, + .vuart_info = linflex_uart_vuart_info, +}; + +static int __init linflex_uart_init(struct dt_device_node *dev, const void *data) +{ + const char *config = data; + struct linflex_uart *uart; + paddr_t addr, size; + int res; + + if ( strcmp(config, "") ) + printk("WARNING: UART configuration is not supported\n"); + + uart = &linflex_com; + + res = dt_device_get_paddr(dev, 0, &addr, &size); + if ( res ) + { + printk("linflex-uart: Unable to retrieve the base address of the UART\n"); + return res; + } + + res = platform_get_irq(dev, 0); + if ( res < 0 ) + { + printk("linflex-uart: Unable to retrieve the IRQ\n"); + return -EINVAL; + } + uart->irq = res; + + uart->regs = ioremap_nocache(addr, size); + if ( !uart->regs ) + { + printk("linflex-uart: Unable to map the UART memory\n"); + return -ENOMEM; + } + + uart->clock_hz = LINFLEX_CLK_FREQ; + uart->baud = LINFLEX_BAUDRATE; + + uart->vuart.base_addr = addr; + uart->vuart.size = size; + uart->vuart.data_off = BDRL; + uart->vuart.status_off = UARTSR; + uart->vuart.status = UARTSR_DTFTFF; + + /* Register with generic serial driver */ + serial_register_uart(SERHND_DTUART, &linflex_uart_driver, uart); + + dt_device_set_used_by(dev, DOMID_XEN); + + return 0; +} + +static const struct dt_device_match linflex_uart_dt_compat[] __initconst = +{ + DT_MATCH_COMPATIBLE("nxp,s32g2-linflexuart"), + DT_MATCH_COMPATIBLE("nxp,s32g3-linflexuart"), + DT_MATCH_COMPATIBLE("fsl,s32v234-linflexuart"), + { /* sentinel */ }, +}; + +DT_DEVICE_START(linflex_uart, "NXP LINFlexD UART", DEVICE_SERIAL) + .dt_match = linflex_uart_dt_compat, + .init = linflex_uart_init, +DT_DEVICE_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Tue Sep 10 14:34:08 2024 Content-Type: text/plain; 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From: "Andrei Cherechesu (OSS)" To: xen-devel@lists.xenproject.org Cc: S32@nxp.com, andrei.cherechesu@oss.nxp.com, Andrei Cherechesu , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v1 2/5] xen/arm: Add NXP LINFlexD UART early printk support Date: Tue, 10 Sep 2024 17:34:08 +0300 Message-ID: <20240910143411.178704-3-andrei.cherechesu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240910143411.178704-1-andrei.cherechesu@oss.nxp.com> References: <20240910143411.178704-1-andrei.cherechesu@oss.nxp.com> X-ClientProxiedBy: AM0P190CA0019.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::29) To PA4PR04MB9565.eurprd04.prod.outlook.com (2603:10a6:102:26b::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PA4PR04MB9565:EE_|AS8PR04MB7557:EE_ X-MS-Office365-Filtering-Correlation-Id: 4f05d158-cd0c-402f-6169-08dcd1a5b0c8 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|52116014|376014|38350700014; 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Signed-off-by: Andrei Cherechesu Signed-off-by: Peter van der Perk Acked-by: Julien Grall --- xen/arch/arm/Kconfig.debug | 14 +++++++ xen/arch/arm/arm64/debug-linflex.inc | 58 ++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 xen/arch/arm/arm64/debug-linflex.inc diff --git a/xen/arch/arm/Kconfig.debug b/xen/arch/arm/Kconfig.debug index eec860e88e..a309f67f90 100644 --- a/xen/arch/arm/Kconfig.debug +++ b/xen/arch/arm/Kconfig.debug @@ -68,6 +68,16 @@ choice provide the parameters for the i.MX LPUART rather than selecting one of the platform specific options below if you know the parameters for the port. + config EARLY_UART_CHOICE_LINFLEX + select EARLY_UART_LINFLEX + depends on ARM_64 + bool "Early printk via NXP LINFlexD UART" + help + Say Y here if you wish the early printk to direct their + output to an NXP LINFlexD UART. You can use this option to + provide the parameters for the NXP LINFlexD UART rather than + selecting one of the platform specific options below if + you know the parameters for the port. config EARLY_UART_CHOICE_MESON select EARLY_UART_MESON depends on ARM_64 @@ -199,6 +209,9 @@ config EARLY_UART_EXYNOS4210 config EARLY_UART_IMX_LPUART select EARLY_PRINTK bool +config EARLY_UART_LINFLEX + select EARLY_PRINTK + bool config EARLY_UART_MESON select EARLY_PRINTK bool @@ -304,6 +317,7 @@ config EARLY_PRINTK_INC default "debug-cadence.inc" if EARLY_UART_CADENCE default "debug-exynos4210.inc" if EARLY_UART_EXYNOS4210 default "debug-imx-lpuart.inc" if EARLY_UART_IMX_LPUART + default "debug-linflex.inc" if EARLY_UART_LINFLEX default "debug-meson.inc" if EARLY_UART_MESON default "debug-mvebu.inc" if EARLY_UART_MVEBU default "debug-pl011.inc" if EARLY_UART_PL011 diff --git a/xen/arch/arm/arm64/debug-linflex.inc b/xen/arch/arm/arm64/debug-linflex.inc new file mode 100644 index 0000000000..6ed704e104 --- /dev/null +++ b/xen/arch/arm/arm64/debug-linflex.inc @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * xen/arch/arm/arm64/debug-linflex.inc + * + * NXP LINFlexD UART specific debug code + * + * Andrei Cherechesu + * Copyright 2018, 2021, 2023-2024 NXP + */ + +#include +#include + +/* + * wait LINFlexD UART to be ready to transmit + * xb: register which contains the UART base address + * c: scratch register number + */ +.macro early_uart_ready xb, c + ldr w\c, [\xb, #UARTCR] /* <= Control Register */ + and w\c, w\c, #UARTCR_TFBM /* Check Buffer/FIFO (0/1) Mode */ + cbz w\c, 2f /* Buffer Mode => return */ +1: + ldrb w\c, [\xb, #UARTSR] /* <= Status Register */ + tst w\c, #UARTSR_DTFTFF /* FIFO Mode => Check DTF bit */ + b.ne 1b +2: +.endm + +/* + * LINFlexD UART transmit character + * xb: register which contains the UART base address + * wt: register which contains the character to transmit + */ +.macro early_uart_transmit xb, wt + strb \wt, [\xb, #BDRL] + + ldr \wt, [\xb, #UARTCR] /* <= Control Register */ + and \wt, \wt, #UARTCR_TFBM /* Check Buffer/FIFO (0/1) Mode */ + cbnz \wt, 2f /* FIFO Mode => goto exit */ + +3: /* Buffer Mode */ + ldrb \wt, [\xb, #UARTSR] /* <= Status Register */ + and \wt, \wt, #UARTSR_DTFTFF /* Check Transmission Completed */ + cbz \wt, 3b + + ldr \wt, [\xb, #UARTSR] /* <= Status Register */ + orr \wt, \wt, #UARTSR_DTFTFF /* Clear DTF bit */ + str \wt, [\xb, #UARTSR] +2: +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ \ No newline at end of file From patchwork Tue Sep 10 14:34:09 2024 Content-Type: text/plain; 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From: "Andrei Cherechesu (OSS)" To: xen-devel@lists.xenproject.org Cc: S32@nxp.com, andrei.cherechesu@oss.nxp.com, Andrei Cherechesu , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v1 3/5] xen/arm: platforms: Add NXP S32CC platform code Date: Tue, 10 Sep 2024 17:34:09 +0300 Message-ID: <20240910143411.178704-4-andrei.cherechesu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240910143411.178704-1-andrei.cherechesu@oss.nxp.com> References: <20240910143411.178704-1-andrei.cherechesu@oss.nxp.com> X-ClientProxiedBy: AM0P190CA0019.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:190::29) To PA4PR04MB9565.eurprd04.prod.outlook.com (2603:10a6:102:26b::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PA4PR04MB9565:EE_|AS8PR04MB7557:EE_ X-MS-Office365-Filtering-Correlation-Id: 34872067-0a8e-466f-f85e-08dcd1a5b162 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|52116014|376014|38350700014; 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Linux relies on the SCMI Platform for system services such as clocking, reset, etc. S32CC platforms use the NXP LINFlexD UART driver for console by default. Signed-off-by: Andrei Cherechesu --- xen/arch/arm/platforms/Kconfig | 10 ++++ xen/arch/arm/platforms/Makefile | 1 + xen/arch/arm/platforms/s32cc.c | 84 +++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 xen/arch/arm/platforms/s32cc.c diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfig index 76f7e76b1b..310b35122a 100644 --- a/xen/arch/arm/platforms/Kconfig +++ b/xen/arch/arm/platforms/Kconfig @@ -37,6 +37,13 @@ config MPSOC help Enable all the required drivers for Xilinx Ultrascale+ MPSoC +config S32CC + bool "NXP S32CC platforms support" + depends on ARM_64 + select HAS_LINFLEX + help + Enable all the required drivers for NXP S32CC platforms + config NO_PLAT bool "No Platforms" help @@ -56,3 +63,6 @@ config MPSOC_PLATFORM bool default (ALL64_PLAT || MPSOC) +config S32CC_PLATFORM + bool + default (ALL64_PLAT || S32CC) diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile index bec6e55d1f..2c304b964d 100644 --- a/xen/arch/arm/platforms/Makefile +++ b/xen/arch/arm/platforms/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_ALL64_PLAT) += thunderx.o obj-$(CONFIG_ALL64_PLAT) += xgene-storm.o obj-$(CONFIG_ALL64_PLAT) += brcm-raspberry-pi.o obj-$(CONFIG_ALL64_PLAT) += imx8qm.o +obj-$(CONFIG_S32CC_PLATFORM) += s32cc.o obj-$(CONFIG_MPSOC_PLATFORM) += xilinx-zynqmp.o obj-$(CONFIG_MPSOC_PLATFORM) += xilinx-zynqmp-eemi.o diff --git a/xen/arch/arm/platforms/s32cc.c b/xen/arch/arm/platforms/s32cc.c new file mode 100644 index 0000000000..f262673b09 --- /dev/null +++ b/xen/arch/arm/platforms/s32cc.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * xen/arch/arm/platforms/s32cc.c + * + * NXP S32CC Platform-specific settings + * + * Andrei Cherechesu + * Copyright 2021-2024 NXP + */ + +#include +#include +#include + +#define S32CC_SMC_SCMI_FN 0xFE +#define S32CC_SMCCC_FID(fn) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_64, \ + ARM_SMCCC_OWNER_SIP, \ + fn) + +static bool s32cc_smc(struct cpu_user_regs *regs) +{ + struct arm_smccc_res res; + uint32_t fid = get_user_reg(regs, 0); + + /* Check for SMCCC 1.1 availability */ + if ( !cpus_have_const_cap(ARM_SMCCC_1_1) ) + { + printk_once(XENLOG_WARNING + "S32CC: No SMCCC 1.1 support, disabling fw calls."); + return false; + } + + switch ( fid ) + { + /* SCMI */ + case S32CC_SMCCC_FID(S32CC_SMC_SCMI_FN): + goto forward_to_fw; + + default: + printk_once(XENLOG_WARNING "S32CC: Unhandled SMC call: %u\n", fid); + return false; + } + +forward_to_fw: + arm_smccc_1_1_smc(fid, + get_user_reg(regs, 1), + get_user_reg(regs, 2), + get_user_reg(regs, 3), + get_user_reg(regs, 4), + get_user_reg(regs, 5), + get_user_reg(regs, 6), + get_user_reg(regs, 7), + &res); + + set_user_reg(regs, 0, res.a0); + set_user_reg(regs, 1, res.a1); + set_user_reg(regs, 2, res.a2); + set_user_reg(regs, 3, res.a3); + + return true; +} + +static const char * const s32cc_dt_compat[] __initconst = +{ + "nxp,s32g2", + "nxp,s32g3", + "nxp,s32r45", + NULL +}; + +PLATFORM_START(s32cc, "NXP S32CC") + .compatible = s32cc_dt_compat, + .smc = s32cc_smc, +PLATFORM_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ \ No newline at end of file From patchwork Tue Sep 10 14:34:10 2024 Content-Type: text/plain; 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Signed-off-by: Andrei Cherechesu --- xen/arch/arm/Kconfig.debug | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/Kconfig.debug b/xen/arch/arm/Kconfig.debug index a309f67f90..9725f4193c 100644 --- a/xen/arch/arm/Kconfig.debug +++ b/xen/arch/arm/Kconfig.debug @@ -168,6 +168,9 @@ choice config EARLY_PRINTK_RCAR3 bool "Early printk with SCIF2 on Renesas R-Car Gen3 processors" select EARLY_UART_SCIF + config EARLY_PRINTK_S32CC + bool "Early printk with NXP LINFlexD UART on NXP S32CC processors" + select EARLY_UART_LINFLEX config EARLY_PRINTK_SEATTLE bool "Early printk with pl011 for AMD Seattle processor" select EARLY_UART_PL011 @@ -243,6 +246,7 @@ config EARLY_UART_BASE_ADDRESS default 0xd0012000 if EARLY_PRINTK_MVEBU default 0x48020000 if EARLY_PRINTK_OMAP5432 default 0xe6e88000 if EARLY_PRINTK_RCAR3 + default 0x401c8000 if EARLY_PRINTK_S32CC default 0xe1010000 if EARLY_PRINTK_SEATTLE default 0x01c28000 if EARLY_PRINTK_SUN6I default 0x01c28000 if EARLY_PRINTK_SUN7I From patchwork Tue Sep 10 14:34:11 2024 Content-Type: text/plain; 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Enabled ARM64_WORKAROUND_AT_SPECULATE for all versions of Cortex-A53 cores, to avoid corrupting the TLB if performing a speculative AT instruction during a guest context switch. Signed-off-by: Andrei Cherechesu Acked-by: Julien Grall --- docs/misc/arm/silicon-errata.txt | 1 + xen/arch/arm/cpuerrata.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt index fffca09656..853e06aec1 100644 --- a/docs/misc/arm/silicon-errata.txt +++ b/docs/misc/arm/silicon-errata.txt @@ -46,6 +46,7 @@ stable hypervisors. | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 | | ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 | +| ARM | Cortex-A53 | #1530924 | N/A | | ARM | Cortex-A55 | #1530923 | N/A | | ARM | Cortex-A57 | #852523 | N/A | | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 2b7101ea25..afd0605922 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -683,6 +683,12 @@ static const struct arm_cpu_capabilities arm_errata[] = { .capability = ARM64_WORKAROUND_AT_SPECULATE, MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), }, + { + /* Cortex-A53 (All versions) */ + .desc = "ARM erratum 1530924", + .capability = ARM64_WORKAROUND_AT_SPECULATE, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), + }, {}, };