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This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. Currently, device controller will do nothing when endpoints met transfer error if IOC didn't set on that error dTD since UI didn't assert too. This will also handle UEI event as same as USBSTS.UI for such cases. Signed-off-by: Xu Yang Acked-by: Peter Chen --- drivers/usb/chipidea/udc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c index 69ef3cd8d4f8..b9ccf62e0a50 100644 --- a/drivers/usb/chipidea/udc.c +++ b/drivers/usb/chipidea/udc.c @@ -2063,7 +2063,7 @@ static irqreturn_t udc_irq(struct ci_hdrc *ci) } } - if (USBi_UI & intr) + if ((USBi_UI | USBi_UEI) & intr) isr_tr_complete_handler(ci); if ((USBi_SLI & intr) && !(ci->suspended)) { From patchwork Thu Sep 12 03:35:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13801346 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2045.outbound.protection.outlook.com [40.107.20.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05C1C15CD49 for ; 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But this code has a bug when the endpoint is already in error before polling ATDTW or just met error during polling ATDTW. In that cases, ATDTW will never turn to 1 and the cpu will busy loop there. When the endpoint met error, ENDPTSTAT will be cleared by HW. Therefore, ENDPTSTAT should also be considered during this process. In case of endpoint error, the current dTD should not be pushed to the head of dQH since some dTDs may be still not executed. Therefore, the link logic is also improved accordingly. Signed-off-by: Xu Yang --- drivers/usb/chipidea/udc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c index b9ccf62e0a50..0ab57b87b07b 100644 --- a/drivers/usb/chipidea/udc.c +++ b/drivers/usb/chipidea/udc.c @@ -612,10 +612,17 @@ static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq) do { hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW); tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n)); - } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW)); + } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW) && tmp_stat); hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0); if (tmp_stat) goto done; + + /* In case of error, ENDPTSTAT will also turn into 0, then + * don't push this dTD to dQH head if current dTD pointer + * is not the last dTD in previous request. + */ + if (hwep->qh.ptr->curr != prevlastnode->dma) + goto done; } /* QH configuration */ From patchwork Thu Sep 12 03:35:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13801347 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2045.outbound.protection.outlook.com [40.107.20.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC2251714CC for ; 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Finally, USBSTS.UEI will be set. Due to isoc transfers are error-tolerant transfers, we can make isoc endpoint a bit error tolerant on device mode too. In case of error, it's possilbe to resume the endpoint by reprime the corresponding endpoint. When error occurs, this will allow error dTD be deleted from dQH and giveback request to user. Then, a reprime/prime operation is executed depends on whether dQH is empty or not. If dQH is not empty, reprime will be done during dequeue process. If dQH is empty, prime will be done when new dTD is linked. In this way, isoc transfer can be recovered from a small number of errors. Signed-off-by: Xu Yang --- drivers/usb/chipidea/udc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c index 0ab57b87b07b..b1a1be6439b6 100644 --- a/drivers/usb/chipidea/udc.c +++ b/drivers/usb/chipidea/udc.c @@ -683,6 +683,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq) unsigned remaining_length; unsigned actual = hwreq->req.length; struct ci_hdrc *ci = hwep->ci; + bool is_isoc = hwep->type == USB_ENDPOINT_XFER_ISOC; if (hwreq->req.status != -EALREADY) return -EINVAL; @@ -696,7 +697,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq) int n = hw_ep_bit(hwep->num, hwep->dir); if (ci->rev == CI_REVISION_24 || - ci->rev == CI_REVISION_22) + ci->rev == CI_REVISION_22 || is_isoc) if (!hw_read(ci, OP_ENDPTSTAT, BIT(n))) reprime_dtd(ci, hwep, node); hwreq->req.status = -EALREADY; @@ -707,7 +708,6 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq) remaining_length >>= __ffs(TD_TOTAL_BYTES); actual -= remaining_length; - hwreq->req.status = tmptoken & TD_STATUS; if ((TD_STATUS_HALTED & hwreq->req.status)) { hwreq->req.status = -EPIPE; break; @@ -715,11 +715,13 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq) hwreq->req.status = -EPROTO; break; } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) { - hwreq->req.status = -EILSEQ; - break; + if (!is_isoc) { + hwreq->req.status = -EILSEQ; + break; + } } - if (remaining_length) { + if (remaining_length && !is_isoc) { if (hwep->dir == TX) { hwreq->req.status = -EPROTO; break;