From patchwork Thu Sep 12 07:08:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801525 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2088.outbound.protection.outlook.com [40.107.93.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D564F189BBF for ; Thu, 12 Sep 2024 07:08:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.88 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124925; cv=fail; b=d6QWKS3LiWm0kgPAlPSfZZzWANkEO2XY5dN19U3ebMD0Z8uKI0VCIHOThQCvSpcEmclpHiEJNaiETsfclI53Q1LdHgmiT3tXxy9ztSNILnkHSSDiDSoeBl4RLc6kHXkZkdxtEP0629m57Ny0nEzoWXXzBFFJUeGpMesWqa0Svoc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124925; c=relaxed/simple; bh=LyJgzTqxjOXGiWyJWlqerl6GyeQ6WczcDaeXJKKQvDk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TnOW4OmQZy5WVmIUz0/Wu4VFvRcgbTyizVlcfHREmsV9yQAqfsyRwiUObtoweoJRXj2wN8I0Iuf8O4qzrcheus20SFtqEOvTRlMqrBnXu9zkkX3rcnrFz6t3YiwUBgM9gYK9EEdvYcafsLA0yk6Jbmq3eoBr+jk69cylA8yQLXc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=fGM8HOk8; arc=fail smtp.client-ip=40.107.93.88 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="fGM8HOk8" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=GtOUsiUOIwqehZyEw+JVWqc437PO+GVzZoxYiXEEaV1mSiil7Lg/wNByrYgNlbd589tZifTSVkiP0xmDnX85cqx9Xawod1KsmReN0n/NRPyLmSLY8rJdNOzHM/oalVBgr29M5PcTfnY29B6Hdn3hxkcUcY2JwvIN00+/7SgvWGyaKyu0uej9j49jmBoTd/Zj729P5+w+hplye3p0AU8fW5gP1jCnulGtZDsFtjXy6nKKdrzzh/lhLIeanoz0dz1vQuqXFNPVCeluPUu9VOcLcmablcwJLVwtLma+wMqJ7qUayu2+VoCoKmaufuwHwd6tlYWhxyFJ2qjnMz4slhnKDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZehFrVfKcOnlrJfwljc6mnapNc8Y0Rqht4OwaeE63SM=; b=HpRlBmzQ5qvnocHjhbsZqh00XEqndGTcPuHZVqCCFauXRvF+tTUlyQe0Cmqg7fvI7obPjYDwMtd1fp2mCPvpx+T6cOzMDY3jvjltUCl1hTHo5ey2Eg8Jwf6+LoX+SLxaxhq/p/y6PGMVlH+GfNIhhkV0nu4EDq2mBql/IO8cjc9C9398Frrj9ISsL6BGRGMISqTWG4KzRkDHDeWWrHNlK+y/HTh9CkPV5QU/EY0i5z8MJpPKV7dRbIB+Oo8vR8A73dN7iM3ujMyeh3ZBKLkADBFV6qenGrGGDN7MwSNiQltCi4jDb4bqXe6CEFnVhX8fyUMHXTYgnmXHcrVM/t/wew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZehFrVfKcOnlrJfwljc6mnapNc8Y0Rqht4OwaeE63SM=; b=fGM8HOk8LbghHgkVbaXVo+BXw1PyQWTpqKCFs6t+O1iHcIrJZ4vzzKFed0DNgHR9jiK/RRYBdaQjBbvN2/3jDOHT2oI1uPMgBGPxj9grPXFsjdg2ELehrzrihQs5dNxWdB1CeB6HBFbuYsZlC5lXYAi5B+gw9DFKa4L1s6NZ2e0= Received: from CH2PR08CA0026.namprd08.prod.outlook.com (2603:10b6:610:5a::36) by CH0PR12MB8487.namprd12.prod.outlook.com (2603:10b6:610:18c::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.24; Thu, 12 Sep 2024 07:08:35 +0000 Received: from CH1PEPF0000AD7D.namprd04.prod.outlook.com (2603:10b6:610:5a:cafe::2b) by CH2PR08CA0026.outlook.office365.com (2603:10b6:610:5a::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.25 via Frontend Transport; Thu, 12 Sep 2024 07:08:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD7D.mail.protection.outlook.com (10.167.244.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:08:35 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:31 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 1/9] hwmon/misc: amd-sbi: Move core sbrmi from hwmon to misc Date: Thu, 12 Sep 2024 07:08:02 +0000 Message-ID: <20240912070810.1644621-2-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|CH0PR12MB8487:EE_ X-MS-Office365-Filtering-Correlation-Id: a56af153-ecd6-4d23-cc44-08dcd2f9b7c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: RLi1yf1FyC6ZkcVKuSsoZDjvjvHMZ8cBL8Tlooe7hzUiBeSqmek9/XiGQzGhN/wp5ITwqF+5wVpYNtGCksR6WD/VgXO64HCAq7d1wepN4h1h2N5depLSPAYZJbcqYJAWhIPKhRpijt4CkfDWpOTutuQbhEzl6HZOLWyJj78ADtpm2A0N8cRuKGz7DWA/lORZu81Qi48ArYKTjTHTPt28ousp6mujMmO8X5g86zBFrURFWpx58YOwwdHNOtXmv8knTtO2cc2TNp4NwSBLX7v67Xl+JXFjKIs7P7eJHfyjOZVTAfG0zbnDBj0kiCej38QIXtjrMv9KNV5JxcpSvtCpimOJa/DHAIsWpyAMBDJDyHicqqMdYqgBOUrMQNS6MmZZ+KfEeHulHyd4Sd5e63Ilgcw11bBYh+H5Zq6sJiS5PyAI8UubGqYKxI4lUp5dTh4S7TTX9LjMnFUdmRoeooS4gzzJm8nezI2PutMvL5NVSo0zS3pyPMtfGg9AufYnV02F8xzc2oN6vZvW5DEPAGPpIIKzFn/5eCrjgGsOGJx3hLmN5Wdfy7Xg8r4ysTOg6yHzilTw3RrBQrj7zFNHw4aKskZdogr2xkkGEZj0Pl3BgOHcYGIH3J1JZajgX1T5NShN3I3D2ZvZqmVO27LrUzwA7ClCt3yrpx/W5ev4j0ZKWSOz+GHdrjQPCsnhBYPi65uSwd8qzuAGEC1PQJVci/U5l1lhUiugeE2xXyDL2YtTZEUo0EysIHLM5CWicNQLdYPFZAOdTDWEkKGetkwoT6pcm+TYCm5L3qatHGTiIzNvR3SgdXTxF1npzPXgfOoafy9wQMpv2ynE+bYPUr5q0xLEByR5z4U4eo8zDmHqA+r1v+LUiW5CoGvtFs0f8mdxtifFdzlJ8LxI/SR3lWyAJRIk+S4cmWvwE22JYEpvOv5SAbVjOUl33M9y234czN91NMcV3c/EYDhDizDJb3fDDQ/mejuiLDOxfhBE6AOOv+1erA9/HwSWXu944frEBMfhZbb0d33N934sNzrM2dmdEgHUeFGs+Ap5RDCqX05c9xyDFttUfliwyY0aDY7Iljt5MXucpdk2NwKY1jImgK1V/QZgAwOnKJ/sU/XCuN7hkkOujJE/Ev3lh6CR66Uh2A8BNyBRZl3PpJWRALlD2XCGQdgN1i7sG24jcYqsWqrZKv0siIWDuimEj2/CIllvYNXvow1BLiUhLHhlbIwDbHbNlvERmd+1rVtQp/g2tzXHcKYcerC7dypQ2MxlXAfCatJhyzHyR59YaOxq1wsIhv4GrzQ4POoHRcLLCKHyEaHC2LOrtDES0X2FvEXSc0yk1j82tUmj41Ewz2Wcn5PuXctviPDndJd2aECl09hr6O5mGpuZK7ZzISOS09kJIWZuFXOpk2tDNhZ9X1yrViA63PLcM4n1NVYwKIg8koLFOr2FD9zPQWcr0OxYTqaZwn1EXwDrIfgH X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:08:35.0935 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a56af153-ecd6-4d23-cc44-08dcd2f9b7c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8487 This is done to support other functionality provided by the SBRMI, which does not fit in the hwmon subsystem. - Move the SBRMI core functionality and I2C device probing part to misc. - Move hwmon device sensor to misc as only power is reported through hwmon sensor. Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi Acked-by: Guenter Roeck --- Changes since v3: Rebase the patch Added Acked-by Changes since v2: Rebase the patch Changes since v1: - File name update - Add hwmon sensor registration in this patch - Update Copyright year drivers/hwmon/Kconfig | 10 - drivers/hwmon/sbrmi.c | 357 ------------------------------- drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/amd-sbi/Kconfig | 9 + drivers/misc/amd-sbi/Makefile | 3 + drivers/misc/amd-sbi/rmi-core.c | 115 ++++++++++ drivers/misc/amd-sbi/rmi-core.h | 65 ++++++ drivers/misc/amd-sbi/rmi-hwmon.c | 121 +++++++++++ drivers/misc/amd-sbi/rmi-i2c.c | 111 ++++++++++ 10 files changed, 426 insertions(+), 367 deletions(-) delete mode 100644 drivers/hwmon/sbrmi.c create mode 100644 drivers/misc/amd-sbi/Kconfig create mode 100644 drivers/misc/amd-sbi/Makefile create mode 100644 drivers/misc/amd-sbi/rmi-core.c create mode 100644 drivers/misc/amd-sbi/rmi-core.h create mode 100644 drivers/misc/amd-sbi/rmi-hwmon.c create mode 100644 drivers/misc/amd-sbi/rmi-i2c.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index b60fe2e58ad6..20bd7126362c 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1823,16 +1823,6 @@ config SENSORS_SBTSI This driver can also be built as a module. If so, the module will be called sbtsi_temp. -config SENSORS_SBRMI - tristate "Emulated SB-RMI sensor" - depends on I2C - help - If you say yes here you get support for emulated RMI - sensors on AMD SoCs with APML interface connected to a BMC device. - - This driver can also be built as a module. If so, the module will - be called sbrmi. - config SENSORS_SHT15 tristate "Sensiron humidity and temperature sensors. SHT15 and compat." depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/hwmon/sbrmi.c b/drivers/hwmon/sbrmi.c deleted file mode 100644 index d48d8e5460ff..000000000000 --- a/drivers/hwmon/sbrmi.c +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * sbrmi.c - hwmon driver for a SB-RMI mailbox - * compliant AMD SoC device. - * - * Copyright (C) 2020-2021 Advanced Micro Devices, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* Do not allow setting negative power limit */ -#define SBRMI_PWR_MIN 0 -/* Mask for Status Register bit[1] */ -#define SW_ALERT_MASK 0x2 - -/* Software Interrupt for triggering */ -#define START_CMD 0x80 -#define TRIGGER_MAILBOX 0x01 - -/* - * SB-RMI supports soft mailbox service request to MP1 (power management - * firmware) through SBRMI inbound/outbound message registers. - * SB-RMI message IDs - */ -enum sbrmi_msg_id { - SBRMI_READ_PKG_PWR_CONSUMPTION = 0x1, - SBRMI_WRITE_PKG_PWR_LIMIT, - SBRMI_READ_PKG_PWR_LIMIT, - SBRMI_READ_PKG_MAX_PWR_LIMIT, -}; - -/* SB-RMI registers */ -enum sbrmi_reg { - SBRMI_CTRL = 0x01, - SBRMI_STATUS, - SBRMI_OUTBNDMSG0 = 0x30, - SBRMI_OUTBNDMSG1, - SBRMI_OUTBNDMSG2, - SBRMI_OUTBNDMSG3, - SBRMI_OUTBNDMSG4, - SBRMI_OUTBNDMSG5, - SBRMI_OUTBNDMSG6, - SBRMI_OUTBNDMSG7, - SBRMI_INBNDMSG0, - SBRMI_INBNDMSG1, - SBRMI_INBNDMSG2, - SBRMI_INBNDMSG3, - SBRMI_INBNDMSG4, - SBRMI_INBNDMSG5, - SBRMI_INBNDMSG6, - SBRMI_INBNDMSG7, - SBRMI_SW_INTERRUPT, -}; - -/* Each client has this additional data */ -struct sbrmi_data { - struct i2c_client *client; - struct mutex lock; - u32 pwr_limit_max; -}; - -struct sbrmi_mailbox_msg { - u8 cmd; - bool read; - u32 data_in; - u32 data_out; -}; - -static int sbrmi_enable_alert(struct i2c_client *client) -{ - int ctrl; - - /* - * Enable the SB-RMI Software alert status - * by writing 0 to bit 4 of Control register(0x1) - */ - ctrl = i2c_smbus_read_byte_data(client, SBRMI_CTRL); - if (ctrl < 0) - return ctrl; - - if (ctrl & 0x10) { - ctrl &= ~0x10; - return i2c_smbus_write_byte_data(client, - SBRMI_CTRL, ctrl); - } - - return 0; -} - -static int rmi_mailbox_xfer(struct sbrmi_data *data, - struct sbrmi_mailbox_msg *msg) -{ - int i, ret, retry = 10; - int sw_status; - u8 byte; - - mutex_lock(&data->lock); - - /* Indicate firmware a command is to be serviced */ - ret = i2c_smbus_write_byte_data(data->client, - SBRMI_INBNDMSG7, START_CMD); - if (ret < 0) - goto exit_unlock; - - /* Write the command to SBRMI::InBndMsg_inst0 */ - ret = i2c_smbus_write_byte_data(data->client, - SBRMI_INBNDMSG0, msg->cmd); - if (ret < 0) - goto exit_unlock; - - /* - * For both read and write the initiator (BMC) writes - * Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1] - * SBRMI_x3C(MSB):SBRMI_x39(LSB) - */ - for (i = 0; i < 4; i++) { - byte = (msg->data_in >> i * 8) & 0xff; - ret = i2c_smbus_write_byte_data(data->client, - SBRMI_INBNDMSG1 + i, byte); - if (ret < 0) - goto exit_unlock; - } - - /* - * Write 0x01 to SBRMI::SoftwareInterrupt to notify firmware to - * perform the requested read or write command - */ - ret = i2c_smbus_write_byte_data(data->client, - SBRMI_SW_INTERRUPT, TRIGGER_MAILBOX); - if (ret < 0) - goto exit_unlock; - - /* - * Firmware will write SBRMI::Status[SwAlertSts]=1 to generate - * an ALERT (if enabled) to initiator (BMC) to indicate completion - * of the requested command - */ - do { - sw_status = i2c_smbus_read_byte_data(data->client, - SBRMI_STATUS); - if (sw_status < 0) { - ret = sw_status; - goto exit_unlock; - } - if (sw_status & SW_ALERT_MASK) - break; - usleep_range(50, 100); - } while (retry--); - - if (retry < 0) { - dev_err(&data->client->dev, - "Firmware fail to indicate command completion\n"); - ret = -EIO; - goto exit_unlock; - } - - /* - * For a read operation, the initiator (BMC) reads the firmware - * response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1] - * {SBRMI_x34(MSB):SBRMI_x31(LSB)}. - */ - if (msg->read) { - for (i = 0; i < 4; i++) { - ret = i2c_smbus_read_byte_data(data->client, - SBRMI_OUTBNDMSG1 + i); - if (ret < 0) - goto exit_unlock; - msg->data_out |= ret << i * 8; - } - } - - /* - * BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the - * ALERT to initiator - */ - ret = i2c_smbus_write_byte_data(data->client, SBRMI_STATUS, - sw_status | SW_ALERT_MASK); - -exit_unlock: - mutex_unlock(&data->lock); - return ret; -} - -static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, - u32 attr, int channel, long *val) -{ - struct sbrmi_data *data = dev_get_drvdata(dev); - struct sbrmi_mailbox_msg msg = { 0 }; - int ret; - - if (type != hwmon_power) - return -EINVAL; - - msg.read = true; - switch (attr) { - case hwmon_power_input: - msg.cmd = SBRMI_READ_PKG_PWR_CONSUMPTION; - ret = rmi_mailbox_xfer(data, &msg); - break; - case hwmon_power_cap: - msg.cmd = SBRMI_READ_PKG_PWR_LIMIT; - ret = rmi_mailbox_xfer(data, &msg); - break; - case hwmon_power_cap_max: - msg.data_out = data->pwr_limit_max; - ret = 0; - break; - default: - return -EINVAL; - } - if (ret < 0) - return ret; - /* hwmon power attributes are in microWatt */ - *val = (long)msg.data_out * 1000; - return ret; -} - -static int sbrmi_write(struct device *dev, enum hwmon_sensor_types type, - u32 attr, int channel, long val) -{ - struct sbrmi_data *data = dev_get_drvdata(dev); - struct sbrmi_mailbox_msg msg = { 0 }; - - if (type != hwmon_power && attr != hwmon_power_cap) - return -EINVAL; - /* - * hwmon power attributes are in microWatt - * mailbox read/write is in mWatt - */ - val /= 1000; - - val = clamp_val(val, SBRMI_PWR_MIN, data->pwr_limit_max); - - msg.cmd = SBRMI_WRITE_PKG_PWR_LIMIT; - msg.data_in = val; - msg.read = false; - - return rmi_mailbox_xfer(data, &msg); -} - -static umode_t sbrmi_is_visible(const void *data, - enum hwmon_sensor_types type, - u32 attr, int channel) -{ - switch (type) { - case hwmon_power: - switch (attr) { - case hwmon_power_input: - case hwmon_power_cap_max: - return 0444; - case hwmon_power_cap: - return 0644; - } - break; - default: - break; - } - return 0; -} - -static const struct hwmon_channel_info * const sbrmi_info[] = { - HWMON_CHANNEL_INFO(power, - HWMON_P_INPUT | HWMON_P_CAP | HWMON_P_CAP_MAX), - NULL -}; - -static const struct hwmon_ops sbrmi_hwmon_ops = { - .is_visible = sbrmi_is_visible, - .read = sbrmi_read, - .write = sbrmi_write, -}; - -static const struct hwmon_chip_info sbrmi_chip_info = { - .ops = &sbrmi_hwmon_ops, - .info = sbrmi_info, -}; - -static int sbrmi_get_max_pwr_limit(struct sbrmi_data *data) -{ - struct sbrmi_mailbox_msg msg = { 0 }; - int ret; - - msg.cmd = SBRMI_READ_PKG_MAX_PWR_LIMIT; - msg.read = true; - ret = rmi_mailbox_xfer(data, &msg); - if (ret < 0) - return ret; - data->pwr_limit_max = msg.data_out; - - return ret; -} - -static int sbrmi_probe(struct i2c_client *client) -{ - struct device *dev = &client->dev; - struct device *hwmon_dev; - struct sbrmi_data *data; - int ret; - - data = devm_kzalloc(dev, sizeof(struct sbrmi_data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - data->client = client; - mutex_init(&data->lock); - - /* Enable alert for SB-RMI sequence */ - ret = sbrmi_enable_alert(client); - if (ret < 0) - return ret; - - /* Cache maximum power limit */ - ret = sbrmi_get_max_pwr_limit(data); - if (ret < 0) - return ret; - - hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data, - &sbrmi_chip_info, NULL); - - return PTR_ERR_OR_ZERO(hwmon_dev); -} - -static const struct i2c_device_id sbrmi_id[] = { - {"sbrmi"}, - {} -}; -MODULE_DEVICE_TABLE(i2c, sbrmi_id); - -static const struct of_device_id __maybe_unused sbrmi_of_match[] = { - { - .compatible = "amd,sbrmi", - }, - { }, -}; -MODULE_DEVICE_TABLE(of, sbrmi_of_match); - -static struct i2c_driver sbrmi_driver = { - .driver = { - .name = "sbrmi", - .of_match_table = of_match_ptr(sbrmi_of_match), - }, - .probe = sbrmi_probe, - .id_table = sbrmi_id, -}; - -module_i2c_driver(sbrmi_driver); - -MODULE_AUTHOR("Akshay Gupta "); -MODULE_DESCRIPTION("Hwmon driver for AMD SB-RMI emulated sensor"); -MODULE_LICENSE("GPL"); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 41c3d2821a78..add70bc22fee 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -618,4 +618,5 @@ source "drivers/misc/uacce/Kconfig" source "drivers/misc/pvpanic/Kconfig" source "drivers/misc/mchp_pci1xxxx/Kconfig" source "drivers/misc/keba/Kconfig" +source "drivers/misc/amd-sbi/Kconfig" endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index c2f990862d2b..5e70d2b34a11 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -71,3 +71,4 @@ obj-$(CONFIG_TPS6594_PFSM) += tps6594-pfsm.o obj-$(CONFIG_NSM) += nsm.o obj-$(CONFIG_MARVELL_CN10K_DPI) += mrvl_cn10k_dpi.o obj-y += keba/ +obj-y += amd-sbi/ diff --git a/drivers/misc/amd-sbi/Kconfig b/drivers/misc/amd-sbi/Kconfig new file mode 100644 index 000000000000..be2d9e495eb7 --- /dev/null +++ b/drivers/misc/amd-sbi/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only +config AMD_SBRMI_I2C + tristate "AMD side band RMI support" + depends on I2C + help + Side band RMI over I2C support for AMD out of band management. + + This driver can also be built as a module. If so, the module will + be called sbrmi-i2c. diff --git a/drivers/misc/amd-sbi/Makefile b/drivers/misc/amd-sbi/Makefile new file mode 100644 index 000000000000..eac90a7635de --- /dev/null +++ b/drivers/misc/amd-sbi/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +sbrmi-i2c-objs := rmi-i2c.o rmi-core.o rmi-hwmon.o +obj-$(CONFIG_AMD_SBRMI_I2C) += sbrmi-i2c.o diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c new file mode 100644 index 000000000000..5d93fb703fa0 --- /dev/null +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * sbrmi-core.c - file defining SB-RMI protocols compliant + * AMD SoC device. + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. + */ +#include +#include +#include +#include +#include "rmi-core.h" + +/* Mask for Status Register bit[1] */ +#define SW_ALERT_MASK 0x2 +/* Do not allow setting negative power limit */ +#define SBRMI_PWR_MIN 0 + +/* Software Interrupt for triggering */ +#define START_CMD 0x80 +#define TRIGGER_MAILBOX 0x01 + +int rmi_mailbox_xfer(struct sbrmi_data *data, + struct sbrmi_mailbox_msg *msg) +{ + int i, ret, retry = 10; + int sw_status; + u8 byte; + + mutex_lock(&data->lock); + + /* Indicate firmware a command is to be serviced */ + ret = i2c_smbus_write_byte_data(data->client, + SBRMI_INBNDMSG7, START_CMD); + if (ret < 0) + goto exit_unlock; + + /* Write the command to SBRMI::InBndMsg_inst0 */ + ret = i2c_smbus_write_byte_data(data->client, + SBRMI_INBNDMSG0, msg->cmd); + if (ret < 0) + goto exit_unlock; + + /* + * For both read and write the initiator (BMC) writes + * Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1] + * SBRMI_x3C(MSB):SBRMI_x39(LSB) + */ + for (i = 0; i < 4; i++) { + byte = (msg->data_in >> i * 8) & 0xff; + ret = i2c_smbus_write_byte_data(data->client, + SBRMI_INBNDMSG1 + i, byte); + if (ret < 0) + goto exit_unlock; + } + + /* + * Write 0x01 to SBRMI::SoftwareInterrupt to notify firmware to + * perform the requested read or write command + */ + ret = i2c_smbus_write_byte_data(data->client, + SBRMI_SW_INTERRUPT, TRIGGER_MAILBOX); + if (ret < 0) + goto exit_unlock; + + /* + * Firmware will write SBRMI::Status[SwAlertSts]=1 to generate + * an ALERT (if enabled) to initiator (BMC) to indicate completion + * of the requested command + */ + do { + sw_status = i2c_smbus_read_byte_data(data->client, + SBRMI_STATUS); + if (sw_status < 0) { + ret = sw_status; + goto exit_unlock; + } + if (sw_status & SW_ALERT_MASK) + break; + usleep_range(50, 100); + } while (retry--); + + if (retry < 0) { + dev_err(&data->client->dev, + "Firmware fail to indicate command completion\n"); + ret = -EIO; + goto exit_unlock; + } + + /* + * For a read operation, the initiator (BMC) reads the firmware + * response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1] + * {SBRMI_x34(MSB):SBRMI_x31(LSB)}. + */ + if (msg->read) { + for (i = 0; i < 4; i++) { + ret = i2c_smbus_read_byte_data(data->client, + SBRMI_OUTBNDMSG1 + i); + if (ret < 0) + goto exit_unlock; + msg->data_out |= ret << i * 8; + } + } + + /* + * BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the + * ALERT to initiator + */ + ret = i2c_smbus_write_byte_data(data->client, SBRMI_STATUS, + sw_status | SW_ALERT_MASK); + +exit_unlock: + mutex_unlock(&data->lock); + return ret; +} diff --git a/drivers/misc/amd-sbi/rmi-core.h b/drivers/misc/amd-sbi/rmi-core.h new file mode 100644 index 000000000000..3d600e450e08 --- /dev/null +++ b/drivers/misc/amd-sbi/rmi-core.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 Advanced Micro Devices, Inc. + */ + +#ifndef _SBRMI_CORE_H_ +#define _SBRMI_CORE_H_ + +#include +#include +#include + +/* SB-RMI registers */ +enum sbrmi_reg { + SBRMI_CTRL = 0x01, + SBRMI_STATUS, + SBRMI_OUTBNDMSG0 = 0x30, + SBRMI_OUTBNDMSG1, + SBRMI_OUTBNDMSG2, + SBRMI_OUTBNDMSG3, + SBRMI_OUTBNDMSG4, + SBRMI_OUTBNDMSG5, + SBRMI_OUTBNDMSG6, + SBRMI_OUTBNDMSG7, + SBRMI_INBNDMSG0, + SBRMI_INBNDMSG1, + SBRMI_INBNDMSG2, + SBRMI_INBNDMSG3, + SBRMI_INBNDMSG4, + SBRMI_INBNDMSG5, + SBRMI_INBNDMSG6, + SBRMI_INBNDMSG7, + SBRMI_SW_INTERRUPT, +}; + +/* + * SB-RMI supports soft mailbox service request to MP1 (power management + * firmware) through SBRMI inbound/outbound message registers. + * SB-RMI message IDs + */ +enum sbrmi_msg_id { + SBRMI_READ_PKG_PWR_CONSUMPTION = 0x1, + SBRMI_WRITE_PKG_PWR_LIMIT, + SBRMI_READ_PKG_PWR_LIMIT, + SBRMI_READ_PKG_MAX_PWR_LIMIT, +}; + +/* Each client has this additional data */ +struct sbrmi_data { + struct i2c_client *client; + struct mutex lock; + struct platform_device *pdev; + u32 pwr_limit_max; +}; + +struct sbrmi_mailbox_msg { + u8 cmd; + bool read; + u32 data_in; + u32 data_out; +}; + +int rmi_mailbox_xfer(struct sbrmi_data *data, struct sbrmi_mailbox_msg *msg); +int create_hwmon_sensor_device(struct device *dev, struct sbrmi_data *data); +#endif /*_SBRMI_CORE_H_*/ diff --git a/drivers/misc/amd-sbi/rmi-hwmon.c b/drivers/misc/amd-sbi/rmi-hwmon.c new file mode 100644 index 000000000000..36913f105eef --- /dev/null +++ b/drivers/misc/amd-sbi/rmi-hwmon.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * rmi-hwmon.c - hwmon sensor support for side band RMI + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. + */ +#include +#include +#include "rmi-core.h" + +/* Do not allow setting negative power limit */ +#define SBRMI_PWR_MIN 0 + +static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct sbrmi_data *data = dev_get_drvdata(dev); + struct sbrmi_mailbox_msg msg = { 0 }; + int ret; + + if (!data) + return -ENODEV; + + if (type != hwmon_power) + return -EINVAL; + + msg.read = true; + switch (attr) { + case hwmon_power_input: + msg.cmd = SBRMI_READ_PKG_PWR_CONSUMPTION; + ret = rmi_mailbox_xfer(data, &msg); + break; + case hwmon_power_cap: + msg.cmd = SBRMI_READ_PKG_PWR_LIMIT; + ret = rmi_mailbox_xfer(data, &msg); + break; + case hwmon_power_cap_max: + msg.data_out = data->pwr_limit_max; + ret = 0; + break; + default: + return -EINVAL; + } + if (ret < 0) + return ret; + /* hwmon power attributes are in microWatt */ + *val = (long)msg.data_out * 1000; + return ret; +} + +static int sbrmi_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct sbrmi_data *data = dev_get_drvdata(dev); + struct sbrmi_mailbox_msg msg = { 0 }; + + if (!data) + return -ENODEV; + + if (type != hwmon_power && attr != hwmon_power_cap) + return -EINVAL; + /* + * hwmon power attributes are in microWatt + * mailbox read/write is in mWatt + */ + val /= 1000; + + val = clamp_val(val, SBRMI_PWR_MIN, data->pwr_limit_max); + + msg.cmd = SBRMI_WRITE_PKG_PWR_LIMIT; + msg.data_in = val; + msg.read = false; + + return rmi_mailbox_xfer(data, &msg); +} + +static umode_t sbrmi_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_power: + switch (attr) { + case hwmon_power_input: + case hwmon_power_cap_max: + return 0444; + case hwmon_power_cap: + return 0644; + } + break; + default: + break; + } + return 0; +} + +static const struct hwmon_channel_info * const sbrmi_info[] = { + HWMON_CHANNEL_INFO(power, + HWMON_P_INPUT | HWMON_P_CAP | HWMON_P_CAP_MAX), + NULL +}; + +static const struct hwmon_ops sbrmi_hwmon_ops = { + .is_visible = sbrmi_is_visible, + .read = sbrmi_read, + .write = sbrmi_write, +}; + +static const struct hwmon_chip_info sbrmi_chip_info = { + .ops = &sbrmi_hwmon_ops, + .info = sbrmi_info, +}; + +int create_hwmon_sensor_device(struct device *dev, struct sbrmi_data *data) +{ + struct device *hwmon_dev; + + hwmon_dev = devm_hwmon_device_register_with_info(dev, "sbrmi", data, + &sbrmi_chip_info, NULL); + return PTR_ERR_OR_ZERO(hwmon_dev); +} diff --git a/drivers/misc/amd-sbi/rmi-i2c.c b/drivers/misc/amd-sbi/rmi-i2c.c new file mode 100644 index 000000000000..ae968cf3c29c --- /dev/null +++ b/drivers/misc/amd-sbi/rmi-i2c.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * rmi-i2c.c - Side band RMI over I2C support for AMD out + * of band management + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "rmi-core.h" + +#define SBRMI_CTRL 0x1 + +static int sbrmi_enable_alert(struct i2c_client *client) +{ + int ctrl; + + /* + * Enable the SB-RMI Software alert status + * by writing 0 to bit 4 of Control register(0x1) + */ + ctrl = i2c_smbus_read_byte_data(client, SBRMI_CTRL); + if (ctrl < 0) + return ctrl; + + if (ctrl & 0x10) { + ctrl &= ~0x10; + return i2c_smbus_write_byte_data(client, + SBRMI_CTRL, ctrl); + } + + return 0; +} + +static int sbrmi_get_max_pwr_limit(struct sbrmi_data *data) +{ + struct sbrmi_mailbox_msg msg = { 0 }; + int ret; + + msg.cmd = SBRMI_READ_PKG_MAX_PWR_LIMIT; + msg.read = true; + ret = rmi_mailbox_xfer(data, &msg); + if (ret < 0) + return ret; + data->pwr_limit_max = msg.data_out; + + return ret; +} + +static int sbrmi_i2c_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct sbrmi_data *data; + int ret; + + data = devm_kzalloc(dev, sizeof(struct sbrmi_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client = client; + mutex_init(&data->lock); + + /* Enable alert for SB-RMI sequence */ + ret = sbrmi_enable_alert(client); + if (ret < 0) + return ret; + + /* Cache maximum power limit */ + ret = sbrmi_get_max_pwr_limit(data); + if (ret < 0) + return ret; + + dev_set_drvdata(dev, data); + return create_hwmon_sensor_device(dev, data); +} + +static const struct i2c_device_id sbrmi_id[] = { + {"sbrmi-i2c"}, + {} +}; +MODULE_DEVICE_TABLE(i2c, sbrmi_id); + +static const struct of_device_id __maybe_unused sbrmi_of_match[] = { + { + .compatible = "amd,sbrmi", + }, + { }, +}; +MODULE_DEVICE_TABLE(of, sbrmi_of_match); + +static struct i2c_driver sbrmi_driver = { + .driver = { + .name = "sbrmi-i2c", + .of_match_table = of_match_ptr(sbrmi_of_match), + }, + .probe = sbrmi_i2c_probe, + .id_table = sbrmi_id, +}; + +module_i2c_driver(sbrmi_driver); + +MODULE_AUTHOR("Akshay Gupta "); +MODULE_AUTHOR("Naveen Krishna Chatradhi "); +MODULE_DESCRIPTION("Hwmon driver for AMD SB-RMI emulated sensor"); +MODULE_LICENSE("GPL"); From patchwork Thu Sep 12 07:08:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801524 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2085.outbound.protection.outlook.com [40.107.93.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E7BF189F2A for ; Thu, 12 Sep 2024 07:08:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.85 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124925; cv=fail; b=gLPhqXAKFq0pM6vUL+SVUMPoS8WxWpD8XvJd5oOiDRWHz6041Z/5P6Z5VaudEP//EgHTJ0y1gJiuC+jWX/JLZ97UlGZQYP4+uKeOoLvoCxPFEx8GGE12+nglwVAUKOwlG6XduRQ+RGYQvWKVaCJvtcH9A1oWM9D1X4GDw/3eNLI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124925; c=relaxed/simple; bh=jMv/QrqBJFuuYIVqev3tXqeWryWjk29ATHYANcNnXv8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h15CTWZGUBHCi2ny2xQOuNVux7l7dpqBiJ0tdJvSa01FFR8CCMxiKZ+O06TIUo+yelNT0v81C8VxU0mnVKcgjiN/LdSbwjxVvdsHcGuRk1O/fYV8LIiTbYFMTfFtJOslPP324zoCR8ezEA8Yl8qf7xK6AmQzuFpM5LFsjISCUsA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=kJMkAAjS; arc=fail smtp.client-ip=40.107.93.85 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="kJMkAAjS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=UbaimzdERKjLnMy1izcL+lWMajZqwmRP/PsHmvHFq0c+YJu4zMy3PhwZmiXta9eVU+JEilBmPyfhhriOTrG2Fux2HMiVrpnOBGYYButHcEBIenRVaF7GvJl/F7xQKwAy2/kF38NoNoVTg8se+hZwdWgqdeHn0pfmt8RusJKQGO6llSIeD7Z4HWcexrtfTAcmTooCPnxs+8TkuY1ls8ROCKq3aim7LAn+ddGK7m+QJ3R1cMBhcwGtTKsB+X4hAGMs4l/TIoEYO3oE8CZBpAfhjt2xBlkxzpsL08QlndNEStGbAlHUtIr2IViZEa19IZL5dHgQvrhVYZlSv2BLLLsssg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ioX+ve7GGeemcpIvhLj7o9nLzvlqlaRoA7YT3+R7ra8=; b=xfg6+QGbVxKY6C5vVqd0J9hyFvPZA3DL4TDwyxuRPhZIanRLEScKtPNcsEbmlluYu4EF7QtzOf1VXI+WdBJHwJWVjDKUxKN7qZBtbDrhs9h5GAk10V255QZcGbYS4ERK+YFceTyPt/zjEP8vBrTFJIDoIZ7pHvPqM0UUf2gWUt9JaTF+C54Hl+byurSUtjmDCaPJWY5nyIIB9jWY+JnP29bs5epoaVYy1Ly3Qhu5EEDl/hvmAvJIFSruVfKsjhca169fjK6Wp7P/8HuEhf+bqFnGIZwm7pcgFBiQNBlkOhP9NjrnE46EehCqCsgymqhSYO3pLwxUVS4MssggX1M+LA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ioX+ve7GGeemcpIvhLj7o9nLzvlqlaRoA7YT3+R7ra8=; b=kJMkAAjSrAsYPKfNnGtKwdh5nMFSYvW80s/0O58jV3TOBkG63l51wtS0dl4cf7r3IyT23zr+WAVW8ppMU3Uye1d6dtIm71XD1HGboAM45z2oS9DjBpgR/xcd7YIwDxOhOjjWOeT3JgkfjhyrOZDLC8cEYkwM92CKeRMy3skjnko= Received: from CH5PR04CA0018.namprd04.prod.outlook.com (2603:10b6:610:1f4::29) by CH3PR12MB9080.namprd12.prod.outlook.com (2603:10b6:610:1a7::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.25; Thu, 12 Sep 2024 07:08:39 +0000 Received: from CH1PEPF0000AD7F.namprd04.prod.outlook.com (2603:10b6:610:1f4:cafe::65) by CH5PR04CA0018.outlook.office365.com (2603:10b6:610:1f4::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.27 via Frontend Transport; Thu, 12 Sep 2024 07:08:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD7F.mail.protection.outlook.com (10.167.244.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:08:38 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:36 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 2/9] misc: amd-sbi: Use regmap subsystem Date: Thu, 12 Sep 2024 07:08:03 +0000 Message-ID: <20240912070810.1644621-3-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7F:EE_|CH3PR12MB9080:EE_ X-MS-Office365-Filtering-Correlation-Id: ed5f08c8-70d0-485e-ad5f-08dcd2f9ba12 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: Avt+Q2U1rvA6PnqSsd1QzUHwuAdNCf3aELyCFj+8bKqNzCAfmkcYmqivmaxwY3SueNLbxujJWizWigCBuj3GL1fHi1y+x5gi7HlCNNCRQ+kAwRwHieRTPWEJug4IwXyFyOsxpi3yLJ700uw9P0u04ABWhQ+Rr00mUEF6j0flobI5IYwVKQVaaokxj6ygQ+wPYFj5ASpAnYNV1nKLxxa1Ys+65KOQnfhQ2fyYrleuaAd6a1f3wgpevg6E2+la8qTDpB5Kt5KX2nxMAud2InSo2Uhu3QrKO0VG2p8b3FwW7DY3WwT0nrdTjByC25eof9ha1cmnsDcZc+HL2dk4rZJl0dbQI6sSyveP+ThECBANM3dNthdV0N0tU9eOWu+S7G1w+RbIcpICuOTSKjFa64PXmVmaxDoAxI11H4bcdt0Ja7pTam+/5uwfQxpUtwatYDRwdqVBSFN3ePmva6ein6X8/Cc/dhm7B9FfzsYxNekdXVVMnaG4wYhhPkstlSSKy+IQ49NCefLPC3mbvY7TjtnOGnkEUp9fy2RyzFvsyCPk68UWY4XHclX5X+Zevw7uns5UEo7jJTvJ5AJEvo/8bgMbRlKuFJYXRnBg0G69f4msz7C9DoSCs6H9HERTrx5w/AIYMEwtNKCX8n0yTSXBzGcaW7GpApXqMyKZ4GxkLZYgcusWAi7tWwyUWneZ3xxZfCVFBpB0PMoHMg2fgNYmR4tt2eyO410l2FbiDbQabNBf2Dzi9/QzG6jKwjc5N3wlN3klyEs+qzwQxo3R0bTRKGUDaJQnkBl3xJN41i86PckTp9xMPqdap9gGAEuf0zNXVudKRsa1I/hwwupmnwDk9fyGOSdmCed73Xj0yOv4TH9N7+Agk/me9E4RV8Fg5L+FiOblWNfVkmt4WWqojqfeKmpKYkzmh42ZAYi3oXH5U34dI358XcYDjcaJkHw+OLpz9unsZY15BI9LKZ9RNg7RTktR1QKraRJw/C/OHs1RygylRN04kNDbck6BDcCX+DzCtJIuC8fxnA1wZBG7RNpCKf96DS5AgqetsdjFSOrtNwdikfWXhK9zBxtNCouXX6D/5/Xf9geoUeo3KaRA+XaL97wkgVTQa760Byqrjf6QO0TNGxhQi5cPzu3tWYNA0+qYPGPp7EtRAcIQjZ29WCd7XzPwbrm0o7dRTaXw+tW4hUCAZfLGmj11ehBXqinpcPRDhO1XpM+JnKGhmFSjg+Pk4VkG9bRZObt5fmwCvfS0EmhjDIz5iGbAqoM+D0DNOe3tBEJCv+bNBfpI8VaFIshe6lHyKfyrDfxp98ehw72SAKhd+V/Ae/TJHBrtdUaeVTQa3dWYhMkh2g/qLEmJhibkXc/wvl8IBWjckWOcYZt98fQdwrKljGoJnRrZjltYGb3+5HZ49SOHSMwKJ9RBAuQElGf/YPF4T+jHvyLr9HTZarBke9Ve6T0W7Wf0G5AGcPJaN9Px X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:08:38.9306 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed5f08c8-70d0-485e-ad5f-08dcd2f9ba12 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9080 - regmap subsystem provides multiple benefits over direct smbus APIs - The susbsytem can be helpful in following cases - Differnet types of bus (i2c/i3c), we have plans to support i3c. - Different Register address size (1byte/2byte) Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v1: - Previously patch 3 - Remove "__packed" from data structure drivers/misc/amd-sbi/rmi-core.c | 29 ++++++++++++----------------- drivers/misc/amd-sbi/rmi-core.h | 3 ++- drivers/misc/amd-sbi/rmi-i2c.c | 25 ++++++++++++++++--------- 3 files changed, 30 insertions(+), 27 deletions(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 5d93fb703fa0..5a0b7912cc4e 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "rmi-core.h" /* Mask for Status Register bit[1] */ @@ -23,6 +24,7 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, struct sbrmi_mailbox_msg *msg) { + unsigned int bytes; int i, ret, retry = 10; int sw_status; u8 byte; @@ -30,14 +32,12 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, mutex_lock(&data->lock); /* Indicate firmware a command is to be serviced */ - ret = i2c_smbus_write_byte_data(data->client, - SBRMI_INBNDMSG7, START_CMD); + ret = regmap_write(data->regmap, SBRMI_INBNDMSG7, START_CMD); if (ret < 0) goto exit_unlock; /* Write the command to SBRMI::InBndMsg_inst0 */ - ret = i2c_smbus_write_byte_data(data->client, - SBRMI_INBNDMSG0, msg->cmd); + ret = regmap_write(data->regmap, SBRMI_INBNDMSG0, msg->cmd); if (ret < 0) goto exit_unlock; @@ -48,8 +48,7 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, */ for (i = 0; i < 4; i++) { byte = (msg->data_in >> i * 8) & 0xff; - ret = i2c_smbus_write_byte_data(data->client, - SBRMI_INBNDMSG1 + i, byte); + ret = regmap_write(data->regmap, SBRMI_INBNDMSG1 + i, byte); if (ret < 0) goto exit_unlock; } @@ -58,8 +57,7 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, * Write 0x01 to SBRMI::SoftwareInterrupt to notify firmware to * perform the requested read or write command */ - ret = i2c_smbus_write_byte_data(data->client, - SBRMI_SW_INTERRUPT, TRIGGER_MAILBOX); + ret = regmap_write(data->regmap, SBRMI_SW_INTERRUPT, TRIGGER_MAILBOX); if (ret < 0) goto exit_unlock; @@ -69,8 +67,7 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, * of the requested command */ do { - sw_status = i2c_smbus_read_byte_data(data->client, - SBRMI_STATUS); + ret = regmap_read(data->regmap, SBRMI_STATUS, &sw_status); if (sw_status < 0) { ret = sw_status; goto exit_unlock; @@ -81,8 +78,6 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, } while (retry--); if (retry < 0) { - dev_err(&data->client->dev, - "Firmware fail to indicate command completion\n"); ret = -EIO; goto exit_unlock; } @@ -94,11 +89,11 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, */ if (msg->read) { for (i = 0; i < 4; i++) { - ret = i2c_smbus_read_byte_data(data->client, - SBRMI_OUTBNDMSG1 + i); + ret = regmap_read(data->regmap, + SBRMI_OUTBNDMSG1 + i, &bytes); if (ret < 0) goto exit_unlock; - msg->data_out |= ret << i * 8; + msg->data_out |= bytes << i * 8; } } @@ -106,8 +101,8 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, * BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the * ALERT to initiator */ - ret = i2c_smbus_write_byte_data(data->client, SBRMI_STATUS, - sw_status | SW_ALERT_MASK); + ret = regmap_write(data->regmap, SBRMI_STATUS, + sw_status | SW_ALERT_MASK); exit_unlock: mutex_unlock(&data->lock); diff --git a/drivers/misc/amd-sbi/rmi-core.h b/drivers/misc/amd-sbi/rmi-core.h index 3d600e450e08..24a6957c8fa0 100644 --- a/drivers/misc/amd-sbi/rmi-core.h +++ b/drivers/misc/amd-sbi/rmi-core.h @@ -9,6 +9,7 @@ #include #include #include +#include /* SB-RMI registers */ enum sbrmi_reg { @@ -47,7 +48,7 @@ enum sbrmi_msg_id { /* Each client has this additional data */ struct sbrmi_data { - struct i2c_client *client; + struct regmap *regmap; struct mutex lock; struct platform_device *pdev; u32 pwr_limit_max; diff --git a/drivers/misc/amd-sbi/rmi-i2c.c b/drivers/misc/amd-sbi/rmi-i2c.c index ae968cf3c29c..c4207672d1e4 100644 --- a/drivers/misc/amd-sbi/rmi-i2c.c +++ b/drivers/misc/amd-sbi/rmi-i2c.c @@ -13,26 +13,26 @@ #include #include #include +#include #include "rmi-core.h" #define SBRMI_CTRL 0x1 -static int sbrmi_enable_alert(struct i2c_client *client) +static int sbrmi_enable_alert(struct sbrmi_data *data) { - int ctrl; + int ctrl, ret; /* * Enable the SB-RMI Software alert status * by writing 0 to bit 4 of Control register(0x1) */ - ctrl = i2c_smbus_read_byte_data(client, SBRMI_CTRL); - if (ctrl < 0) - return ctrl; + ret = regmap_read(data->regmap, SBRMI_CTRL, &ctrl); + if (ret < 0) + return ret; if (ctrl & 0x10) { ctrl &= ~0x10; - return i2c_smbus_write_byte_data(client, - SBRMI_CTRL, ctrl); + return regmap_write(data->regmap, SBRMI_CTRL, ctrl); } return 0; @@ -57,17 +57,24 @@ static int sbrmi_i2c_probe(struct i2c_client *client) { struct device *dev = &client->dev; struct sbrmi_data *data; + struct regmap_config sbrmi_i2c_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + }; int ret; data = devm_kzalloc(dev, sizeof(struct sbrmi_data), GFP_KERNEL); if (!data) return -ENOMEM; - data->client = client; mutex_init(&data->lock); + data->regmap = devm_regmap_init_i2c(client, &sbrmi_i2c_regmap_config); + if (IS_ERR(data->regmap)) + return PTR_ERR(data->regmap); + /* Enable alert for SB-RMI sequence */ - ret = sbrmi_enable_alert(client); + ret = sbrmi_enable_alert(data); if (ret < 0) return ret; From patchwork Thu Sep 12 07:08:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801526 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2071.outbound.protection.outlook.com [40.107.101.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8767518BBA5 for ; Thu, 12 Sep 2024 07:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.101.71 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124929; cv=fail; b=bJaJ+O0Yvw6569U5Y9rE1PVhOjbNzK6E7tJJLH8mP1kllcvsrD9bvyujn01wbvtTQJuWrWMiNOBNbqMNQo6mbIJhDcz1BOIV6r4RpahEQkHcDd+ifbO/IsJQ606b3WSiODIumNGJMFK+GnqiiIIzlhQJykopc0f6phqlrx4rJuw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124929; c=relaxed/simple; bh=CEyEFsA4JutyYbMXXGWQcRKbX3J21uKQVD4d1GuuADo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kiMip+dwK9B9y1sZcYCFCUCobuFjDqD/dxZUsCgC1g9y1t1fHfuUun3pOqjGnv9hlcx1fI7c/TiQAAa74uTHpU9nJ8LS8wgZ3RFbICeNoERmlh6GI8umRnTxQwlrsFscDS0+OK8dbka2MGB5ZFuDW1ZyJbgy8dBCQP7eX0FnEjk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=kSd+MpXy; arc=fail smtp.client-ip=40.107.101.71 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="kSd+MpXy" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=h4l2wrAFTgjVgTfLtPw6Po+rxF3samhiIRJO7BAYfOj5qxoElk+L6k5e/GINzSwABG6jYt67yzCr7Dzi1A4vS4PfYjXmETa6Qk2Dtq37AiZP/dbqNRaeSb1zCTOIZFIsBr0KaWxdKU5lfEoBLPGXm+TYTki7rb4pOnD31oipd3UiVXLP7/cV/KIt5e1IMK+rr8Nj34brWeYh87u9ZAUp/fdTJqlXB/KQZ2Zf4goaj5pp8WlwPvlbLVMSpEFl0cMK9LxLlbrx2SJNX1oBRqmgLKfUN9yN8ZGi05+zwQ0vCPMLiPYAafbrTwm2MLHQsLBQoh36K+J5wvluoibhd2VUvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MuxGRWRjn2x2sYDIJ2UNvnPQFSUjLf6HPQ/i4x12klc=; b=H8J1jbk/WWBrQad9j5QKEfcczjidYvT2O24AI8QqmgFrnPzcrq7tzmzRNwwDgtgJvTOcDTl4Xey8N+ovYLp5jTyXwG0NfL9ezw9PB1CCoLfSGe/3vACUNHvMxdCXXN2byH2YfoxIT+Zd82vzvZYVTHv3OUEK102fwkKmhO4PMxoTkHTiioZ0tzHnbOlj1vHvZxtjAi+CiHTnvMKMw3HDEzC51oHZOi61UxIOZHOT/il5W9crx6pGmeZcVQyx2F/eKIJ8BsXvp9CvIvEzggvZNVTcv0jCNrM99IqRJnN6k/fyuwAHwp7ecUqmXcdyPF4/sGwY+FVU+l4aBq+lW6SNLQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MuxGRWRjn2x2sYDIJ2UNvnPQFSUjLf6HPQ/i4x12klc=; b=kSd+MpXy++7LQnEHBG+vepgED8xujfy/GOAEIjiLoRRfzA38ijRFriE1B18ByHO3M8H/D/mL/KEo3Yr8MIFHIoOwHpbzsqkfmzQhiIk7GILc6SwYNINilSpdhYe5fH0fB+9gHuzjjhxeqeKdbvm/v+plCp/CTtB+Xv+QuRXXMD4= Received: from CH5PR04CA0024.namprd04.prod.outlook.com (2603:10b6:610:1f4::9) by DS0PR12MB6487.namprd12.prod.outlook.com (2603:10b6:8:c4::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7918.27; Thu, 12 Sep 2024 07:08:42 +0000 Received: from CH1PEPF0000AD7F.namprd04.prod.outlook.com (2603:10b6:610:1f4:cafe::98) by CH5PR04CA0024.outlook.office365.com (2603:10b6:610:1f4::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.25 via Frontend Transport; Thu, 12 Sep 2024 07:08:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD7F.mail.protection.outlook.com (10.167.244.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:08:42 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:39 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 3/9] misc: amd-sbi: Optimize the wait condition for mailbox command completion Date: Thu, 12 Sep 2024 07:08:04 +0000 Message-ID: <20240912070810.1644621-4-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7F:EE_|DS0PR12MB6487:EE_ X-MS-Office365-Filtering-Correlation-Id: 20fbc12a-edc2-46d7-6d2d-08dcd2f9bc39 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: JHUInqc2Yn7pZsjfngvtFrM2TAsyXFJPA3es4PAR29Z5ZiJncajq+GxuJgSLaw4CKu8NKn41ch220ddylYtZzu6cgp6LmCv04HxL9+Nh5aLNx1XT+lOgKD2TfmpTJoSml2eKp2frm47CAIQtO+rE5hFwDOYGGr+RqXtbeygtfnnnLkOBcYIYXJAAkpUA4spdypEY6ifYIJ4lq0/1GIbt++ZvDL8s525BhBS0wgYALIVWYAYaeHPHZh6dbA7pKc3F6R/ydKqY4YpID+gpWBtq0GJqS5yvpwihmhvk5tEAKW3LepuRxaNLVDKJMO2zzPumA5I6qdPhZcgQcYVKX9MgEiYFIhoKAWTqiDAEqgCqcnCMJE07ptAXiPA1BAqXN7jBOa3DjY5tdFmobtOHfXY+DDoNmoYyoVwZsPfzHW/KY2Zk7HFR6pvhl/u6rDKYMgotnNjbbsghugdCn40l6unvKtWtzOY37fK6HJ+8fU6FOYDs/UTzgY+GUGU+tWxU+tgKRkVFO2fq88L6Izk8O4teY2iT/wlFCNjNQQabpaDELbBj4XkQmWl4OBFiNlnPFrLVaOcph6PPU0hApxvKuo/SHWG2grebaHrt6ALavSpot3H58ZUsjuk8YdWn7XatiKxmforYX/28CEvQDBL5u7Eb9RPoLFEs625xKK0SVFqFiNw5u7TKoX3YooP+eaxtUnXtuFz67PDLatdOFPwFr6gRvWbPC8fCFXWDXpP0ArUjpusaMjDVinDWkv/O+KyuoczeBe5qx6iREJGG9JaAKmXa/kUb8nyWFSqZNyXjhHp6OHPGYJQy36DJeeUHM3A6EoMTpWDkryQxG3XUxqhIm1Dozx3Ise5IANoiUoE4ifQUEMWSc24vhU05+3wY/nigf0tgoPYsClibM6XCPiJ3rNzRJ6etGZmxs0yhZ251eWT5FbzRMn3O/mRiL+l5uG6O93niyfnWBcYQBKpHYOzdzHDEmDjVYeslmAApQJ7NiNM4doa41SDCQ+wem1HLUG6f7ELG9BRuXLLU5gpQdOI/U7URv8VIzy9R2Nr+Mur6CXIDYEIR+LBSYeCEP2KTo7pyiaXYUpTR0TKFuoUJwhuwjKE9FdvRYw7KEA44D3Z5zSYHaO37nU9nPhOt8kJDrTG7vDJ6s2020LqhcTFjkdARPuLOK5weMZ17iGFAIwALkIwJ1QGB1PsLlmu+vPtUn54kc4JYWXda5bhOCDIvpshU3ATOEedN+2sMQzQOG3RJ+3DxIlA2Q53KcNBLMJqX/om/edmo8Hy4RbT1ng/IW74NOThMse5JtVgqZapsHB/pHlNG8+MdbwEEQY553I5dfJuFmCm+b/0EbGcoDE6JzmeblTcZcYoPNQgeetBaV9Hai2qwCDDERcgwHZ2ckAewltg2RcMARkJ/zqQ3exRgWsvYij64bCagj/2F2ZeKEtDqeaF2LLP1TrOnraFP0b+mDfXioMW/ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:08:42.5400 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20fbc12a-edc2-46d7-6d2d-08dcd2f9bc39 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6487 - optimize the wait condition to indicate command completion by replacing the do while loop with regmap subsystem API regmap_read_poll_timeout() Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v3: - New patch as per suggestion from Arnd drivers/misc/amd-sbi/rmi-core.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 5a0b7912cc4e..57f2915ac8d5 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -25,7 +25,7 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, struct sbrmi_mailbox_msg *msg) { unsigned int bytes; - int i, ret, retry = 10; + int i, ret; int sw_status; u8 byte; @@ -66,21 +66,10 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, * an ALERT (if enabled) to initiator (BMC) to indicate completion * of the requested command */ - do { - ret = regmap_read(data->regmap, SBRMI_STATUS, &sw_status); - if (sw_status < 0) { - ret = sw_status; - goto exit_unlock; - } - if (sw_status & SW_ALERT_MASK) - break; - usleep_range(50, 100); - } while (retry--); - - if (retry < 0) { - ret = -EIO; + ret = regmap_read_poll_timeout(data->regmap, SBRMI_STATUS, sw_status, + sw_status & SW_ALERT_MASK, 500, 2000000); + if (ret) goto exit_unlock; - } /* * For a read operation, the initiator (BMC) reads the firmware From patchwork Thu Sep 12 07:08:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801527 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2065.outbound.protection.outlook.com [40.107.212.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1F29188930 for ; Thu, 12 Sep 2024 07:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.212.65 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124933; cv=fail; b=MS2GT1/EeYriXs2+9QCZjSEsPV1qNEI3q6lLXVULAIjw+zT2T6GtM2MAIX0pU9fl6SXjOBPdpdh/xcyr2BcJtTfBVWzoAqkDXdVr6wAFdNbz5Ek1i4vX1MJ3PL2bBI6JGNG4bJ5VqvyCwjm1BYJZjCrflKrZ1IKFcjpSlQaAxMo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124933; c=relaxed/simple; bh=Q/F4dwtp8Ler1PY3K+KDzq8KKcCncrNRczWRPo6VxW4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lDf8soL4Qz09odOC24Cp5rNoYavo5to8jX4ATNFJtpk4R7pLz4EeaAcyErcWsOTG/9wcZPj5ToN19YS2GvGTvT6rfMbojxbRhyPtz5jB/nZzAxWYdA17esaWFP46sY/FMCFgbcJMyZujsCof6jXT3/+0FfvmpkfWZmHwzEEOGXo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=LOf7B829; arc=fail smtp.client-ip=40.107.212.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="LOf7B829" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pM8Jvc6kcblAFUzUegOLmMX11Q24JbHpngsntfVtxtte3F0S1xzn0A1L2D77cuTnCl+sUqSyVV1l5mwIEnK4R73TpAm9+Sppvnfe1uVm1/HQ3Io6JBXl262MQgQMtZLd27nmkmuyecv3sQ8j7MDSjvAAwDkrEmAPttsmIbcTbTAXkvVYIKfi6U6s92fWRnBpB7O65NHIlZlD8tzfRsIv8/YaTfdh/4iFhTxIoeGBHRyQvVgW3wxWE1RlHconDdvd7yLR4ma/xcanomE1+QLLXwAzTZ3YlCSLK+jMMfcHeolQFcXOg/sYN9eiUblR8HIEYjne1fNWgI5RaysNZthRdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ssqRBtzFff9/wluJDRjUDPmvENR67sBQ+ZrRIwyD8Yk=; b=BgE0ibAP+QHAdJ69ORtfzXJxcugMf99R4/jmpLyO4ZtHqlWWDcf4Rl0+ktrqFG08Ts2wscKhdw62SFlfSMJ6NOvnW3GSpDgnwL9GQvcjqVy3bR8dhaMKDphybCc7vPs7zdUmpYcqOT7gFYh8pRNv+Rm+3pH6lECprYo3YE0l9TQvTrvILl5bNfWOlSAQVlwcwrmVlqT7Uva3k/81h/L0UNJUG/eou3StcVi1B65wfekPqjL8JRgD1y/RocjpeKUWtBC/OCxYdGa01uWjkuEm7OczxRUM/jY9kv3LY0mMabySn3vZ3lvhoVk8ufeNYisT0qGiSii9xRxbR+ig2X/dZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ssqRBtzFff9/wluJDRjUDPmvENR67sBQ+ZrRIwyD8Yk=; b=LOf7B829PFo7KSwnRkFkOVs/QZqfqdXdLs/jv8ZBZKBCAg2/25/IpZcIlCY9UTwtUPmjXJwawJDQv0NQ3yWYwhG4C6u4uQRWf+etoo/7BZfkgOktYmfGghvGEVLFbDxlFTLBXdhURMNTEkCXw2r35cuCXMidmqVflj/9luORTeM= Received: from CH2PR08CA0015.namprd08.prod.outlook.com (2603:10b6:610:5a::25) by DM6PR12MB4403.namprd12.prod.outlook.com (2603:10b6:5:2ab::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.26; Thu, 12 Sep 2024 07:08:47 +0000 Received: from CH1PEPF0000AD7D.namprd04.prod.outlook.com (2603:10b6:610:5a:cafe::f0) by CH2PR08CA0015.outlook.office365.com (2603:10b6:610:5a::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.25 via Frontend Transport; Thu, 12 Sep 2024 07:08:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD7D.mail.protection.outlook.com (10.167.244.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:08:46 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:44 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 4/9] misc: amd-sbi: Add support for AMD_SBI IOCTL Date: Thu, 12 Sep 2024 07:08:05 +0000 Message-ID: <20240912070810.1644621-5-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|DM6PR12MB4403:EE_ X-MS-Office365-Filtering-Correlation-Id: e9715915-4e50-4a07-b720-08dcd2f9bec7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: Cnvx9k8Jw+LYK8RRxOJJUnBfgPDS/p+sIFBGmY4KuqK2R2VANXxtN1UgZL6A9yRmvZD88vwh9Gb2L6mW+zNc29tALw54+r7XUyhdeXDImcucJTlyzK1Sc93yuVihQudKYhvY9/EYnrOS3tMqoZN7A8cdLvVx1/F3eLRDflxXsPj8JdWEh+gCw8EioWkqBWGATZsMQAMKgRcotr21Ip0mWQOVenKZvRB9VS6oK/tSza+Vj85QFYTr47VY4G9g2LDJzAh6bKnZ8PDuVVzT9SmZ58Xl7DmJrJXLEHz2KQ/S+VV3rS8E2FishCxDwD28g1A5y0T6pdXWKYfTqB3veoJoqFUM3X8sUpMAlBMZcAWZvN4xyQTeK/JXMcvyjdhZreUsZEdnseDxEyaCsOVcIFGt/SpS2E+v8XAn4YDmzCTiFf7/mfjS/PDA8XbfTcauSQWhWtkSlRDN1ooEI64+RxOBDvXWiqsgWYdTrAINiylaLy5c6bBu1woJDAQC6u6e0cjI7olv8bB3wSfDF/8G2x4MPeCzzACzcxc7qQlCdSe9jIKgeNtkSh30nOYROtNxDFiVNi6F2IrCItoLxwd8cQYlPNNwUxlLNb0099pCunfa0sqb/cO5xrAdoLJNmg0LCQoiGaBo521hfAtMNIr0o9rQ+YL03zVVAv2tP8gHybvY+55vP146N6oV3RLaiBwVuGlN6veFHy3hsm2qjOCzGwUJctzyCbjf2VCBCh+re5WQ0MpU4D/+A2qQfWqfTI17fcrvZvhkx0t+vP8dRVmzqONQ51KPRUQMg5P45GSZLp4ecWRdee5fr2ok15NhcuN1PYq0ek1Ce7/TZjrk3jK7aTV7E8UB7Xr2xXufXB/FylqfKs1m7bgFEBMbzSed6IJDcJu7dOrwjPqtUa0UWofI0VzmHwjs5q2IxScscYsQ7M9J3/MamWcMo9zfnnF8bSizjqagqNhYDaozDQ1jDVVT/IgCWodoheAygbtPnZea36UkJKqo4EmMN4izMYLQuqh96TbQguWbuRVT5qCaVvvy2lQA0Noxq8vjkXbUa8g4sOctP6kElzwPJW0G5rslg3LdSQxuvgrWrWsQ16WyvRhz6yIy2mD+iF4X6XMy3RyANFHoRwc0EFPqGIHuQfsX3ZYByHDmMWkrC57+5M5MHdxrYgN2BwU0xIp4qLKKj7Mk7Y4kcg661myFgMPFpVVWbniTykiYP7wx02kJkIOAWYqB7sf6c9/ZWgLKHS1p80hEpSQXqI82mnE3MHKI5IJjHIWkgoJRmxhlZ+uGYYcpxR9BPp2REdlVhc3g71D5LL6xsQqc/ivDk/Gh5LeLR0xr1+s3sVhXSVTAxFFTE5r6W9Zv7GDbFJ8GJIvgSbelkNGtvNHu0QShdTqI3CzC0GuQv+6fXxi+RK02HMo8AIhShXXGPHAWw4fYReaMQus7sFXg8Sv+1B0QXhbOwdqWBj/sUSgM91O9 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:08:46.8279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9715915-4e50-4a07-b720-08dcd2f9bec7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4403 The present sbrmi module only support reporting power via hwmon. However, AMD data center range of processors support various system management functionality using custom protocols defined in Advanced Platform Management Link (APML) specification. Register a miscdevice, which creates a device /dev/sbrmiX with an IOCTL interface for the user space to invoke the APML Mailbox protocol, which is already defined in sbrmi_mailbox_xfer(). The APML protocols depend on a set of RMI registers. Having an IOCTL as a single entry point will help in providing synchronization among these protocols as multiple transactions on RMI register set may create race condition. Support for other protocols will be added in subsequent patches. Open-sourced and widely used https://github.com/amd/esmi_oob_library will continue to provide user-space programmable API. Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v3: - Previously patch 3 - Documentation and comments changes Changes since v2: - update the MACROS name as per feedback Changes since v1: - Previously patch 5 - Add IOCTL description in ioctl-number.rst - Split patch as per suggestion. Documentation/misc-devices/index.rst | 1 + .../userspace-api/ioctl/ioctl-number.rst | 2 + drivers/misc/amd-sbi/rmi-core.c | 89 +++++++++++++++++-- drivers/misc/amd-sbi/rmi-core.h | 16 ++-- drivers/misc/amd-sbi/rmi-hwmon.c | 15 ++-- drivers/misc/amd-sbi/rmi-i2c.c | 25 +++++- include/uapi/misc/amd-apml.h | 66 ++++++++++++++ 7 files changed, 186 insertions(+), 28 deletions(-) create mode 100644 include/uapi/misc/amd-apml.h diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst index 8c5b226d8313..081e79415e38 100644 --- a/Documentation/misc-devices/index.rst +++ b/Documentation/misc-devices/index.rst @@ -12,6 +12,7 @@ fit into other categories. :maxdepth: 2 ad525x_dpot + amd-sbi apds990x bh1770glc c2port diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst index e91c0376ee59..5a189300efc5 100644 --- a/Documentation/userspace-api/ioctl/ioctl-number.rst +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst @@ -388,6 +388,8 @@ Code Seq# Include File Comments 0xF8 all arch/x86/include/uapi/asm/amd_hsmp.h AMD HSMP EPYC system management interface driver +0xF9 00-0F uapi/misc/amd-apml.h AMD side band system management interface driver + 0xFD all linux/dm-ioctl.h 0xFE all linux/isst_if.h ==== ===== ======================================================= ================================================================ diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 57f2915ac8d5..92d33d589bdc 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -7,7 +7,10 @@ */ #include #include +#include #include +#include +#include #include #include #include "rmi-core.h" @@ -22,7 +25,7 @@ #define TRIGGER_MAILBOX 0x01 int rmi_mailbox_xfer(struct sbrmi_data *data, - struct sbrmi_mailbox_msg *msg) + struct apml_message *msg) { unsigned int bytes; int i, ret; @@ -46,8 +49,8 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, * Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1] * SBRMI_x3C(MSB):SBRMI_x39(LSB) */ - for (i = 0; i < 4; i++) { - byte = (msg->data_in >> i * 8) & 0xff; + for (i = 0; i < AMD_SBI_MB_DATA_SIZE; i++) { + byte = msg->data_in.reg_in[i]; ret = regmap_write(data->regmap, SBRMI_INBNDMSG1 + i, byte); if (ret < 0) goto exit_unlock; @@ -76,13 +79,13 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, * response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1] * {SBRMI_x34(MSB):SBRMI_x31(LSB)}. */ - if (msg->read) { - for (i = 0; i < 4; i++) { + if (msg->data_in.reg_in[AMD_SBI_RD_FLAG_INDEX]) { + for (i = 0; i < AMD_SBI_MB_DATA_SIZE; i++) { ret = regmap_read(data->regmap, SBRMI_OUTBNDMSG1 + i, &bytes); if (ret < 0) - goto exit_unlock; - msg->data_out |= bytes << i * 8; + break; + msg->data_out.reg_out[i] = bytes; } } @@ -92,8 +95,78 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, */ ret = regmap_write(data->regmap, SBRMI_STATUS, sw_status | SW_ALERT_MASK); - exit_unlock: mutex_unlock(&data->lock); return ret; } + +static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) +{ + int __user *arguser = (int __user *)arg; + struct apml_message msg = { 0 }; + bool read = false; + int ret = -EFAULT; + + struct sbrmi_data *data = container_of(fp->private_data, struct sbrmi_data, + sbrmi_misc_dev); + if (!data) + return -ENODEV; + + /* Copy the structure from user */ + if (copy_struct_from_user(&msg, sizeof(msg), arguser, + sizeof(struct apml_message))) + return ret; + + /* Is this a read/monitor/get request */ + if (msg.data_in.reg_in[AMD_SBI_RD_FLAG_INDEX]) + read = true; + + switch (msg.cmd) { + case 0 ... 0x999: + /* Mailbox protocol */ + ret = rmi_mailbox_xfer(data, &msg); + break; + default: + pr_err("Command:0x%x not recognized\n", msg.cmd); + break; + } + + /* Copy results back to user only for get/monitor commands and firmware failures */ + if ((read && !ret) || ret == -EPROTOTYPE) { + if (copy_to_user(arguser, &msg, sizeof(struct apml_message))) + ret = -EFAULT; + } + return ret; +} + +static const struct file_operations sbrmi_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = sbrmi_ioctl, + .compat_ioctl = sbrmi_ioctl, +}; + +int create_misc_rmi_device(struct sbrmi_data *data, + struct device *dev) +{ + int ret; + + data->sbrmi_misc_dev.name = devm_kasprintf(dev, + GFP_KERNEL, + "sbrmi-%x", + data->dev_static_addr); + data->sbrmi_misc_dev.minor = MISC_DYNAMIC_MINOR; + data->sbrmi_misc_dev.fops = &sbrmi_fops; + data->sbrmi_misc_dev.parent = dev; + data->sbrmi_misc_dev.nodename = devm_kasprintf(dev, + GFP_KERNEL, + "sbrmi-%x", + data->dev_static_addr); + data->sbrmi_misc_dev.mode = 0600; + + ret = misc_register(&data->sbrmi_misc_dev); + if (ret) + return ret; + + dev_info(dev, "register %s device\n", data->sbrmi_misc_dev.name); + return ret; +} diff --git a/drivers/misc/amd-sbi/rmi-core.h b/drivers/misc/amd-sbi/rmi-core.h index 24a6957c8fa0..b728f5582256 100644 --- a/drivers/misc/amd-sbi/rmi-core.h +++ b/drivers/misc/amd-sbi/rmi-core.h @@ -6,10 +6,12 @@ #ifndef _SBRMI_CORE_H_ #define _SBRMI_CORE_H_ +#include #include #include #include #include +#include /* SB-RMI registers */ enum sbrmi_reg { @@ -48,19 +50,15 @@ enum sbrmi_msg_id { /* Each client has this additional data */ struct sbrmi_data { + struct miscdevice sbrmi_misc_dev; struct regmap *regmap; + /* Mutex locking */ struct mutex lock; - struct platform_device *pdev; u32 pwr_limit_max; + u8 dev_static_addr; }; -struct sbrmi_mailbox_msg { - u8 cmd; - bool read; - u32 data_in; - u32 data_out; -}; - -int rmi_mailbox_xfer(struct sbrmi_data *data, struct sbrmi_mailbox_msg *msg); +int rmi_mailbox_xfer(struct sbrmi_data *data, struct apml_message *msg); int create_hwmon_sensor_device(struct device *dev, struct sbrmi_data *data); +int create_misc_rmi_device(struct sbrmi_data *data, struct device *dev); #endif /*_SBRMI_CORE_H_*/ diff --git a/drivers/misc/amd-sbi/rmi-hwmon.c b/drivers/misc/amd-sbi/rmi-hwmon.c index 36913f105eef..5f1634a17579 100644 --- a/drivers/misc/amd-sbi/rmi-hwmon.c +++ b/drivers/misc/amd-sbi/rmi-hwmon.c @@ -6,6 +6,7 @@ */ #include #include +#include #include "rmi-core.h" /* Do not allow setting negative power limit */ @@ -15,7 +16,7 @@ static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { struct sbrmi_data *data = dev_get_drvdata(dev); - struct sbrmi_mailbox_msg msg = { 0 }; + struct apml_message msg = { 0 }; int ret; if (!data) @@ -24,7 +25,7 @@ static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, if (type != hwmon_power) return -EINVAL; - msg.read = true; + msg.data_in.reg_in[AMD_SBI_RD_FLAG_INDEX] = 1; switch (attr) { case hwmon_power_input: msg.cmd = SBRMI_READ_PKG_PWR_CONSUMPTION; @@ -35,7 +36,7 @@ static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, ret = rmi_mailbox_xfer(data, &msg); break; case hwmon_power_cap_max: - msg.data_out = data->pwr_limit_max; + msg.data_out.mb_out[AMD_SBI_RD_WR_DATA_INDEX] = data->pwr_limit_max; ret = 0; break; default: @@ -44,7 +45,7 @@ static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, if (ret < 0) return ret; /* hwmon power attributes are in microWatt */ - *val = (long)msg.data_out * 1000; + *val = (long)msg.data_out.mb_out[AMD_SBI_RD_WR_DATA_INDEX] * 1000; return ret; } @@ -52,7 +53,7 @@ static int sbrmi_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long val) { struct sbrmi_data *data = dev_get_drvdata(dev); - struct sbrmi_mailbox_msg msg = { 0 }; + struct apml_message msg = { 0 }; if (!data) return -ENODEV; @@ -68,8 +69,8 @@ static int sbrmi_write(struct device *dev, enum hwmon_sensor_types type, val = clamp_val(val, SBRMI_PWR_MIN, data->pwr_limit_max); msg.cmd = SBRMI_WRITE_PKG_PWR_LIMIT; - msg.data_in = val; - msg.read = false; + msg.data_in.mb_in[AMD_SBI_RD_WR_DATA_INDEX] = val; + msg.data_in.reg_in[AMD_SBI_RD_FLAG_INDEX] = 0; return rmi_mailbox_xfer(data, &msg); } diff --git a/drivers/misc/amd-sbi/rmi-i2c.c b/drivers/misc/amd-sbi/rmi-i2c.c index c4207672d1e4..0e80acc61d6e 100644 --- a/drivers/misc/amd-sbi/rmi-i2c.c +++ b/drivers/misc/amd-sbi/rmi-i2c.c @@ -40,15 +40,15 @@ static int sbrmi_enable_alert(struct sbrmi_data *data) static int sbrmi_get_max_pwr_limit(struct sbrmi_data *data) { - struct sbrmi_mailbox_msg msg = { 0 }; + struct apml_message msg = { 0 }; int ret; msg.cmd = SBRMI_READ_PKG_MAX_PWR_LIMIT; - msg.read = true; + msg.data_in.reg_in[AMD_SBI_RD_FLAG_INDEX] = 1; ret = rmi_mailbox_xfer(data, &msg); if (ret < 0) return ret; - data->pwr_limit_max = msg.data_out; + data->pwr_limit_max = msg.data_out.mb_out[AMD_SBI_RD_WR_DATA_INDEX]; return ret; } @@ -83,8 +83,24 @@ static int sbrmi_i2c_probe(struct i2c_client *client) if (ret < 0) return ret; + data->dev_static_addr = client->addr; dev_set_drvdata(dev, data); - return create_hwmon_sensor_device(dev, data); + ret = create_hwmon_sensor_device(dev, data); + if (ret < 0) + return ret; + return create_misc_rmi_device(data, dev); +} + +static void sbrmi_i2c_remove(struct i2c_client *client) +{ + struct sbrmi_data *data = dev_get_drvdata(&client->dev); + + misc_deregister(&data->sbrmi_misc_dev); + /* Assign fops and parent of misc dev to NULL */ + data->sbrmi_misc_dev.fops = NULL; + data->sbrmi_misc_dev.parent = NULL; + dev_info(&client->dev, "Removed sbrmi-i2c driver\n"); + return; } static const struct i2c_device_id sbrmi_id[] = { @@ -107,6 +123,7 @@ static struct i2c_driver sbrmi_driver = { .of_match_table = of_match_ptr(sbrmi_of_match), }, .probe = sbrmi_i2c_probe, + .remove = sbrmi_i2c_remove, .id_table = sbrmi_id, }; diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h new file mode 100644 index 000000000000..dc926327629d --- /dev/null +++ b/include/uapi/misc/amd-apml.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright (C) 2021-2024 Advanced Micro Devices, Inc. + */ +#ifndef _AMD_APML_H_ +#define _AMD_APML_H_ + +#include + +/* These are byte indexes into data_in and data_out arrays */ +#define AMD_SBI_RD_WR_DATA_INDEX 0 +#define AMD_SBI_REG_OFF_INDEX 0 +#define AMD_SBI_REG_VAL_INDEX 4 +#define AMD_SBI_RD_FLAG_INDEX 7 + +#define AMD_SBI_MB_DATA_SIZE 4 + +struct apml_message { + /* message ids: + * Mailbox Messages: 0x0 ... 0x999 + */ + __u32 cmd; + + /* + * 8 bit data for reg read, + * 32 bit data in case of mailbox, + */ + union { + __u32 mb_out[2]; + __u8 reg_out[8]; + } data_out; + + /* + * [0]...[3] mailbox 32bit input + * [7] read/write functionality + */ + union { + __u32 mb_in[2]; + __u8 reg_in[8]; + } data_in; +} __attribute__((packed)); + +/** + * AMD sideband interface base IOCTL + */ +#define SB_BASE_IOCTL_NR 0xF9 + +/** + * DOC: SBRMI_IOCTL_CMD + * + * @Parameters + * + * @struct apml_message * + * Pointer to the &struct apml_message that will contain the protocol + * information + * + * @Description + * IOCTL command for APML messages using generic _IOWR + * The IOCTL provides userspace access to AMD sideband protocols + * The APML RMI module checks whether the cmd is + * - Mailbox message read/write(0x0~0x999) + * - returning "-EFAULT" if none of the above + */ +#define SBRMI_IOCTL_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_message) + +#endif /*_AMD_APML_H_*/ From patchwork Thu Sep 12 07:08:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801528 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2041.outbound.protection.outlook.com [40.107.93.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3AC6189BA5 for ; Thu, 12 Sep 2024 07:08:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.41 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124936; cv=fail; b=Q0SygBfplh4qnJ3HURyFPOLuE1BOlwO+4ir69+rVD8ZY4XP6T5GsqXTDJB3EiW4UafXf/JuqyGeiKRsYo3ZE0y8tba5KBBdugXT7/uZWL3mOXrmXtv+soS0cMcIvTQM6AUPtOH26ZmDUa8MgngWLddPa8fXwSPBe4B1uQj0FZEk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124936; c=relaxed/simple; bh=hwYNauNFnDp6G1I6Dns78SuJQW1SuLiCYEXnrqX4vsg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=m8xNN9LX+55gdu+9yPxASiaE5yRkAIVQX1mHxzbF2czXC1dCFfYAvwGqnWHaUn2nHikx7XLQxSn9FVV5X4jAEdWSs4KhYKDP95rcb7TXqoz16yXD+uYFsgVedakzR5ftMKqOKXtIGJqBLXZ7GJjqN7YuDMeNqGhX7P+xgw1wEiY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=2KMp8FHI; arc=fail smtp.client-ip=40.107.93.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="2KMp8FHI" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Fx+SqhP4CEWrYzJvNY5b6bko3WXIESFJ3VtGpGNHCzdx6qIF9nwEnfPqXkDhpxKOQQNZO5SF9ry3AJbr0yD32oZyH1R7mw9O+uTEU4VSBJ6/OxnyXKxddibekMBsUmUfyv4bxvNWDbyENGFchf3wOLqS59hZKOyHO9gGCxgAJjXshMmnatQDkJrcIfPmY3YIXkPHGnF4OKN+rftPO53xa3Qv2ptjzE6S+hEn0ZSvkclzrJwSfpzoa3tMpLPVZGohgHOXLi/AqjAjKTS2kkepNZhD8uMKPYRp11KZ+k9y2Fco8Nbnhl+bZlQ/xs8/4ja5pCeBHajL7WRCKVmkYj9vpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Dv/2ldloZTlwiaNq5oOi8yzMUVWbxfuVVRPydOLFRHA=; b=J105dXO2Rz9Mh3AdYAR3ApD9+c7njJ2zdk8Qo8ZEeELLsH0XU9p8ZewvIhjpO6xHTEa9VmOFrSrsiG3nWm113JIe4omgRbjoHyo5yhYcjFTAQFI2kK5M5S/0jkf5iRz68vYR5iGBLTJylvGm/UFz+/lb4wUTdk5+bbE1OfMG6vOR61NwjuX1YHMQPgddRprE8zBNfem+G6rxYegqWJPBAxlbGM6E8KScfMwGcV+ZDINykSHnlOBgFNKsodJXG6+OD60le7twOQzr4ikArwknphaSjB22mmlePYg2z6B9/3omvQ5Om2b1UVufb0tTtb9bk1VutwGqleE/hWCkdySjsw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Dv/2ldloZTlwiaNq5oOi8yzMUVWbxfuVVRPydOLFRHA=; b=2KMp8FHIML5RbXp4dBU7US8dgeSJheIvES7VQBhB0PuBp5h8ujxLgtO8beHimjB8qs4MIBVv9odh4+TIBwzbKzWLgGgcjPW6x1TmHJygNJ24uJwb56lb1bGW80riBlySvNFV21wtqLFiylE+qbFVb9WnaAwdr6ma5ry8uCuW5Io= Received: from CH5PR04CA0014.namprd04.prod.outlook.com (2603:10b6:610:1f4::26) by LV2PR12MB5727.namprd12.prod.outlook.com (2603:10b6:408:17d::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.24; Thu, 12 Sep 2024 07:08:50 +0000 Received: from CH1PEPF0000AD7F.namprd04.prod.outlook.com (2603:10b6:610:1f4::4) by CH5PR04CA0014.outlook.office365.com (2603:10b6:610:1f4::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.26 via Frontend Transport; Thu, 12 Sep 2024 07:08:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD7F.mail.protection.outlook.com (10.167.244.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:08:50 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:47 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 5/9] misc: amd-sbi: Add support for mailbox error codes Date: Thu, 12 Sep 2024 07:08:06 +0000 Message-ID: <20240912070810.1644621-6-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7F:EE_|LV2PR12MB5727:EE_ X-MS-Office365-Filtering-Correlation-Id: 260cef74-38ef-447a-710e-08dcd2f9c10c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: CiannKmomgPGY960WAUw1jsIyP5UvREGxX+FliYBiaDmV3LQxPB3lWJKRrShjSPOlZXr7n9AV5nIQK8jY20ARuUypBsxfQoBLYrq1glq9L9BpsHZFwcBHdY1IMqysj/Q3pT0xixFPuzL7ONGCQzRRDDVrRRRz4knvBp70EqAZBJ5BkpoOwreUrm+nTbJL7TPqu45oCmj68tSNq9TRqKj2rfIUif1CRd7KTcRhrFZuD+jWktUCzidIupFveYTf0HexV3GyiDoasBf2DkpKl8pqxXu6Y2pMe6PMlG8xhQ3Mc8wIgRtGAJcrds9ky3tn2Y6PfWtd95BIKh4wJcSAkcr2XKjMpog4zeHBZtSn5AzVorrlf0ntUY8qEh44WSpYoPI6eNTSulS/IkHx2b/sRAM4knXHUIYFCj6b8Lp+f2InR4AJ3jqeli+Rg70VbvPM91iMDvZ0r5cEUZfNEbkDOJscG9wMVuzqV9o0VBuZ9mhDGzpF9MkIP/1e4XvQvSIO02UPJyRWa7o0MgRRoUh3Ypj8Oz4RYPB2NqNilX2f45NHSd+TkgwSbtGFy7SkX9XOmk6S1TBXDcWNmyIGhiwxixP1BDHw5vuIaanrgDqhByXsjgvrYdjsVZBwrAh5OyCyEHzRxlFZPr1uXDgJk3rHfZddtjyRhPZzUQVwk8NNA4uB3VqjgURlzHfWY5ZCxx6cReaIiWijIZcSg8/R9RPZnuYVMrrhZgrrhptVKyBRGlnAgoEdxW73DScoD0i71V4VrT4zhe+9w9g5S/ciTWl+sVvedvJOB3xJB6oSrijLsCb4f78+HtjrFfpLH+KKOwTHzQPOFrVZpOQtpcF8JW9RLsNH+FGAVN3f5zYv3rcPqlYT1t6XZ8rL1RjVG7IFqK4WgzAcNjKLfkIBeeWBMBaqr+2ngBgvMMZmGlO82VtFcxWSrjrh8xKvyJqiGVLwJFzDSIm2eMlT6HqBYeObwYO3a8krof6f7pwHI0bZK4BEh2TjmgvpnIV35f44xS32WJpAWGXBG3DVF1j6MAEoVzjmJWa2+J3xw0Jp9ctTVEnZ4jND5ApyinLd7JjL1Qh6EojiRsHtvUM7jL+E+g3F8O9euZ6uXxA7xdbOwfNTNCez0Io7jNl7pYFE4oSlB/hsjGisqDO1UIuxDj6lN/OUekQO0N7CensR8TMpKCgW6SepQN6kn+Wo7VAJsSP1azberlQM5l1XMI1HUfG/yh8LrrhslymRLgl/3FB5aN6sbl6H1vpsTMHLD7Cr2J9rJCvK8sYDy7alN4PuyNOQyTVGD11J59K19wwGANL/67U9+/2ea/cQyGfG6BAezJQqNWkLyawFEjvbg1sWu9PPkzWixT6eElTWy8b09tuVPk1rx+2WpdE43TS7slTSPQ/kdd6irBgtQD0CSeEUGJKcUu3l0lacwBN9UBD4OnCNKE1xr+9XuSqjuJua2GfcQTjb+vvzKpaJ2YV X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:08:50.6338 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 260cef74-38ef-447a-710e-08dcd2f9c10c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5727 APML mailbox protocol returns additional error codes written by SMU firmware in the out-bound register 0x37. These errors include, invalid core, message not supported over platform and others. This additional error codes can be used to provide more details to userspace. Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v3: - update ioctl comment description Changes since v1: - bifurcated from previous patch 5 drivers/misc/amd-sbi/rmi-core.c | 12 +++++++++++- include/uapi/misc/amd-apml.h | 5 +++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 92d33d589bdc..b4f292303ed4 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -27,13 +27,15 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, struct apml_message *msg) { - unsigned int bytes; + unsigned int bytes, ec; int i, ret; int sw_status; u8 byte; mutex_lock(&data->lock); + msg->fw_ret_code = 0; + /* Indicate firmware a command is to be serviced */ ret = regmap_write(data->regmap, SBRMI_INBNDMSG7, START_CMD); if (ret < 0) @@ -74,6 +76,9 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, if (ret) goto exit_unlock; + ret = regmap_read(data->regmap, SBRMI_OUTBNDMSG7, &ec); + if (ret || ec) + goto exit_clear_alert; /* * For a read operation, the initiator (BMC) reads the firmware * response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1] @@ -89,12 +94,17 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, } } +exit_clear_alert: /* * BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the * ALERT to initiator */ ret = regmap_write(data->regmap, SBRMI_STATUS, sw_status | SW_ALERT_MASK); + if (ec) { + ret = -EPROTOTYPE; + msg->fw_ret_code = ec; + } exit_unlock: mutex_unlock(&data->lock); return ret; diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h index dc926327629d..4207aa08b660 100644 --- a/include/uapi/misc/amd-apml.h +++ b/include/uapi/misc/amd-apml.h @@ -38,6 +38,10 @@ struct apml_message { __u32 mb_in[2]; __u8 reg_in[8]; } data_in; + /* + * Error code is returned in case of soft mailbox + */ + __u32 fw_ret_code; } __attribute__((packed)); /** @@ -60,6 +64,7 @@ struct apml_message { * The APML RMI module checks whether the cmd is * - Mailbox message read/write(0x0~0x999) * - returning "-EFAULT" if none of the above + * "-EPROTOTYPE" error is returned to provide additional error details */ #define SBRMI_IOCTL_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_message) From patchwork Thu Sep 12 07:08:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801529 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2065.outbound.protection.outlook.com [40.107.94.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32B5A188930 for ; Thu, 12 Sep 2024 07:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.65 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124940; cv=fail; b=nu5awX1U9eGwNWw+mbWNb3BpEfGVSPJKSbEgzFPK31Y6tcjCoevelNYD2qJh8nawY/wT3ny7PC7d6wPcHLsmYs1bBGW4S2DmafNx15iALXVoDX78n37KFJ8p12TH0H23qrJmqyWekce9rddtIM/tLU6FgQNv5YyS8WBF6lB/zN8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124940; c=relaxed/simple; bh=WOS1mX6OcpJSYslpFhwNma38/rUfxL7bVHNc39zKPqI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Mlv3Ur9QQ87BoZ7dTyGvHI6EcogoVgwj9AmosAJMa3HzInD0ZotR8GIvUslhyMBrvLug3zoPJt39Jacqg1kepcJiE8iRWvSoEPHUw8mgQslyYmdDAfVWZo/4q+XJhlv4drKJXQw/3y3lsqRpHrUdi+JiRt+DufbQkt5UXjZMsIg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=TfwaRDUb; arc=fail smtp.client-ip=40.107.94.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="TfwaRDUb" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=hUFrzrbUdulanxGtovBdgZEYmMATkIXCkeX7iYZJDZDrlys/pF9yhUyFVRdbMUc6kcgPBG5ltBabMjgCIHQogapVEHULtOjq+ucE6p19W1kb3QbmXy//4zOk2UtqXORf01hpGLLIp4XSuvTLUd32lDJlTvpHPD4ER8/EM+SxmMnfhnDeGScF6jXs3FFM/n53STgFz1giDwuzxzG3gUh3tf9t3mk1HUHcp1INdtTxlh1FmPOhNoRuzF6PZgGhjyEwnTaHNMtSVRP/W/s6W/bjP3o4s9NdtLnv0lRMc0HZoO2RayHHpUIzY2xWEDv4NR+GV6uQ3q98spO6FbRVKhP34A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pG/W3JpCrw4yO6tuAim/nlTDkb63CizuW51UJ1jp8E4=; b=UsYwN+6+oSvECFw8OMVCJ03VWcONaboxkWS5nBo5UsggnjZ+ge2IWJuY8iV1ULHXsbvuIYo+3mP101Y8EmZ6vuLUS0CWyui+g4k85VT9lyZmBYHMCXXeCUWKNkP16cMX5U+IGekdyL3BenrEmTDwdW8qy0+Iw8Q0IkflFYdQLxNc0Gztm/COtfGUDnwv6b5lkZuogjQIjgk+sXCRfyRkh3WybP6nfqDadWCcN3i7PmYKwckxXOro8VvtUSsW5QO3QwhAA8mgRjAZCpAjs7E27LwSDrROszMyk0FM3ar/oFFghAGhYzyeMWNC9Kwgpe/EHjw6BujKPmtLZtcbhTNC6w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pG/W3JpCrw4yO6tuAim/nlTDkb63CizuW51UJ1jp8E4=; b=TfwaRDUby/Tt/5S8TaNJdDGXh6KT6PTvRCfRwHjQOmGRswZuEeeaZyOpqpuFdyEhQhKA8nDeXd8wlAfiGtLFy1DY+qDF0YA3xFS7cDIW0VUsSXGPDCX6u14voNPCgz2czxBXtuZDzssyOa9MBL3frr8b1u79eeMoWA0NTbDQ9IE= Received: from CH5P223CA0023.NAMP223.PROD.OUTLOOK.COM (2603:10b6:610:1f3::28) by CH3PR12MB7617.namprd12.prod.outlook.com (2603:10b6:610:140::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7962.17; Thu, 12 Sep 2024 07:08:55 +0000 Received: from CH1PEPF0000AD80.namprd04.prod.outlook.com (2603:10b6:610:1f3:cafe::50) by CH5P223CA0023.outlook.office365.com (2603:10b6:610:1f3::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.25 via Frontend Transport; Thu, 12 Sep 2024 07:08:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD80.mail.protection.outlook.com (10.167.244.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:08:55 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:52 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 6/9] misc: amd-sbi: Add support for CPUID protocol Date: Thu, 12 Sep 2024 07:08:07 +0000 Message-ID: <20240912070810.1644621-7-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD80:EE_|CH3PR12MB7617:EE_ X-MS-Office365-Filtering-Correlation-Id: 99be545c-4a43-4c97-05a2-08dcd2f9c3a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: PLHOIgi4fc6l34QhzfIP2uzskt3Fr0eHtajbS3ktdNqsngjhvh1Se3vb9vm08eW6d1zCLK68JMBCeGAyr3/ocV5BFOGO9bKCGoz3oZr1FD/OASy0bhC7CQ97Q50zIrrJSO0cAK9Y/ZTJPk0gp3mq91o3N696dvel8HDaaZFnvqou9BxdD92re/APQ3eS+BlogRsvWwrlQ+iZCylP27E/X429J5MrfQ1ucaTbUfOame7PIOXHgW4CkzeWKR2GMM/wfXGK5AQZ8KViiEbn0MxMUAwUW60fBSQ8qm4RcNs+D3pIYg+Fb00P06Wn0UEBi+Fj1khw+BGmQ1RlNlGh+XcjQiNbO3ATSWV7n1VduBY/Fm6dEB9FYJ0GPHTeXyDYV0IP+HnJ8WpqxKnMRcjo0os3SssUAKbxagfWQLB1RqqtnvsPlh9cJF5IkFAXYuw2Ltm5O0OWH2Pf8LGayMnlSNnVJW88A9sTqqUpin14u19sWVG0tZPKMLVjQWZ6r4NedOGoEvN8YL3v8SlFQzftWgKTo6h8Sx7/mBzdsTobLzH9yepEaOHoBTIOnVK7pwczzz1LCwyvNDNDSxXGe5VBUuEkheY56k0vAwNxXsEl/H5zxrbOws1sUJ02g1/z+20UYk22ttmspV+NSWmCi8AAhsQNDitrCpZbqKabNpCQ0yt9/cfZ2U0iXghzMnzqblk5fCh+bMAvIRa0tCRHr1H8tPDa0KkfUpG8ZVCPHBLCU917NeReqH0fUQgl0SL8lNwDLlSBXOyRMm+SpjxiKvHNN82+1qHwxjz3onkF2agjA3RKgFbCh5L+afvEh8oAPcCgfTCE30wxuiyKxNsUFCSGuIrhu5vG2IRVTCai6tpQgG97vOIyoM66xZDaIlKuaOwdXayq1j7efqm5GNNMwiYH9rEk1zUdFos/cJ7QO/1n+7UyvwURwZCbt7i8HTk+xKzDNyTU7wE6kJRoTYr2FcH19uun6CfDCGzt2fgm7LZV5v5W+xHIH2Lxhw3iWXO42hOPP7g/Cb0uHyZbKykrEsc+MnqmN3deURyDD80tu3O2kaYZ2ATwfPyXbRbzQX0BgQM87IrtjIt20jR/oiEsTDcCbkpKJ9QHxsJ9zy8deOIzh1JA9wNB+JgbLdKvhg31BnwiO6frmpM7hIAEI+oH7LDCDKX1ovVJuuO5MjhDnjwdBGi+Tbsa1xBP9dNaI5Jr/Xwc6Oc9XIVF7AMMpkKnjJAwZ/jKBazHgvfGiotMAOHbSgUr7mEGIOesIN4ALGA01FwZOQuyRP1nJt2yJvduXqdp8ed1kendDofCFZAEM/6W6lMRTZpqwbx67ytcxEucboNpSiD/ywTVI7xDxYa+nh1Kkp4F9q59R9V8zly1zSQInbArWT7J4+OpFZmphCEYqsdMQVZsFZwK//bQDTcXCYnSBXMSV8BPsUTxaNoyjZ5XbEqmMu1rSWHFfBN48kkkd8Mmr3HN X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:08:55.0179 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99be545c-4a43-4c97-05a2-08dcd2f9c3a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD80.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7617 - AMD provides custom protocol to read Processor feature capabilities and configuration information through side band. The information is accessed by providing CPUID Function, extended function and thread ID to the protocol. Undefined function returns 0. Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v3: - Address review comments: - update the #define to inline function - pack the union inside the structure Changes since v2: - update the MACROS name as per feedback Changes since v1: - bifurcated from previous patch 5 drivers/misc/amd-sbi/rmi-core.c | 148 ++++++++++++++++++++++++++++++++ drivers/misc/amd-sbi/rmi-core.h | 5 +- include/uapi/misc/amd-apml.h | 16 ++++ 3 files changed, 168 insertions(+), 1 deletion(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index b4f292303ed4..3efb11ac2910 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -17,6 +17,8 @@ /* Mask for Status Register bit[1] */ #define SW_ALERT_MASK 0x2 +/* Mask to check H/W Alert status bit */ +#define HW_ALERT_MASK 0x80 /* Do not allow setting negative power limit */ #define SBRMI_PWR_MIN 0 @@ -24,6 +26,149 @@ #define START_CMD 0x80 #define TRIGGER_MAILBOX 0x01 +/* Default message lengths as per APML command protocol */ +/* CPUID */ +#define CPUID_RD_DATA_LEN 0x8 +#define CPUID_WR_DATA_LEN 0x8 +#define CPUID_RD_REG_LEN 0xa +#define CPUID_WR_REG_LEN 0x9 + +/* CPUID MSR Command Ids */ +#define CPUID_MCA_CMD 0x73 +#define RD_CPUID_CMD 0x91 + +/* input for bulk write to CPUID protocol */ +struct cpu_msr_indata { + u8 wr_len; /* const value */ + u8 rd_len; /* const value */ + u8 proto_cmd; /* const value */ + u8 thread; /* thread number */ + union { + u8 reg_offset[4]; /* input value */ + u32 value; + } __packed; + u8 ext; /* extended function */ +}; + +/* output for bulk read from CPUID protocol */ +struct cpu_msr_outdata { + u8 num_bytes; /* number of bytes return */ + u8 status; /* Protocol status code */ + union { + u64 value; + u8 reg_data[8]; + } __packed; +}; + +static inline void prepare_cpuid_input_message(struct cpu_msr_indata *input, + u8 thread_id, u32 func, + u8 ext_func) +{ + input->rd_len = CPUID_RD_DATA_LEN; + input->wr_len = CPUID_WR_DATA_LEN; + input->proto_cmd = RD_CPUID_CMD; + input->thread = thread_id << 1; + input->value = func; + input->ext = ext_func; +} + +static int sbrmi_get_rev(struct sbrmi_data *data) +{ + struct apml_message msg = { 0 }; + int ret; + + msg.data_in.reg_in[AMD_SBI_REG_OFF_INDEX] = SBRMI_REV; + msg.data_in.reg_in[AMD_SBI_RD_FLAG_INDEX] = 1; + ret = regmap_read(data->regmap, + msg.data_in.reg_in[AMD_SBI_REG_OFF_INDEX], + &msg.data_out.mb_out[AMD_SBI_RD_WR_DATA_INDEX]); + if (ret < 0) + return ret; + + data->rev = msg.data_out.reg_out[AMD_SBI_RD_WR_DATA_INDEX]; + return 0; +} + +/* Read CPUID function protocol */ +static int rmi_cpuid_read(struct sbrmi_data *data, + struct apml_message *msg) +{ + struct cpu_msr_indata input = {0}; + struct cpu_msr_outdata output = {0}; + int val = 0; + int ret, hw_status; + u16 thread; + + mutex_lock(&data->lock); + /* cache the rev value to identify if protocol is supported or not */ + if (!data->rev) { + ret = sbrmi_get_rev(data); + if (ret < 0) + goto exit_unlock; + } + /* CPUID protocol for REV 0x10 is not supported*/ + if (data->rev == 0x10) { + ret = -EOPNOTSUPP; + goto exit_unlock; + } + + thread = msg->data_in.reg_in[AMD_SBI_THREAD_LOW_INDEX] | + msg->data_in.reg_in[AMD_SBI_THREAD_HI_INDEX] << 8; + + /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */ + if (thread > 127) { + thread -= 128; + val = 1; + } + ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val); + if (ret < 0) + goto exit_unlock; + + prepare_cpuid_input_message(&input, thread, + msg->data_in.mb_in[AMD_SBI_RD_WR_DATA_INDEX], + msg->data_in.reg_in[AMD_SBI_EXT_FUNC_INDEX]); + + ret = regmap_bulk_write(data->regmap, CPUID_MCA_CMD, + &input, CPUID_WR_REG_LEN); + if (ret < 0) + goto exit_unlock; + + /* + * For RMI Rev 0x20, new h/w status bit is introduced. which is used + * by firmware to indicate completion of commands (0x71, 0x72, 0x73). + * wait for the status bit to be set by the hardware before + * reading the data out. + */ + ret = regmap_read_poll_timeout(data->regmap, SBRMI_STATUS, hw_status, + hw_status & HW_ALERT_MASK, 500, 2000000); + if (ret) + goto exit_unlock; + + ret = regmap_bulk_read(data->regmap, CPUID_MCA_CMD, + &output, CPUID_RD_REG_LEN); + if (ret < 0) + goto exit_unlock; + + ret = regmap_write(data->regmap, SBRMI_STATUS, + HW_ALERT_MASK); + if (ret < 0) + goto exit_unlock; + + if (output.num_bytes != CPUID_RD_REG_LEN - 1) { + ret = -EMSGSIZE; + goto exit_unlock; + } + if (output.status) { + ret = -EPROTOTYPE; + msg->fw_ret_code = output.status; + goto exit_unlock; + } + msg->data_out.cpu_msr_out = output.value; +exit_unlock: + mutex_unlock(&data->lock); + return ret; +} + int rmi_mailbox_xfer(struct sbrmi_data *data, struct apml_message *msg) { @@ -136,6 +281,9 @@ static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) /* Mailbox protocol */ ret = rmi_mailbox_xfer(data, &msg); break; + case APML_CPUID: + ret = rmi_cpuid_read(data, &msg); + break; default: pr_err("Command:0x%x not recognized\n", msg.cmd); break; diff --git a/drivers/misc/amd-sbi/rmi-core.h b/drivers/misc/amd-sbi/rmi-core.h index b728f5582256..529c8284dec4 100644 --- a/drivers/misc/amd-sbi/rmi-core.h +++ b/drivers/misc/amd-sbi/rmi-core.h @@ -15,7 +15,8 @@ /* SB-RMI registers */ enum sbrmi_reg { - SBRMI_CTRL = 0x01, + SBRMI_REV = 0x00, + SBRMI_CTRL, SBRMI_STATUS, SBRMI_OUTBNDMSG0 = 0x30, SBRMI_OUTBNDMSG1, @@ -34,6 +35,7 @@ enum sbrmi_reg { SBRMI_INBNDMSG6, SBRMI_INBNDMSG7, SBRMI_SW_INTERRUPT, + SBRMI_THREAD128CS = 0x4b, }; /* @@ -56,6 +58,7 @@ struct sbrmi_data { struct mutex lock; u32 pwr_limit_max; u8 dev_static_addr; + u8 rev; }; int rmi_mailbox_xfer(struct sbrmi_data *data, struct apml_message *msg); diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h index 4207aa08b660..293532500450 100644 --- a/include/uapi/misc/amd-apml.h +++ b/include/uapi/misc/amd-apml.h @@ -7,38 +7,53 @@ #include +/* command ID to identify CPUID protocol */ +#define APML_CPUID 0x1000 /* These are byte indexes into data_in and data_out arrays */ #define AMD_SBI_RD_WR_DATA_INDEX 0 #define AMD_SBI_REG_OFF_INDEX 0 #define AMD_SBI_REG_VAL_INDEX 4 #define AMD_SBI_RD_FLAG_INDEX 7 +#define AMD_SBI_THREAD_LOW_INDEX 4 +#define AMD_SBI_THREAD_HI_INDEX 5 +#define AMD_SBI_EXT_FUNC_INDEX 6 #define AMD_SBI_MB_DATA_SIZE 4 struct apml_message { /* message ids: * Mailbox Messages: 0x0 ... 0x999 + * APML_CPUID: 0x1000 */ __u32 cmd; /* * 8 bit data for reg read, * 32 bit data in case of mailbox, + * up to 64 bit in case of cpuid */ union { + __u64 cpu_msr_out; __u32 mb_out[2]; __u8 reg_out[8]; } data_out; /* * [0]...[3] mailbox 32bit input + * cpuid, + * [4][5] cpuid: thread + * [6] cpuid: ext function & read eax/ebx or ecx/edx + * [7:0] -> bits [7:4] -> ext function & + * bit [0] read eax/ebx or ecx/edx * [7] read/write functionality */ union { + __u64 cpu_msr_in; __u32 mb_in[2]; __u8 reg_in[8]; } data_in; /* + * Status code is returned in case of CPUID access * Error code is returned in case of soft mailbox */ __u32 fw_ret_code; @@ -63,6 +78,7 @@ struct apml_message { * The IOCTL provides userspace access to AMD sideband protocols * The APML RMI module checks whether the cmd is * - Mailbox message read/write(0x0~0x999) + * - CPUID read(0x1000) * - returning "-EFAULT" if none of the above * "-EPROTOTYPE" error is returned to provide additional error details */ From patchwork Thu Sep 12 07:08:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801530 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2055.outbound.protection.outlook.com [40.107.96.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 862A518BBA7 for ; Thu, 12 Sep 2024 07:09:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.96.55 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124948; cv=fail; b=Qj+eqP+8MqaSKuc0P93z8pO3NtDoGeZbfLK8zLZnu82LQAUl8f6gVuaGPO4t+E9I7WxXS+QlRPDsMxQuVqtjiSMhqb7o0NYgXIdp6/8LiG4L6uEvqsOCExD9D9OM10BKs42BBlXs5Kd/ytB7U9XiECX0EYjm4crDViRX99b8OEM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124948; c=relaxed/simple; bh=uW5dOgPQm/D8CNLVBAQDoXHSnykIB3661jOBMayFIHU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NRtqQiTq9nWQ+OHTIyOxUgGXZkChQGxGU1H8xo+K2hHN3ZcAy+qlnz9f+kFhdM3PVnwgK9ooA65F6KkhKD+/Dl7mA9pUI9nhPoqkC6B8zubpdfKCf/k4scJ9TfTueCxLiI2atdlNv5NHgdcynsba1f3sX4WC8wndsplfsW4hH9M= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=gO6uKw4k; arc=fail smtp.client-ip=40.107.96.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="gO6uKw4k" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=SingobMDMFPQHOWMCfGYCG0Z1wtF9p5QRqSjphUT2m7p9TzDs1gTGMKhxUCW+SHqJMySdB7U1UeCot0BKoGL16feQamtvA8H8MgS6DmbAFcEOmfx8JQ+FEFcq2uDNhZwI3ERQg+IJRRgX2PJQMK+ZP7obIZ42gi0k1UQIlsLvEoruyzrymwnawwvYji6hHuctqiEmnGJa7pZ0R8NcCdZz+L2Urp/2+Z15TY8DBsnCS2icoqbXNj5OMuOz/lk287Zh60FJ/lRz/mA8kG8YPLoOrjQ6wN2qGCchszg1vbwnpRsyeWJORLbqlAoBeTrbblWx+WAxQjdjIvZm1gehX+tlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7nXpne9a8ESiuP/GQb/yNxlPpXPTUY4kaPpgK4DmRKY=; b=Ewg0xPsbl6GM6mTGNl9uS+hbztStMLQY1KFezetGb0M7vP2DUtt7cCwHfKqWs1X9ccyp8BZKVI55OCU7Fj9fcAHqOgTwIGD1sprb22nMkzTkXZwkSjH97Ph68ZUIhDTs4CYBwm+yfe0u/uKWlw7fL9YfPPWryDF9jUTc1d/lGde8uxZJvOnhUUkmXyV/0YstVcVcrYelb//P3U7QzxaZf+FYqcizUYVWB/V4m3i7pDviogimp91pEh9JxNqbzls3vAKfaSx3Y9tbjNvXGymKbNekngv5CX9jg6s3o3LLUBt0d+WfE8DXE5s97U2un9TB3JTRcWCr56M/u2Hyj2egKw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7nXpne9a8ESiuP/GQb/yNxlPpXPTUY4kaPpgK4DmRKY=; b=gO6uKw4kwofSXg7xC192gKCnE4h7G2lKepZPmqaBwkQCpDLiQUl+hsLpxbWqifh/JMSp2M1xJL4lepUXYnUuzFF0NgEA97Pe+FO59TTrITvTLnhhzMu/MGmODVD46oZ0WZxC+YYbSkZbFGPP3VIEmtVD39Xa2v5CzQDUd8DT+Vc= Received: from SJ0PR03CA0097.namprd03.prod.outlook.com (2603:10b6:a03:333::12) by PH8PR12MB6987.namprd12.prod.outlook.com (2603:10b6:510:1be::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7962.18; Thu, 12 Sep 2024 07:09:01 +0000 Received: from CO1PEPF000075F2.namprd03.prod.outlook.com (2603:10b6:a03:333:cafe::14) by SJ0PR03CA0097.outlook.office365.com (2603:10b6:a03:333::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.24 via Frontend Transport; Thu, 12 Sep 2024 07:09:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000075F2.mail.protection.outlook.com (10.167.249.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:09:00 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:56 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 7/9] misc: amd-sbi: Add support for MCA register protocol Date: Thu, 12 Sep 2024 07:08:08 +0000 Message-ID: <20240912070810.1644621-8-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F2:EE_|PH8PR12MB6987:EE_ X-MS-Office365-Filtering-Correlation-Id: f45032e6-66f6-49aa-3784-08dcd2f9c6b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: LGxOq5Agx64nnPmb50aG3HVOKNYVbdAku3WIZfyH2sHUp7ASy+zZuS98sUTJXW2zM1C1YVTdej+WE5nmmg48u4X7kB2Lxi1HwCt7RH8EktfTJIy/XqflEKAagn8XlrEfpaO3jMUwtZ0Ni3X7j8nx9y0xWQQR62Y9itvnhW4wVEGIJHr1UV3c+RGtn7xta2T0T2KjW0I28rPIPxWgYXm5CgtRhMT6LifLx7+11AeQNcXB8FvC8M7rzZ5p88yqXhHcmJZwZnf/9SuxcsWWu2AUlfNhJjGVKyNysatUvUVcxz798ik1Kzz0sWYFemIuOt2GhH93xUb0CXEzVPcbs4ig5sAWyO+QzHzb+0sdfAn1L1uqwT7NCAPZK/tXPXUwFHZIQNAI/b4WkkWGmmE1HollnpFl3acIlFogT7R48UDXgq0E8FBr3Dd9qTAzqYOb9onjYmJa74uQ/ZMQXFLYHWUiBGWstjMqi6zEaWNbICYjgriM/X80cBhA1wPbNqaPs+KmubD69n3+0sGawR5IfPcV4hvV3EOs4dNe+MMwnc7DdYzgnXzb1OBHSNi+rLXE70yQRE+vXqhvF8u/e582gGhnUZuQkhQAZeQIp6EBZXilXalB4nnFidTqInhlYRSEoJd2q014F4gmlBaNzXA6idE3vTv/VSmzzobRIcA2y6f0FR+25bClg2TUitmc8TxUGModgTv61SWeVJ5tRRj/hEraozhHH7GXWGotVsEW+/YppbhfvKZIr1DCYwS7Zdl7ClJiAOteIKt5mFc+pZ6wnJSFxgoA43EDZSQ2snMhNF9z250Itkgf8Zoja3hWK7yoFZwjobJyJYkJsKBT8ExP3NvTakuhrb+gNveUQ6goOHQtrGxHGEVTStMT5+ZMNmgC/PcxeJ5FSiMSGq2MMAnpOIeTwBKBpaAChl4maOnR0yvV/rJ4BeWrgxFCKuka+dcQktkp/t+m51fR7Nsl0fA/OypRHoMOmXMq4dgByFLaQJCsloFvo8yy9GQOSu8rvPBjy7hkGBh/9MRyBxe8Lw5r3vtwZkCTYmeEVjWpMRZT+MZIy755kdP1tSDKuSzFO2SgdT6il+7lpDXGGD3ZaCMN01xbd8SepuHvHj37HUmf9xDRiJF1UEkXM46AV7bnle2kMLhAoZ4Lz06EPXCnqOEMjeZeR5/WgX8AtF9rjmSqeHgCoepetZczNMDx/aOHaVBcezZ334Gxg4pDIQoEzl+CJOYPdCXsz7EAouAzhphKieiuZbK5SHqXX6HI41/40svTo65VIE73LHT1GQLth63W5tPhmESl9ZoebLwc0KlAICOLFOBdhlSMORKBFLPtkSvfmR4zOpnjStf6LfVu2QOvWzviwV+GOJrRMKQGK80PrK7k3dyBWW3+AFZ1w8djRdGZmDzIpf4KSqr0LM/7Lll1cr+4Rt7y3T89u7zFzscgXDtx6tJDXXH5cpWgLzV9v2YGLZQt X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:09:00.0659 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f45032e6-66f6-49aa-3784-08dcd2f9c6b5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6987 - AMD provides custom protocol to read Machine Check Architecture(MCA) registers over sideband. The inforamtion is accessed for range of MCA registers by passing register address and thread ID to the protocol. Access is read-only Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v3: - Address review comments: - update the #define to inline function - pack the union inside the structure Changes since v2: - update the MACROS name as per feedback Changes since v1: - bifurcated from previous patch 5 drivers/misc/amd-sbi/rmi-core.c | 100 ++++++++++++++++++++++++++++++++ include/uapi/misc/amd-apml.h | 18 ++++-- 2 files changed, 112 insertions(+), 6 deletions(-) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 3efb11ac2910..0ec7fcd1f73e 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -32,10 +32,16 @@ #define CPUID_WR_DATA_LEN 0x8 #define CPUID_RD_REG_LEN 0xa #define CPUID_WR_REG_LEN 0x9 +/* MSR */ +#define MSR_RD_REG_LEN 0xa +#define MSR_WR_REG_LEN 0x8 +#define MSR_RD_DATA_LEN 0x8 +#define MSR_WR_DATA_LEN 0x7 /* CPUID MSR Command Ids */ #define CPUID_MCA_CMD 0x73 #define RD_CPUID_CMD 0x91 +#define RD_MCA_CMD 0x86 /* input for bulk write to CPUID protocol */ struct cpu_msr_indata { @@ -72,6 +78,16 @@ static inline void prepare_cpuid_input_message(struct cpu_msr_indata *input, input->ext = ext_func; } +static inline void prepare_mca_msr_input_message(struct cpu_msr_indata *input, + u8 thread_id, u32 data_in) +{ + input->rd_len = MSR_RD_DATA_LEN; + input->wr_len = MSR_WR_DATA_LEN; + input->proto_cmd = RD_MCA_CMD; + input->thread = thread_id << 1; + input->value = data_in; +} + static int sbrmi_get_rev(struct sbrmi_data *data) { struct apml_message msg = { 0 }; @@ -169,6 +185,86 @@ static int rmi_cpuid_read(struct sbrmi_data *data, return ret; } +/* MCA MSR protocol */ +static int rmi_mca_msr_read(struct sbrmi_data *data, + struct apml_message *msg) +{ + struct cpu_msr_outdata output = {0}; + struct cpu_msr_indata input = {0}; + int ret, val = 0; + int hw_status; + u16 thread; + + mutex_lock(&data->lock); + /* cache the rev value to identify if protocol is supported or not */ + if (!data->rev) { + ret = sbrmi_get_rev(data); + if (ret < 0) + goto exit_unlock; + } + /* MCA MSR protocol for REV 0x10 is not supported*/ + if (data->rev == 0x10) { + ret = -EOPNOTSUPP; + goto exit_unlock; + } + + thread = msg->data_in.reg_in[AMD_SBI_THREAD_LOW_INDEX] | + msg->data_in.reg_in[AMD_SBI_THREAD_HI_INDEX] << 8; + + /* Thread > 127, Thread128 CS register, 1'b1 needs to be set to 1 */ + if (thread > 127) { + thread -= 128; + val = 1; + } + ret = regmap_write(data->regmap, SBRMI_THREAD128CS, val); + if (ret < 0) + goto exit_unlock; + + prepare_mca_msr_input_message(&input, thread, + msg->data_in.mb_in[AMD_SBI_RD_WR_DATA_INDEX]); + + ret = regmap_bulk_write(data->regmap, CPUID_MCA_CMD, + &input, MSR_WR_REG_LEN); + if (ret < 0) + goto exit_unlock; + + /* + * For RMI Rev 0x20, new h/w status bit is introduced. which is used + * by firmware to indicate completion of commands (0x71, 0x72, 0x73). + * wait for the status bit to be set by the hardware before + * reading the data out. + */ + ret = regmap_read_poll_timeout(data->regmap, SBRMI_STATUS, hw_status, + hw_status & HW_ALERT_MASK, 500, 2000000); + if (ret) + goto exit_unlock; + + ret = regmap_bulk_read(data->regmap, CPUID_MCA_CMD, + &output, MSR_RD_REG_LEN); + if (ret < 0) + goto exit_unlock; + + ret = regmap_write(data->regmap, SBRMI_STATUS, + HW_ALERT_MASK); + if (ret < 0) + goto exit_unlock; + + if (output.num_bytes != MSR_RD_REG_LEN - 1) { + ret = -EMSGSIZE; + goto exit_unlock; + } + if (output.status) { + ret = -EPROTOTYPE; + msg->fw_ret_code = output.status; + goto exit_unlock; + } + msg->data_out.cpu_msr_out = output.value; + +exit_unlock: + mutex_unlock(&data->lock); + return ret; +} + int rmi_mailbox_xfer(struct sbrmi_data *data, struct apml_message *msg) { @@ -284,6 +380,10 @@ static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) case APML_CPUID: ret = rmi_cpuid_read(data, &msg); break; + case APML_MCA_MSR: + /* MCAMSR protocol */ + ret = rmi_mca_msr_read(data, &msg); + break; default: pr_err("Command:0x%x not recognized\n", msg.cmd); break; diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h index 293532500450..f26b83b933de 100644 --- a/include/uapi/misc/amd-apml.h +++ b/include/uapi/misc/amd-apml.h @@ -7,8 +7,11 @@ #include -/* command ID to identify CPUID protocol */ -#define APML_CPUID 0x1000 +enum apml_protocol { + APML_CPUID = 0x1000, + APML_MCA_MSR, +}; + /* These are byte indexes into data_in and data_out arrays */ #define AMD_SBI_RD_WR_DATA_INDEX 0 #define AMD_SBI_REG_OFF_INDEX 0 @@ -24,13 +27,14 @@ struct apml_message { /* message ids: * Mailbox Messages: 0x0 ... 0x999 * APML_CPUID: 0x1000 + * APML_MCA_MSR: 0x1001 */ __u32 cmd; /* * 8 bit data for reg read, * 32 bit data in case of mailbox, - * up to 64 bit in case of cpuid + * up to 64 bit in case of cpuid and mca msr */ union { __u64 cpu_msr_out; @@ -40,8 +44,9 @@ struct apml_message { /* * [0]...[3] mailbox 32bit input - * cpuid, - * [4][5] cpuid: thread + * cpuid & mca msr, + * [4][5] cpuid & mca msr: thread + * [4] rmi reg wr: value * [6] cpuid: ext function & read eax/ebx or ecx/edx * [7:0] -> bits [7:4] -> ext function & * bit [0] read eax/ebx or ecx/edx @@ -53,7 +58,7 @@ struct apml_message { __u8 reg_in[8]; } data_in; /* - * Status code is returned in case of CPUID access + * Status code is returned in case of CPUID/MCA access * Error code is returned in case of soft mailbox */ __u32 fw_ret_code; @@ -79,6 +84,7 @@ struct apml_message { * The APML RMI module checks whether the cmd is * - Mailbox message read/write(0x0~0x999) * - CPUID read(0x1000) + * - MCAMSR read(0x1001) * - returning "-EFAULT" if none of the above * "-EPROTOTYPE" error is returned to provide additional error details */ From patchwork Thu Sep 12 07:08:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801532 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2077.outbound.protection.outlook.com [40.107.236.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A226518B486 for ; Thu, 12 Sep 2024 07:09:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.77 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124955; cv=fail; b=kcCko1E7pGKJ7feF2f05aKg2sjD2Hhqc1PVZnL4JlEVt+mVxn9hOUiZBoQahRW9ZnNMG5Kw6Wv6JWSGjRovqxS6F6h4U9lJMhRRjc5CWS7sHeEc1j6Lw1gLIUakZsbCLNnoXCJWom9dvfoykXrBG5J5eWAlQxTIQZswYxn2KoYE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124955; c=relaxed/simple; bh=h3Lmnlz528S8/t6/xm+dJSUg5+rr407M+k/crDtJlVo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MBcpXFcKFB3t3L1zxaBUVG1DxFDXcSoGTxZK/neDA21Q5DPWCVFtvmnzm6W8Ys2yzBjpNC+jXbkIidAJlkTHbr0EYkgx4lrumj3A1M83d8o3RJkj3O0Ufay+1LtmvBX33YjuHZoC+yRrPPdNAKcqo9PFCawnUlNThvh58kui7CM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=N3F5NU+e; arc=fail smtp.client-ip=40.107.236.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="N3F5NU+e" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=l9nQ0Wah4IjYLalSjizK6cXrbY39JgMbmoh4RUegeV2KV/t850dC5x8LTXf0EN7DY93AQeFPXmtkjFMutvI8Kq2XqqoPoSZef38Z+096yaBCLPb26k47Dk9ong7gICn1Fa3yC1CW3bbXnc54yUNwZv1wKIxo9UExi+Chyv3zQLDOXjX3DNUkiIGuwtY7nj5BDrVEj6na1scc4W5iGlD5s8vzwo66PLQE8vAcicLEtnu1LUhB8+XO4t1wscHcZxlYZCKxre9ajIvh2138mwnuZlmfCPFosGgBfQ/5FLghgePhr6XWeTvR+ftc1WYaiseMS02E64yWP499/9SJlgbIag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=N+nsiPfouhBfLPHb7BsksuSNiZWqezRoxR/yOS4ZXVU=; b=mhXCY08KfwYj4ZiDDBaYt3OHQ43By5IQpX9+re1S9TT1aIHfkql6Pr5kVAtGXf9VtJcTHN/sz/+DV/N/+XmSnC6QCsX+1lGI6UwqrNjKYCIn5WdquQNiXV93pbv6NrL8++YLk3SJ4f/J7aXMMw8/jrpOqs/Oqo7E2ltWb9JcC+8v9AjLMdPy+LJFmgCmFw2fp1QS0l2NJU9SOXbBhrLLWq26M/2MSH+nR3g3KCG+V5BbFXlsI0Qm4lcq4D1hXU9ElNB1xtY89QUyQkUfrD2dSP1RIaJvSq0LLnNuECzRIQc9t2xAC+UN2z/J0RshMfDPiMOXYUTvBbva8RwHw4dw6Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=N+nsiPfouhBfLPHb7BsksuSNiZWqezRoxR/yOS4ZXVU=; b=N3F5NU+eNPI9kRx7xVyRxNNHA7S3fMhd4goAJdWrE6Pk5KTz4p0XHlo4nWjCgKLh9R10GoOn68YLgDXfP3R3jo74yNftWXRXAgJ2hxzMR8X9JgBW3iW8xvyeoxzWwnBYm7Knoj78zVZtuYsBP/i5vDRTd1AsJSfiNxYBLSZGOV0= Received: from BY3PR03CA0021.namprd03.prod.outlook.com (2603:10b6:a03:39a::26) by CH2PR12MB4167.namprd12.prod.outlook.com (2603:10b6:610:7a::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7962.18; Thu, 12 Sep 2024 07:09:08 +0000 Received: from CO1PEPF000075EF.namprd03.prod.outlook.com (2603:10b6:a03:39a:cafe::bf) by BY3PR03CA0021.outlook.office365.com (2603:10b6:a03:39a::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.24 via Frontend Transport; Thu, 12 Sep 2024 07:09:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000075EF.mail.protection.outlook.com (10.167.249.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:09:07 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:59 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 8/9] misc: amd-sbi: Add supoort for register xfer Date: Thu, 12 Sep 2024 07:08:09 +0000 Message-ID: <20240912070810.1644621-9-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075EF:EE_|CH2PR12MB4167:EE_ X-MS-Office365-Filtering-Correlation-Id: 94d0beb2-0550-4140-7982-08dcd2f9cb11 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: lThCb/1XcgUbja1SDZEOYk8hqxv+s4va7csXsF3+JuZYlxF5bM3tBPg9NIcpbG+Bw9yV+qxWoqvpiia2rT7Tfi+DY+agM6uPh2Xr+jQARWAVaFbuSOkX+M99m+S402rgsrtIqii16QjM3IJz5V9U0/WWu6wqh8UVYObJmRUtRCBvy0uayMIPSHdWQYM9kXaCowPeqqM+Cei5u8TrSxdw5qY1emQyG0l7mNvCi5kmokd2FXG1cSQFINvHYOPRoyr+J9SBg5pw3B8vUNLS5Pa8+BOtqQhZ2OAHElQs/cbFshkbNp41o+DSXL6czrQB5OW/6hMVkZhkYj+th+PvyPGNLvRTjlZIpPjI49ZDoh/7k/9R1V6yHcPYLDcnqpmPahvX5nbFudMxiYAiMSAwL0rSsfSd49GCP46P1qC+Lhyr8cN/gS0PmTGhl3bx8Oyur40H9HsrAxi0FlWnhQRcW+fMZK5Ct4dvAX2X0agVEssB228CX0mY6VMp8Xc6uZ+AcSI/jav8bSXJqACX5Hgc1KSPVPiWxXGtXqy9qtqVGdp/yW3bYolfMJTRNFNOwOHcvDj1aV6dP2FxX0yShM4hJw5mFc2d5QwKMg/i4u9zpA39M3gafHr4xLiRyEmW95ieweGk3Hg7499aM5PpShxvxvj4BZxqMfnDUPl/IWQoM13D7nLlws1l5Gx8OBa2SxykFmFZ/RJSuZon23rNRjSg2qHC1mPSDCCrVZf9UGM86rQzaytOMljx2oXEvSJQ5BHtb14ksD/e5d78ichb/Iqt5VGDZS5j/XzfgnuU1X+nPBvYHwpgqefoQTGSDnYFOs1Vmjcj9VI74lNkhOY90r6lrc5jxO7K1N7cuxkCYKdf8ACM2gXekdUsy+30dzC3tJEH55ShPgZgVrB8Eu71XGALwW7shaMVxfb3Ab2B3HgjE0p6K/FEh/zI4fGC69kKfSvx9ra2pFE+TNN0faT+sUg3326aVEZD1029XBBlA3FnBoi/F/bChe2jdIU9JXpNyHL9pDn+yuPDgk9SO3Pqr+WWrZ+q8HW6Nqw0DNcDwoAmIQptcxwHB9YfTmX9i79qbx33Hw8hCmAQcTPUNUoLrABJjNBbs2MZ/tfbXpPKddBi8gZpw7HGlOQoTKYE+p4XnNg0ZHWKPjecPPWipVdY8q6BGWIG7KT00RjSvJD03NkhGYdpbDcSQmqps7dP9Jj1E/MIACpAZVrHFu3trLSznrK77dAH4Hy1ONW9uNw5iqJ0QbNWW0iEVkRCI/8q6PZwULp/0pZtT6mYzdN2bXv1PHvq6siaEudTWn3wlrO0QqypfA1Jnoa0qmns7ZD1F7bVhveYYovqGqF9XQL778TrUxmNOSEihc/4dGvHOVMEY8DwReANkt8AL4/h9/9KbHQzMaf5sYiW7vqIMfzqwt4RDnKKRb7lN9RYVEYX131KqpFJutZqpRqdI0I/jU06ztYFqWV/hLc7 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:09:07.3658 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 94d0beb2-0550-4140-7982-08dcd2f9cb11 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075EF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4167 - Provide user register access over IOCTL. Both register read and write are supported. - APML interface does not provide a syncronysation method. By defining, a register access path, we use APML modules and library for all APML transactions. Without having to use external tools such as i2c-tools, which may cause race conditions. Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v2: - Add ioctl description comment Changes since v2: - update the MACROS name as per feedback Changes since v1: - bifurcated from previous patch 5 drivers/misc/amd-sbi/rmi-core.c | 22 ++++++++++++++++++++++ include/uapi/misc/amd-apml.h | 4 ++++ 2 files changed, 26 insertions(+) diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 0ec7fcd1f73e..7907524909e2 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -351,6 +351,24 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, return ret; } +static int rmi_register_xfer(struct sbrmi_data *data, + struct apml_message *msg) +{ + int ret; + + mutex_lock(&data->lock); + if (msg->data_in.reg_in[AMD_SBI_RD_FLAG_INDEX]) + ret = regmap_read(data->regmap, + msg->data_in.reg_in[AMD_SBI_REG_OFF_INDEX], + &msg->data_out.mb_out[AMD_SBI_RD_WR_DATA_INDEX]); + else + ret = regmap_write(data->regmap, + msg->data_in.reg_in[AMD_SBI_REG_OFF_INDEX], + msg->data_in.reg_in[AMD_SBI_REG_VAL_INDEX]); + mutex_unlock(&data->lock); + return ret; +} + static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) { int __user *arguser = (int __user *)arg; @@ -384,6 +402,10 @@ static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) /* MCAMSR protocol */ ret = rmi_mca_msr_read(data, &msg); break; + case APML_REG: + /* REG R/W */ + ret = rmi_register_xfer(data, &msg); + break; default: pr_err("Command:0x%x not recognized\n", msg.cmd); break; diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h index f26b83b933de..ea8ebff495bf 100644 --- a/include/uapi/misc/amd-apml.h +++ b/include/uapi/misc/amd-apml.h @@ -10,6 +10,7 @@ enum apml_protocol { APML_CPUID = 0x1000, APML_MCA_MSR, + APML_REG, }; /* These are byte indexes into data_in and data_out arrays */ @@ -28,6 +29,7 @@ struct apml_message { * Mailbox Messages: 0x0 ... 0x999 * APML_CPUID: 0x1000 * APML_MCA_MSR: 0x1001 + * APML_REG: 0x1002 */ __u32 cmd; @@ -45,6 +47,7 @@ struct apml_message { /* * [0]...[3] mailbox 32bit input * cpuid & mca msr, + * rmi rd/wr: reg_offset * [4][5] cpuid & mca msr: thread * [4] rmi reg wr: value * [6] cpuid: ext function & read eax/ebx or ecx/edx @@ -85,6 +88,7 @@ struct apml_message { * - Mailbox message read/write(0x0~0x999) * - CPUID read(0x1000) * - MCAMSR read(0x1001) + * - Register read/write(0x1002) * - returning "-EFAULT" if none of the above * "-EPROTOTYPE" error is returned to provide additional error details */ From patchwork Thu Sep 12 07:08:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801531 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2081.outbound.protection.outlook.com [40.107.223.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96357187866 for ; Thu, 12 Sep 2024 07:09:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.81 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124954; cv=fail; b=UCnxFYOMkuuEtzlchkHiz603FyJZdi1/btFHdwAn7JDacwId7FzdEguw3o6sIPvGCwWC89OgXIGECD9yy/mrnH7KLRQYm/pu4foqnEUXveKxYH1WREXt67UDCZOQelxL++jAm5vq0VZWdJ3QKq3JcK+942aB4auWXr19O940q5E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124954; c=relaxed/simple; bh=2xph8UGRIWF3O4IhlJqMmHD+BLPycU5PIS1Qz+s5Eag=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iqz3PEq5ifka2EOschcd0a+V9EDSNMulW7P/gHhedUY01ysrxfiWzA+m02cnDDMvzT6aSYIZfSUsY3oUI5ausfSMNIlznm709que8kk2l5hyxKYDM9BisJQmsP2jehceHXmPMEO9IA9pk/9R9KN/40AtR2v+Tc8Y1C+rN1W/gTc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=xAoBbRUV; arc=fail smtp.client-ip=40.107.223.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="xAoBbRUV" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=WdWRVrwBnMtnvY5xsA9pJE6o/pTiWthtpM3AImwAGNJAxdnZnYAODhMgVemQK5lKwxbpx/UvFBHcTAQYDoyErr3wQgekm0PMcOyzR3fzc0HSkyqlnkwZC1ZFE/ryNPWBTYY7Oqe3e2IxlBQfFyUHowNqXoBr2BUzQLvr2PBGIJ54UA6TQ+2Bx6VCa9rLZbKzIo+UPU7CGmDh8FENBn9VtCsAy6/6s0bkOVUVkpUcxtCu5GzsKg9cJ7NGgaVAdSWHFWSeIMl0fA9Hdu4hcaVbCnONfUPH3K8MXq0mp6Rl3wVRlSIETBIqNmQMWwHv5hJGnQHjw28OF+TXRM1AkbVgaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=o4DxOb0LYVX7FhcTgGwhKYild4t5rHRoV/imQJTDYjg=; b=BDGgAnq1i2qFUIoo+Z9F509M/FBOQ4JfDeNZD/KYdYnTc2Lm01QyQFrInbHliAYUC9dmxI0ZTsdkE5o5KzURPT5GlYc4tC2Zwl5khXt4xb19w62CIraQpfzYSAesa7jyZPln2UQ+A8T8mNMgtQn69hRlQ2XTghv8H/6e3uLuIvN9zrPfibIn0B4xmkOAGdrM5HDwYRFRDnXWxXwBpTkuHf+2ecHxQzgVrYebwhi8oPFXlPJlo2W6TXXOjhdFA8fkDwvZtQgrBdf5vGs4elCZ4XB8426rVh1kw3b+4MuSlaC1Amh02erKsmC+nCOToRZbQAyscJFTouKw3PulNGt7qg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=o4DxOb0LYVX7FhcTgGwhKYild4t5rHRoV/imQJTDYjg=; b=xAoBbRUVRQYV2x6dpg7FGHygRnqBIqcXDJUBRG+q5CndkhroO85kiD9TREm1uNaxnpb24vgE7zlWizhjkzB3hK4GNyA4qyA0x/zhDpqQKac8l2kwCkzlSMXoa9nqiLGEZQGP54ZsvjeeLGOoDKbSnuMTs+9TRvufbbUAELfUbdI= Received: from BY3PR03CA0009.namprd03.prod.outlook.com (2603:10b6:a03:39a::14) by BY5PR12MB4130.namprd12.prod.outlook.com (2603:10b6:a03:20b::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7962.17; Thu, 12 Sep 2024 07:09:08 +0000 Received: from CO1PEPF000075EF.namprd03.prod.outlook.com (2603:10b6:a03:39a:cafe::9b) by BY3PR03CA0009.outlook.office365.com (2603:10b6:a03:39a::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.24 via Frontend Transport; Thu, 12 Sep 2024 07:09:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000075EF.mail.protection.outlook.com (10.167.249.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:09:08 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:09:03 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 9/9] misc: amd-sbi: Add document for AMD SB IOCTL description Date: Thu, 12 Sep 2024 07:08:10 +0000 Message-ID: <20240912070810.1644621-10-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075EF:EE_|BY5PR12MB4130:EE_ X-MS-Office365-Filtering-Correlation-Id: 383daf75-47d5-4ab2-8501-08dcd2f9cbbf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: ZCOEzLO+6shFbOm2eYBi1Vj+vn4+CfXrGJVDIw7mYkWzdd5cCmJv5aozXO+ZWLvP/9NQ7Xw5d9Wqr2wIJbzR2sGqy/+hLpN1FRkjLZS9U4xzb0k0HO9eBF7EWo2X9z0PuereYe6Xtha8obXkUmipMOHo0plDctQJlfGCnsjHiz4cH9FHe68UaaBrVi+QA30bZokh7QwVMkJC4gaV3As064pgmP1FR1AZ7KFZxSmA0Np6gkkOQap1veWs0QgicMUcuZr9BUFa5RpRs90WZG6ujdLRUT62lQ0bGIlQxSICMp6R2iTz+D7bPGH11zcfAQ+KajmTqJIbKmLSSHSEBr2Cwwz1WFikfoB+ghgv1qbkjGike9CVwNqTtysRQEPTEz6M5q0OmWm3Ri+Wa/pwEYiuV/+hyxgjJjmqw+pF7WTDTmi5QDoHLbH2QF3ZNs0eVn7MxPdC4usLe1lpDoI++CpTroMo/QMAExNOxzetqDKTV0U6cldsyC3uXystAratgMX80Kvk+HSaw928T5OkO+Vpp8aC2lGei/Q6XUqJVWn2DObHQzIuYqPpdoLAQCW3r6fE9z7g1CEN9xE91DaYxEcBFbBk/Khs6dYxCA+4LhlvE+sivXLmoZDrwrq4huwGuu7M79UqP8GBk5ivLcmUhyX4G7vGNDQwFSTVUvuaHQEtMczPNNvlOOppVEqjKKmA2X/k6vVBaxFR13aO+P6TA/qDw/upLlnqiL9kAOoLfB8v91f5Uzo6LOHLoWVjz2ad9Vfxkfy7QfporT3PnwW/7CZAlEbPDQiMRk4K54Tnb6p/0XcR+RQ+cKZuYI86FdviZBhUZ2jFlrHnxb9A9L51/5t09VQBlFOmKjqed0NrCLRfeUxJQrzj+etS27R1CVktWML7j0uuU9XLJicnBoUmqy5TSgUGGyfRXOhemSWzA8BIQ2zVabgmfKEqwtSvY6YzDeDunVR5hC/Aqclg8qP+c4HQr8WPKlui54Ujglpjy621oFBuDeMhXUceDbHznmsG+U5iXh4aPeim252cqZ+aQOZF3a5o2mGvKBZgwseH/NyoZH+O1uXP7J/IuUnnUiKJdSypwuE1Gr3kWsFYCLoC8ul9A6irfvVQcaFjRMMhziibaId0EToXQkLWjpeqmOviGgoc7sok8Ph07QWxJ/pYYUHaF9LP/BqrsWH3oKpsELukPABeYSeJVAeJfvKAW5KAYnBxKuPlQub3I2tF//JUjcbD/n31u627O7p1EA19NZqaI/ERNKbE6q1oyQpARbmNbV1eybNVXsuRCPOTzM58lb+2Hxc7ZzgGYCdPTL6MYQp+9hPSfP3cPveF4ANLdDAirRBL/2KaXxR+D0vv7d7olhtuEx59VfGwsyMusc7lgAPyoLJ1V8AEKKDSMu7qTIoav4FKS2Tr3+jE5TNkHEMfnSFvjQXjqZ7qgV4vaVvN3E4m1JGrYA0v3LUFyXigAS0qynEYLPmIWWeDvpJNTY8p49miDA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:09:08.5065 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 383daf75-47d5-4ab2-8501-08dcd2f9cbbf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075EF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4130 - This document provide AMD side band IOCTL description defined for APML and its usage. Multiple AMD custom protocols defined for side band system management uses this IOCTL. User space C-APIs are made available by esmi_oob_library, hosted at https://github.com/amd/esmi_oob_library which is provided by the E-SMS project https://www.amd.com/en/developer/e-sms.html. Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v2: - Address the review comments Changes since v2: - update the MACROS name as per feedback Changes since v1: - New patch Documentation/misc-devices/amd-sbi.rst | 84 ++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/misc-devices/amd-sbi.rst diff --git a/Documentation/misc-devices/amd-sbi.rst b/Documentation/misc-devices/amd-sbi.rst new file mode 100644 index 000000000000..6e2ba6fa323a --- /dev/null +++ b/Documentation/misc-devices/amd-sbi.rst @@ -0,0 +1,84 @@ +.. SPDX-License-Identifier: GPL-2.0 + +======================= +AMD SIDE BAND interface +======================= + +AMD server line of processors supports system management +functionality via side-band interface (SBI) called +Advanced Platform Management Link (APML). APML is an I2C/I3C +based 2-wire processor target interface. APML is used to +communicate with the Remote Management Interface +(SB Remote Management Interface (SB-RMI) +and SB Temperature Sensor Interface (SB-TSI)). + +More details on the interface can be found in chapter +"5 Advanced Platform Management Link (APML)" of the family/model PPR +Eg: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/55898_B1_pub_0_50.zip + + +SBRMI device +============ + +apml_sbrmi driver under the drivers/misc/amd-sbi creates miscdevice +/dev/sbrmi-* to let user space programs run APML mailbox, CPUID, +MCAMSR and register xfer commands. + +Register sets is common across APML protocols. IOCTL is providing synchronization +among protocols as transactions may create race condition. + +$ ls -al /dev/sbrmi-3c +crw------- 1 root root 10, 53 Jul 10 11:13 /dev/sbrmi-3c + +apml_sbrmi driver registers hwmon sensors for monitoring power_cap_max, +current power consumption and managing power_cap. + +Characteristics of the dev node: + * message ids are defined to run differnet xfer protocols: + * Mailbox: 0x0 ... 0x999 + * CPUID: 0x1000 + * MCA_MSR: 0x1001 + * Register xfer: 0x1002 + +Access restrictions: + * Only root user is allowed to open the file. + * APML Mailbox messages and Register xfer access are read-write, + * CPUID and MCA_MSR access is read-only. + +Driver IOCTLs +============= + +.. c:macro:: SBRMI_IOCTL_CMD +.. kernel-dec:: include/uapi/misc/amd-apml.h + :doc: SBRMI_IOCTL_CMD + +User-space usage +================ + +To access side band interface from a C program. +First, user need to include the headers:: + + #include + +Which defines the supported IOCTL and data structure to be passed +from the user space. + +Next thing, open the device file, as follows:: + + int file; + + file = open("/dev/sbrmi-*", O_RDWR); + if (file < 0) { + /* ERROR HANDLING */ + exit(1); + } + +The following IOCTL is defined: + +``#define SB_BASE_IOCTL_NR 0xF9`` +``#define SBRMI_IOCTL_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_message)`` + + +User space C-APIs are made available by esmi_oob_library, hosted at +https://github.com/amd/esmi_oob_library which is provided by the E-SMS +project https://www.amd.com/en/developer/e-sms.html.