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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5365f9038e3sm2348008e87.187.2024.09.13.08.58.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 08:58:08 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f8e3888c-71e8-11ef-a0b5-8be0dac302b0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726243089; x=1726847889; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fJg7BHwepPlrOFfGyIMBAxXTIqwMuFC09Emwsc98p9A=; b=jp9ZEJNsOgo+lQdrxk99q3hiCN8Hu8AIImpRhECvzxtbnvycpszkysD4Ys66gw10e4 d314zWkpQNQiyGj7DR7snNwWz9uejE9RMaxwrcppQNl2nhzsQbKZ/08BMj+kEwSUn0qY IoIVYKALmWfxueYgAovZKAk6Ndxdq/LWV2zoY4QCUoG4PXe0XMfe9vS+lAf+ydZQ+8cM MJUviFDKdAK8YZjlw11ifO2DjuZBRmU4tHVLgT7imNg3u4i3zdOnCzcjTr2bzaciK+vF pEXR1MZztHpDi7wOXKGs8GQ/xFkwLoumWUt9IkjuvjIvWVXO3BdwShXPOYFGM42SN3Bf 3bfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726243089; x=1726847889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fJg7BHwepPlrOFfGyIMBAxXTIqwMuFC09Emwsc98p9A=; b=YRU9puhlA5hU9R5CLSWaDsDO7q/cLvVYIjixm5XxtvoM0o6eSS+kPXzWZTkA7Uubh4 cKwvmNA/8eCP6/H7Dv9B+s19FeU+nUdK+x2ZFCK7jaQOyvhyw1YCic/0sCnqtbp5rJPO rXmP8k83rBkz1A2gkur58dMQyApLhNvik9h/Dt+vYukolhADgElsY4bZutr4qAhjOk3S azGNOBtmgdwsvlbQPZQEGSisKF68xSsuhA5WHGKYr/TY1/IWSBGklp74w3xdyRqtAtp6 KVV0dU9C8xUHEjgAuXwI7xX4Y5D3DDnmn5nUvKPDYPryH7uWSmgdk4YXLeHn5wCXm1MR tbHw== X-Gm-Message-State: AOJu0YzBecsGP8BZyTXT7zhLiy7t/TgQrf07g531hZuXgfr9h8/Gq6tg tDE/epiICri3UGNRGA+YXzoFgpHH8szIlCVvqUPRXWGvlXMG0mbiZCy85Q== X-Google-Smtp-Source: AGHT+IGyerPNv3cTkkP8/mhFa7Oun1skPrgXmUdJP4qFrPMpotmkkHOAK1pV1Pbx0FAK+//At8N42Q== X-Received: by 2002:a05:6512:224c:b0:535:6892:3be3 with SMTP id 2adb3069b0e04-53678fe63c0mr4886633e87.41.1726243088410; Fri, 13 Sep 2024 08:58:08 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v7 1/8] xen/riscv: use {read,write}{b,w,l,q}_cpu() to define {read,write}_atomic() Date: Fri, 13 Sep 2024 17:57:39 +0200 Message-ID: <7235612db1c273638263b45c59655328256b8cf2.1726242605.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 The functions {read,write}{b,w,l,q}_cpu() do not need to be memory-ordered atomic operations in Xen, based on their definitions for other architectures. Therefore, {read,write}{b,w,l,q}_cpu() can be used instead of {read,write}{b,w,l,q}(), allowing the caller to decide if additional fences should be applied before or after {read,write}_atomic(). Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in V7: - Nothing changed. Only rebase. --- Changes in V6: - revert changes connected to _write_atomic() prototype and in definition of write_atomic(). - update the commit message. --- Changes in v5: - new patch. --- xen/arch/riscv/include/asm/atomic.h | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/asm/atomic.h index 41f03b2e0c..95910ebfeb 100644 --- a/xen/arch/riscv/include/asm/atomic.h +++ b/xen/arch/riscv/include/asm/atomic.h @@ -31,21 +31,17 @@ void __bad_atomic_size(void); -/* - * Legacy from Linux kernel. For some reason they wanted to have ordered - * read/write access. Thereby read* is used instead of read*_cpu() - */ static always_inline void read_atomic_size(const volatile void *p, void *res, unsigned int size) { switch ( size ) { - case 1: *(uint8_t *)res = readb(p); break; - case 2: *(uint16_t *)res = readw(p); break; - case 4: *(uint32_t *)res = readl(p); break; + case 1: *(uint8_t *)res = readb_cpu(p); break; + case 2: *(uint16_t *)res = readw_cpu(p); break; + case 4: *(uint32_t *)res = readl_cpu(p); break; #ifndef CONFIG_RISCV_32 - case 8: *(uint64_t *)res = readq(p); break; + case 8: *(uint64_t *)res = readq_cpu(p); break; #endif default: __bad_atomic_size(); break; } @@ -58,15 +54,16 @@ static always_inline void read_atomic_size(const volatile void *p, }) static always_inline void _write_atomic(volatile void *p, - unsigned long x, unsigned int size) + unsigned long x, + unsigned int size) { switch ( size ) { - case 1: writeb(x, p); break; - case 2: writew(x, p); break; - case 4: writel(x, p); break; + case 1: writeb_cpu(x, p); break; + case 2: writew_cpu(x, p); break; + case 4: writel_cpu(x, p); break; #ifndef CONFIG_RISCV_32 - case 8: writeq(x, p); break; + case 8: writeq_cpu(x, p); break; #endif default: __bad_atomic_size(); break; } From patchwork Fri Sep 13 15:57:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13803796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6765EFC6160 for ; Fri, 13 Sep 2024 15:58:27 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.798298.1208479 (Exim 4.92) (envelope-from ) id 1sp8gY-0000NV-Io; Fri, 13 Sep 2024 15:58:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 798298.1208479; Fri, 13 Sep 2024 15:58:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8gY-0000MC-B5; Fri, 13 Sep 2024 15:58:14 +0000 Received: by outflank-mailman (input) for mailman id 798298; Fri, 13 Sep 2024 15:58:13 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8gX-0000AA-Q1 for xen-devel@lists.xenproject.org; Fri, 13 Sep 2024 15:58:13 +0000 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [2a00:1450:4864:20::134]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id fa1ba0d1-71e8-11ef-99a2-01e77a169b0f; Fri, 13 Sep 2024 17:58:11 +0200 (CEST) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-5365cf5de24so3009708e87.1 for ; Fri, 13 Sep 2024 08:58:11 -0700 (PDT) Received: from fedora.. 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V7: - use union in definition of write_atomic() to add support of non-scalar types. --- Changes in v6: - new patch. --- xen/arch/riscv/include/asm/atomic.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/asm/atomic.h index 95910ebfeb..e2dbb391f0 100644 --- a/xen/arch/riscv/include/asm/atomic.h +++ b/xen/arch/riscv/include/asm/atomic.h @@ -69,10 +69,11 @@ static always_inline void _write_atomic(volatile void *p, } } -#define write_atomic(p, x) \ -({ \ - typeof(*(p)) x_ = (x); \ - _write_atomic(p, x_, sizeof(*(p))); \ +#define write_atomic(p, x) \ +({ \ + union { typeof(*(p)) v; unsigned long v_ul; } x_ = { .v_ul = 0UL }; \ + x_.v = (x); \ + _write_atomic(p, x_.v_ul, sizeof(*(p))); \ }) static always_inline void _add_sized(volatile void *p, From patchwork Fri Sep 13 15:57:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13803797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39C17FC6161 for ; Fri, 13 Sep 2024 15:58:27 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.798299.1208494 (Exim 4.92) (envelope-from ) id 1sp8ga-0000tJ-Me; Fri, 13 Sep 2024 15:58:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 798299.1208494; Fri, 13 Sep 2024 15:58:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8ga-0000t9-Jo; Fri, 13 Sep 2024 15:58:16 +0000 Received: by outflank-mailman (input) for mailman id 798299; Fri, 13 Sep 2024 15:58:14 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8gY-0000AA-S4 for xen-devel@lists.xenproject.org; Fri, 13 Sep 2024 15:58:14 +0000 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [2a00:1450:4864:20::12a]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id faccde29-71e8-11ef-99a2-01e77a169b0f; Fri, 13 Sep 2024 17:58:12 +0200 (CEST) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-5365cf5de24so3009741e87.1 for ; Fri, 13 Sep 2024 08:58:12 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5365f9038e3sm2348008e87.187.2024.09.13.08.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 08:58:10 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: faccde29-71e8-11ef-99a2-01e77a169b0f DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726243091; x=1726847891; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EGdJ9IsS5M9LmJSGQ62QXYWpBMxLZyVYfJvgQdXSIJ0=; b=XGtbYkmNeA2sQrimUur2BZW42xm4j4yYIZbZBUiGRL4ldMccTa3zkWjhVRDolBqsWI S5NZ4aNp0EFplTbjE2CTxvj08JI8pzOVP8wJescIu2ohzkdky978C4h+PyZn4gyzDtYB dCbBzGW34Q7ww6bZCsZfK69ZS92anDUGgLLBggrIRWHE6/U4eEKQQB+xymQkzBVgzWfu JPTZ/7AwSXavLw4pl0oaK/hA8LOdFqTCzCa3r/H+xuhdM32FVlpLskaw0DRWUHA0cbP3 wburrhNG6LpUyLFfbUK2uszV8ajfAIbwEOTElqLyagV6aDUIkxc0WtSva0EkG7w2T+5K ztQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726243091; x=1726847891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EGdJ9IsS5M9LmJSGQ62QXYWpBMxLZyVYfJvgQdXSIJ0=; b=RNECQ5+B7fColI6eRqa1H4uae8+mPKxkkT0xyAJ+rV2+pB0pKyY6DYYr62v23Abc0q Kp/BL7yzmer6UBHpt3y1NbTqH+dIzNE+/EiKh0LZxushSEPhwMNf/sGkYNBzy/VlV7VR E9NNBNdyuO6XdxV1ojVszFPjWj+aq+Iw9PRu4GHXV8Cz4LgG3Bf1bzKu0DxWGxVa5VOq xX0r2fZ3OI+DBFqOx50/8/AjJ8bpF6oYDJ5XyuvluysrOdRniqK/CJZuCVwA7soie6tg DpTivGmq0Kn8N9zV0FRBSPR3Idjts2obL+VW6i5xfrxAMS4FLXGdJSAg/zneJX4BQedJ SMNQ== X-Gm-Message-State: AOJu0YyH9U6lgPvUWQ+Xt087Nmaj6Q82NC3jltI5HQfTyMtneqC54LEn Xqf+95MPSYGFfaV5OFzaOTgAbJJlZRZGeyx4huq26gVtTOCU9LDFg7gktg== X-Google-Smtp-Source: AGHT+IGm1IMBo6IsWyzmmi6mEIl44QjsrJLn/KePWrukKRND/LPA80neLtOYWYI8/eFH4+edsKkg7g== X-Received: by 2002:a05:6512:33cf:b0:52e:fd53:a251 with SMTP id 2adb3069b0e04-53678fec73amr4693842e87.59.1726243091099; Fri, 13 Sep 2024 08:58:11 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v7 3/8] xen/riscv: set up fixmap mappings Date: Fri, 13 Sep 2024 17:57:41 +0200 Message-ID: <779334f22d3770f7de6a630d2e6ace20c95bb32b.1726242605.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Set up fixmap mappings and the L0 page table for fixmap support. {set, clear}_fixmap() is expected to be implemented using map_pages_to_xen(), which, in turn, is only expected to use arch_pmap_map(). Define new macros in riscv/config.h for calculating the FIXMAP_BASE address, including BOOT_FDT_VIRT_{START, SIZE}, XEN_VIRT_SIZE, and XEN_VIRT_END. Update the check for Xen size in riscv/lds.S to use XEN_VIRT_SIZE instead of a hardcoded constant. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V7: - make const the argument of read_pte(). - update the commit message. --- Changes in V6: - avoid case mixing for address in RISC-V64 layout table. - move definition of FIXMAP_BASE to new line. - update the commit message. --- Changes in V5: - move definition of FIXMAP_ADDR() to asm/fixmap.h - add gap size equal to 2 MB ( 512 * 4K one page table entry in L1 page table ) between Xen, FDT and Fixmap. - drop the comment for FIX_LAST. - move +1 from FIX_LAST definition to FIXADDR_TOP to be aligned with Arm. ( probably everything below FIX_LAST will be moved to a separate header in asm/generic.h ) - correct the "changes in V4: s/'fence r,r'/'fence rw, rw' - use write_atomic() in set_pte(). - introduce read_pte(). --- Changes in V4: - move definitions of XEN_VIRT_SIZE, BOOT_FDT_VIRT_{START,SIZE}, FIXMAP_{BASE,ADDR} below XEN_VIRT_START to have definitions appear in order. - define FIX_LAST as (FIX_MISC + 1) to have a guard slot at the end. - s/enumerated/numbered in the comment - update the cycle which looks for L1 page table in setup_fixmap_mapping_function() and the comment above him. - drop fences inside write_pte() and put 'fence rw,rw' in setup_fixmap() before sfence_vma(). - update the commit message - drop printk message inside setup_fixmap(). --- Changes in V3: - s/XEN_SIZE/XEN_VIRT_SIZE - drop usage of XEN_VIRT_END. - sort newly introduced defines in config.h by address - code style fixes - drop runtime check of that pte is valid as it was checked in L1 page table finding cycle by BUG_ON(). - update implementation of write_pte() with FENCE rw, rw. - add BUILD_BUG_ON() to check that amount of entries aren't bigger then entries in page table. - drop set_fixmap, clear_fixmap declarations as they aren't used and defined now - update the commit message. - s/__ASM_FIXMAP_H/ASM_FIXMAP_H - add SPDX-License-Identifier: GPL-2.0 --- xen/arch/riscv/include/asm/config.h | 16 ++++++++-- xen/arch/riscv/include/asm/fixmap.h | 46 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/mm.h | 2 ++ xen/arch/riscv/include/asm/page.h | 13 ++++++++ xen/arch/riscv/mm.c | 43 +++++++++++++++++++++++++++ xen/arch/riscv/setup.c | 2 ++ xen/arch/riscv/xen.lds.S | 2 +- 7 files changed, 121 insertions(+), 3 deletions(-) create mode 100644 xen/arch/riscv/include/asm/fixmap.h diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index 50583aafdc..7dbb235685 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -41,8 +41,10 @@ * Start addr | End addr | Slot | area description * ============================================================================ * ..... L2 511 Unused - * 0xffffffffc0600000 0xffffffffc0800000 L2 511 Fixmap - * 0xffffffffc0200000 0xffffffffc0600000 L2 511 FDT + * 0xffffffffc0a00000 0xffffffffc0c00000 L2 511 Fixmap + * ..... ( 2 MB gap ) + * 0xffffffffc0400000 0xffffffffc0800000 L2 511 FDT + * ..... ( 2 MB gap ) * 0xffffffffc0000000 0xffffffffc0200000 L2 511 Xen * ..... L2 510 Unused * 0x3200000000 0x7f40000000 L2 200-509 Direct map @@ -74,6 +76,16 @@ #error "unsupported RV_STAGE1_MODE" #endif +#define GAP_SIZE MB(2) + +#define XEN_VIRT_SIZE MB(2) + +#define BOOT_FDT_VIRT_START (XEN_VIRT_START + XEN_VIRT_SIZE + GAP_SIZE) +#define BOOT_FDT_VIRT_SIZE MB(4) + +#define FIXMAP_BASE \ + (BOOT_FDT_VIRT_START + BOOT_FDT_VIRT_SIZE + GAP_SIZE) + #define DIRECTMAP_SLOT_END 509 #define DIRECTMAP_SLOT_START 200 #define DIRECTMAP_VIRT_START SLOTN(DIRECTMAP_SLOT_START) diff --git a/xen/arch/riscv/include/asm/fixmap.h b/xen/arch/riscv/include/asm/fixmap.h new file mode 100644 index 0000000000..63732df36c --- /dev/null +++ b/xen/arch/riscv/include/asm/fixmap.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * fixmap.h: compile-time virtual memory allocation + */ +#ifndef ASM_FIXMAP_H +#define ASM_FIXMAP_H + +#include +#include +#include + +#include + +#define FIXMAP_ADDR(n) (FIXMAP_BASE + (n) * PAGE_SIZE) + +/* Fixmap slots */ +#define FIX_PMAP_BEGIN (0) /* Start of PMAP */ +#define FIX_PMAP_END (FIX_PMAP_BEGIN + NUM_FIX_PMAP - 1) /* End of PMAP */ +#define FIX_MISC (FIX_PMAP_END + 1) /* Ephemeral mappings of hardware */ + +#define FIX_LAST FIX_MISC + +#define FIXADDR_START FIXMAP_ADDR(0) +#define FIXADDR_TOP FIXMAP_ADDR(FIX_LAST + 1) + +#ifndef __ASSEMBLY__ + +/* + * Direct access to xen_fixmap[] should only happen when {set, + * clear}_fixmap() is unusable (e.g. where we would end up to + * recursively call the helpers). + */ +extern pte_t xen_fixmap[]; + +#define fix_to_virt(slot) ((void *)FIXMAP_ADDR(slot)) + +static inline unsigned int virt_to_fix(vaddr_t vaddr) +{ + BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START); + + return ((vaddr - FIXADDR_START) >> PAGE_SHIFT); +} + +#endif /* __ASSEMBLY__ */ + +#endif /* ASM_FIXMAP_H */ diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h index 25af9e1aaa..a0bdc2bc3a 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -255,4 +255,6 @@ static inline unsigned int arch_get_dma_bitsize(void) return 32; /* TODO */ } +void setup_fixmap_mappings(void); + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm/page.h index c831e16417..d4a5009823 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -81,6 +82,18 @@ static inline void flush_page_to_ram(unsigned long mfn, bool sync_icache) BUG_ON("unimplemented"); } +/* Write a pagetable entry. */ +static inline void write_pte(pte_t *p, pte_t pte) +{ + write_atomic(p, pte); +} + +/* Read a pagetable entry. */ +static inline pte_t read_pte(const pte_t *p) +{ + return read_atomic(p); +} + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PAGE_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 7d09e781bf..b8ff91cf4e 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,9 @@ stage1_pgtbl_root[PAGETABLE_ENTRIES]; pte_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) stage1_pgtbl_nonroot[PGTBL_INITIAL_COUNT * PAGETABLE_ENTRIES]; +pte_t __section(".bss.page_aligned") __aligned(PAGE_SIZE) +xen_fixmap[PAGETABLE_ENTRIES]; + #define HANDLE_PGTBL(curr_lvl_num) \ index = pt_index(curr_lvl_num, page_addr); \ if ( pte_is_valid(pgtbl[index]) ) \ @@ -191,6 +195,45 @@ static bool __init check_pgtbl_mode_support(struct mmu_desc *mmu_desc, return is_mode_supported; } +void __init setup_fixmap_mappings(void) +{ + pte_t *pte, tmp; + unsigned int i; + + BUILD_BUG_ON(FIX_LAST >= PAGETABLE_ENTRIES); + + pte = &stage1_pgtbl_root[pt_index(HYP_PT_ROOT_LEVEL, FIXMAP_ADDR(0))]; + + /* + * In RISC-V page table levels are numbered from Lx to L0 where + * x is the highest page table level for currect MMU mode ( for example, + * for Sv39 has 3 page tables so the x = 2 (L2 -> L1 -> L0) ). + * + * In this cycle we want to find L1 page table because as L0 page table + * xen_fixmap[] will be used. + */ + for ( i = HYP_PT_ROOT_LEVEL; i-- > 1; ) + { + BUG_ON(!pte_is_valid(*pte)); + + pte = (pte_t *)LOAD_TO_LINK(pte_to_paddr(*pte)); + pte = &pte[pt_index(i, FIXMAP_ADDR(0))]; + } + + BUG_ON(pte_is_valid(*pte)); + + tmp = paddr_to_pte(LINK_TO_LOAD((unsigned long)&xen_fixmap), PTE_TABLE); + write_pte(pte, tmp); + + RISCV_FENCE(rw, rw); + sfence_vma(); + + /* + * We only need the zeroeth table allocated, but not the PTEs set, because + * set_fixmap() will set them on the fly. + */ +} + /* * setup_initial_pagetables: * diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 97c599db44..82c5752da1 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -47,6 +47,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, test_macros_from_bug_h(); #endif + setup_fixmap_mappings(); + printk("All set up\n"); machine_halt(); diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S index 070b19d915..7a683f6065 100644 --- a/xen/arch/riscv/xen.lds.S +++ b/xen/arch/riscv/xen.lds.S @@ -181,6 +181,6 @@ ASSERT(!SIZEOF(.got.plt), ".got.plt non-empty") * Changing the size of Xen binary can require an update of * PGTBL_INITIAL_COUNT. */ -ASSERT(_end - _start <= MB(2), "Xen too large for early-boot assumptions") +ASSERT(_end - _start <= XEN_VIRT_SIZE, "Xen too large for early-boot assumptions") ASSERT(_ident_end - _ident_start <= IDENT_AREA_SIZE, "identity region is too big"); From patchwork Fri Sep 13 15:57:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13803798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0221DFC6165 for ; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5365f9038e3sm2348008e87.187.2024.09.13.08.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 08:58:11 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fb168103-71e8-11ef-99a2-01e77a169b0f DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726243092; x=1726847892; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6wLpSt/8koaeqq1K4FjJlAX3EhdAS4yEGyLGe6Cxffc=; b=H3MD+IWk45sh3Ilvj6SQpqSkcxleQBLOJK2IBZT0F5mxk0Z2tACsNg958OPv4xxBuK TfPoIzEwmrH8cCotQ8nkjBu2ISBC27WUEfnbLO+bgXx0oCUGbq44+jHNmyGWwmN7ZblX y7mr2rEYC/4kFWnjdwQg6ObkzcxiFErQNlE3xdOhyVRLJGvCdYN6RW2FGxy7w2eoX3uj DY34OTQ03cvZ+RKk+r5cQew/c/9bvdoHhdKNZEIqlrnXpYYTu4jnOdwnAD2la7Nzv5Y4 52ltYFpQijZJvpsRBVypnAADfYIFoGwFfwqwGSMu3JYbRK1K4R4dh1abkYBbByWJN9Le QkBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726243092; x=1726847892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6wLpSt/8koaeqq1K4FjJlAX3EhdAS4yEGyLGe6Cxffc=; b=HP1dBN7DHaw17aOsFdGiLNFK04F3u0N4am2sMCDjuLssGKZg8iZDOolDXON7Pmzazt A3x2FApISpPG4WEFLomdMJjOjzn+qwD5nwo4XWr6vxrGsqalhBJgQPd5jYA3l6T06X7M iEruVhAgsmo6T41Zq9xmw1tUyDxUEdUZ1jufY9l6u2xAf9G+UfdbG4OipXaJpv0Vw5aX uQyIbbNcX7Z64Hno2VNoVSp18laz3llI2kXaCSXB9xigwec3nSZmwRUKXDax5lw4WQwJ cqlKdvvvODwP63gm4WktiCGjBC7wX3CwoOos8vwO4R98OcHgjx+7URy+O9pYqpwx5+Ru evIA== X-Gm-Message-State: AOJu0Yx0xFTmrucU9yduHAc1E7PTD+RxQugeEPAC0rj7ZnEIBisBWnXp x4MjQM5GZ6PUranYvLUfMyjsVWI+GidbyTun3AG1RAq3cHoXBTQlCBwsYA== X-Google-Smtp-Source: AGHT+IECkC1kpArbtqWjZjtYRYmR9uQeuBXKAswFM1s/35hxWEXKFcXIzuhx3oTgNhgshdsl8I0kPg== X-Received: by 2002:a05:6512:3b0b:b0:52c:dfa0:dca0 with SMTP id 2adb3069b0e04-5367ff24f98mr2157905e87.43.1726243092038; Fri, 13 Sep 2024 08:58:12 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v7 4/8] xen/riscv: introduce asm/pmap.h header Date: Fri, 13 Sep 2024 17:57:42 +0200 Message-ID: X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Introduce arch_pmap_{un}map functions and select HAS_PMAP for CONFIG_RISCV. Add pte_from_mfn() for use in arch_pmap_map(). Introduce flush_xen_tlb_one_local() and use it in arch_pmap_{un}map(). Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in V6-V7: - No changes ( only rebase ) --- Changes in V5: - Add Reviewed-by: Jan Beulich . - Fix a typo in "Changes in V4": - "drop flush_xen_tlb_range_va_local() as it isn't used in this patch" -> "drop flush_xen_tlb_range_va() as it isn't used in this patch" - "s/flush_xen_tlb_range_va_local/flush_tlb_range_va_local" -> "s/flush_xen_tlb_one_local/flush_tlb_one_local" --- Changes in V4: - mark arch_pmap_{un}map() as __init: documentation purpose and a necessary (but not sufficient) condition here, to validly use local TLB flushes only. - add flush_xen_tlb_one_local() to arch_pmap_map() as absense of "negative" TLB entrues will be guaranted only in the case when Svvptc extension is present. - s/mfn_from_pte/pte_from_mfn - drop mfn_to_xen_entry() as pte_from_mfn() does the same thing - add flags argument to pte_from_mfn(). - update the commit message. - drop flush_xen_tlb_range_va() as it isn't used in this patch - s/flush_xen_tlb_one_local/flush_tlb_one_local --- Changes in V3: - rename argument of function mfn_to_xen_entry(..., attr -> flags ). - update the code of mfn_to_xen_entry() to use flags argument. - add blank in mfn_from_pte() in return line. - introduce flush_xen_tlb_range_va_local() and use it inside arch_pmap_{un}map(). - s/__ASM_PMAP_H__/ASM_PMAP_H - add SPDX-License-Identifier: GPL-2.0 --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/include/asm/flushtlb.h | 6 +++++ xen/arch/riscv/include/asm/page.h | 6 +++++ xen/arch/riscv/include/asm/pmap.h | 36 +++++++++++++++++++++++++++ 4 files changed, 49 insertions(+) create mode 100644 xen/arch/riscv/include/asm/pmap.h diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index 7a113c7774..1858004676 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -3,6 +3,7 @@ config RISCV select FUNCTION_ALIGNMENT_16B select GENERIC_BUG_FRAME select HAS_DEVICE_TREE + select HAS_PMAP select HAS_VMAP config RISCV_64 diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include/asm/flushtlb.h index 7ce32bea0b..f4a735fd6c 100644 --- a/xen/arch/riscv/include/asm/flushtlb.h +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -5,6 +5,12 @@ #include #include +/* Flush TLB of local processor for address va. */ +static inline void flush_tlb_one_local(vaddr_t va) +{ + asm volatile ( "sfence.vma %0" :: "r" (va) : "memory" ); +} + /* * Filter the given set of CPUs, removing those that definitely flushed their * TLB since @page_timestamp. diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm/page.h index d4a5009823..eb79cb9409 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -94,6 +94,12 @@ static inline pte_t read_pte(const pte_t *p) return read_atomic(p); } +static inline pte_t pte_from_mfn(mfn_t mfn, unsigned int flags) +{ + unsigned long pte = (mfn_x(mfn) << PTE_PPN_SHIFT) | flags; + return (pte_t){ .pte = pte }; +} + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PAGE_H */ diff --git a/xen/arch/riscv/include/asm/pmap.h b/xen/arch/riscv/include/asm/pmap.h new file mode 100644 index 0000000000..60065c996f --- /dev/null +++ b/xen/arch/riscv/include/asm/pmap.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef ASM_PMAP_H +#define ASM_PMAP_H + +#include +#include +#include +#include + +#include +#include +#include + +static inline void __init arch_pmap_map(unsigned int slot, mfn_t mfn) +{ + pte_t *entry = &xen_fixmap[slot]; + pte_t pte; + + ASSERT(!pte_is_valid(*entry)); + + pte = pte_from_mfn(mfn, PAGE_HYPERVISOR_RW); + write_pte(entry, pte); + + flush_tlb_one_local(FIXMAP_ADDR(slot)); +} + +static inline void __init arch_pmap_unmap(unsigned int slot) +{ + pte_t pte = {}; + + write_pte(&xen_fixmap[slot], pte); + + flush_tlb_one_local(FIXMAP_ADDR(slot)); +} + +#endif /* ASM_PMAP_H */ From patchwork Fri Sep 13 15:57:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13803795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3B96FA375E for ; Fri, 13 Sep 2024 15:58:26 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.798300.1208500 (Exim 4.92) (envelope-from ) id 1sp8gb-0000ws-2c; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5365f9038e3sm2348008e87.187.2024.09.13.08.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 08:58:12 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fb8afc8a-71e8-11ef-a0b5-8be0dac302b0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726243093; x=1726847893; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CXFJidxQDiGaEfKB7fqlEAp0impdm4D9++KlmnlKdiI=; b=KAqP3CDjW0YEJLNJPAiuUtjekAKPVp3IMjmo7xw5Ln2iV6YeFXWR+FrxHYtQWNb2Bd 67NxcuYSV5yiAsS3DOERDukFE6EOZixRIFamh4NdFND22213zCGNoGPz0sEp9bd7ZUOu DALyvadaTM401GoFn6DnABie1HZ/50SnjMd/4/hFc2WAQwVQFHUpnfV1SJmhpE1gdI1S 4H3iG506lpmlM30kBl3B7o2lIgRvjHRFcqHLKtJVKxHgq/fB2WPEtKUMYP7SjeIkXsOS 9NDI/knN+KeSq1QMrnjsUL8rQ44GniyxoEx4Pb3WEVIFBA4RWWzGOz4pTG3Kg0hWK3so jCaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726243093; x=1726847893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CXFJidxQDiGaEfKB7fqlEAp0impdm4D9++KlmnlKdiI=; b=qeeOlQP8auj5j0+mMPCS2Yik6DOrhksWkb7ulfyNfmsPPYGVmp+ff7tyfADeEgsI+g nwoMjf4bR2xExdBHzqHfJCifL3XclZJvjyHmg+P/lxiBKTLtEdEdRGq3GzvvRs2wEHa8 0kvjAybNfXmQB6YZa4V7rSAZJW3oqsu+U5XnJD0n9EBc9zjo5RRiIPf+ErZABv36fKA3 AzJauU0ThWedBgQEqAEo/d9Gjh7rcCUshO5aWb1Qmhz3fNaxUX2Z7xEHZq6ITJwukBYX vJJzxPD5v1cUhKmgQHZncH3dH+voOjcMozIHNGaaybcmMlNK1qAv09sW7/Uah9TGaDaB BBjw== X-Gm-Message-State: AOJu0YxIrBDyMLA/01lAH92J43zNC0qBeln9FQVS2OjhO8FiDt+H49nv paV2uno4Qzux3n/VB13ei/1LRbboXeeOfxNrKTm0ak3Exg+ZEBqSsiXY7w== X-Google-Smtp-Source: AGHT+IFazuaiIX8u+eHhhOpdKaEbYkWsDZN2m8MKCjF1Ya3Gth7BeSKFeVKKQs4tc86qJUAs5gmXPQ== X-Received: by 2002:a05:6512:2309:b0:535:6965:be19 with SMTP id 2adb3069b0e04-5367ff32b8emr2258851e87.56.1726243092956; Fri, 13 Sep 2024 08:58:12 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v7 5/8] xen/riscv: introduce functionality to work with CPU info Date: Fri, 13 Sep 2024 17:57:43 +0200 Message-ID: <461a246e3a54345578556821f2c7dbf01e348a05.1726242605.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Introduce struct pcpu_info to store pCPU-related information. Initially, it includes only processor_id and hart id, but it will be extended to include guest CPU information and temporary variables for saving/restoring vCPU registers. Add set_processor_id() function to set processor_id stored in pcpu_info. Define smp_processor_id() to provide accurate information, replacing the previous "dummy" value of 0. Initialize tp registers to point to pcpu_info[0]. Set processor_id to 0 for logical CPU 0 and store the physical CPU ID in pcpu_info[0]. Introduce helpers for getting hart_id ( physical CPU id in RISC-V terms ) from Xen CPU id. Removing of inclusion leads to the following compilation error: common/keyhandler.c: In function 'dump_registers': common/keyhandler.c:200:13: error: implicit declaration of function 'cpu_relax' [-Werror=implicit-function-declaration] 200 | cpu_relax(); Signed-off-by: Oleksii Kurochko --- Changes in V7: - remove get_processor_id(). - move definition of tp variable, struct pcpu_info, pcpu_info[], set_processor_id() and smp_processor_id() from asm/processor.h to asm/current.h. (1) - change xen/lib.h to xen/bug.h in current.h, for BUG_ON() it is enough xen/bug.h - update BUG_ON() from BUG_ON(id > (NR_CPUS-1)) to BUG_ON(id >= NR_CPUS) in smp_processor_id(). - update the comment above cpuid_to_hartid(). - refactor setup_tp() to the way suggested by Jan B. - add helpers to get and set cpuid to hartid. - update the commit message: add information that removing of from leads to compilation error. --- Changes in V6: - update the commit message ( drop outdated information ). - s/FIXME commit/FIXME comment in "changes in V5". - code style fixes. - refactoring of smp_processor_id() and fix BUG_ON() condition inside it. - change "mv a0,x0" to "li a0, 0". - add __cacheline_aligned to the struct pcpu_info. - drop smp_set_bootcpu_id() and smpboot.c as it has only smp_set_bootcpu_id() defined at the moment. - re-write setup_tp() to assembler. --- Changes in V5: - add hart_id to pcpu_info; - add comments to pcpu_info members. - define INVALID_HARTID as ULONG_MAX as mhart_id register has MXLEN which is equal to 32 for RV-32 and 64 for RV-64. - add hart_id to pcpu_info structure. - drop cpuid_to_hartid_map[] and use pcpu_info[] for the same purpose. - introduce new function setup_tp(cpuid). - add the FIXME comment on top of pcpu_info[]. - setup TP register before start_xen() being called. - update the commit message. - change "commit message" to "comment" in "Changes in V4" in "update the comment above the code of TP..." --- Changes in V4: - wrap id with () inside set_processor_id(). - code style fixes - update BUG_ON(id > NR_CPUS) in smp_processor_id() and drop the comment above BUG_ON(). - s/__cpuid_to_hartid_map/cpuid_to_hartid_map - s/cpuid_to_hartid_map/cpuid_to_harti ( here cpuid_to_hartid_map is the name of the macros ). - update the comment above the code of TP register initialization in start_xen(). - s/smp_setup_processor_id/smp_setup_bootcpu_id - update the commit message. - cleanup headers which are included in --- Changes in V3: - new patch. --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/current.h | 27 +++++++++++++++++++++++++- xen/arch/riscv/include/asm/processor.h | 3 --- xen/arch/riscv/include/asm/smp.h | 18 +++++++++++++++++ xen/arch/riscv/riscv64/asm-offsets.c | 3 +++ xen/arch/riscv/riscv64/head.S | 14 +++++++++++++ xen/arch/riscv/setup.c | 5 +++++ xen/arch/riscv/smp.c | 15 ++++++++++++++ 8 files changed, 82 insertions(+), 4 deletions(-) create mode 100644 xen/arch/riscv/smp.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index d192be7b55..6832549133 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_RISCV_64) += riscv64/ obj-y += sbi.o obj-y += setup.o obj-y += shutdown.o +obj-y += smp.o obj-y += stubs.o obj-y += traps.o obj-y += vm_event.o diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/asm/current.h index aedb6dc732..6f1ec4e190 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -3,12 +3,37 @@ #ifndef __ASM_CURRENT_H #define __ASM_CURRENT_H -#include +#include +#include #include + #include #ifndef __ASSEMBLY__ +register struct pcpu_info *tp asm ( "tp" ); + +struct pcpu_info { + unsigned int processor_id; /* Xen CPU id */ + unsigned long hart_id; /* physical CPU id */ +} __cacheline_aligned; + +/* tp points to one of these */ +extern struct pcpu_info pcpu_info[NR_CPUS]; + +#define set_processor_id(id) do { \ + tp->processor_id = (id); \ +} while (0) + +static inline unsigned int smp_processor_id(void) +{ + unsigned int id = tp->processor_id; + + BUG_ON(id >= NR_CPUS); + + return id; +} + /* Which VCPU is "current" on this PCPU. */ DECLARE_PER_CPU(struct vcpu *, curr_vcpu); diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/include/asm/processor.h index 3ae164c265..e42b353b4c 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -12,9 +12,6 @@ #ifndef __ASSEMBLY__ -/* TODO: need to be implemeted */ -#define smp_processor_id() 0 - /* On stack VCPU state */ struct cpu_user_regs { diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/smp.h index b1ea91b1eb..7cb8b86144 100644 --- a/xen/arch/riscv/include/asm/smp.h +++ b/xen/arch/riscv/include/asm/smp.h @@ -5,6 +5,8 @@ #include #include +#include + DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); @@ -14,6 +16,22 @@ DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); */ #define park_offline_cpus false +/* + * Mapping between Xen logical cpu index and hartid. + */ +static inline unsigned long cpuid_to_hartid(unsigned long cpuid) +{ + return pcpu_info[cpuid].hart_id; +} + +static inline void map_cpuid_to_hartid(unsigned long cpuid, + unsigned long hartid) +{ + pcpu_info[cpuid].hart_id = hartid; +} + +void setup_tp(unsigned int cpuid); + #endif /* diff --git a/xen/arch/riscv/riscv64/asm-offsets.c b/xen/arch/riscv/riscv64/asm-offsets.c index 9f663b9510..3b5daf3b36 100644 --- a/xen/arch/riscv/riscv64/asm-offsets.c +++ b/xen/arch/riscv/riscv64/asm-offsets.c @@ -1,5 +1,6 @@ #define COMPILE_OFFSETS +#include #include #include @@ -50,4 +51,6 @@ void asm_offsets(void) OFFSET(CPU_USER_REGS_SSTATUS, struct cpu_user_regs, sstatus); OFFSET(CPU_USER_REGS_PREGS, struct cpu_user_regs, pregs); BLANK(); + DEFINE(PCPU_INFO_SIZE, sizeof(struct pcpu_info)); + BLANK(); } diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S index 3261e9fce8..2a1b3dad91 100644 --- a/xen/arch/riscv/riscv64/head.S +++ b/xen/arch/riscv/riscv64/head.S @@ -1,4 +1,5 @@ #include +#include #include .section .text.header, "ax", %progbits @@ -55,6 +56,10 @@ FUNC(start) */ jal reset_stack + /* Xen's boot cpu id is equal to 0 so setup TP register for it */ + li a0, 0 + jal setup_tp + /* restore hart_id ( bootcpu_id ) and dtb address */ mv a0, s0 mv a1, s1 @@ -72,6 +77,15 @@ FUNC(reset_stack) ret END(reset_stack) +/* void setup_tp(unsigned int xen_cpuid); */ +FUNC(setup_tp) + la t0, pcpu_info + li t1, PCPU_INFO_SIZE + mul t1, a0, t1 + add tp, t0, t1 + ret +END(setup_tp) + .section .text.ident, "ax", %progbits FUNC(turn_on_mmu) diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 82c5752da1..0fd6c37b61 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -9,6 +9,7 @@ #include #include +#include #include void arch_get_xen_caps(xen_capabilities_info_t *info) @@ -41,6 +42,10 @@ void __init noreturn start_xen(unsigned long bootcpu_id, { remove_identity_mapping(); + set_processor_id(0); + + map_cpuid_to_hartid(0, bootcpu_id); + trap_init(); #ifdef CONFIG_SELF_TESTS diff --git a/xen/arch/riscv/smp.c b/xen/arch/riscv/smp.c new file mode 100644 index 0000000000..4ca6a4e892 --- /dev/null +++ b/xen/arch/riscv/smp.c @@ -0,0 +1,15 @@ +#include + +/* + * FIXME: make pcpu_info[] dynamically allocated when necessary + * functionality will be ready + */ +/* + * tp points to one of these per cpu. + * + * hart_id would be valid (no matter which value) if its + * processor_id field is valid (less than NR_CPUS). + */ +struct pcpu_info pcpu_info[NR_CPUS] = { [0 ... NR_CPUS - 1] = { + .processor_id = NR_CPUS, +}}; From patchwork Fri Sep 13 15:57:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13803800 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3520CFA375B for ; Fri, 13 Sep 2024 15:58:27 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.798302.1208515 (Exim 4.92) (envelope-from ) id 1sp8gb-0001GK-VH; Fri, 13 Sep 2024 15:58:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 798302.1208515; Fri, 13 Sep 2024 15:58:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8gb-0001Dm-On; Fri, 13 Sep 2024 15:58:17 +0000 Received: by outflank-mailman (input) for mailman id 798302; Fri, 13 Sep 2024 15:58:16 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8gZ-0000A5-Tn for xen-devel@lists.xenproject.org; Fri, 13 Sep 2024 15:58:16 +0000 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [2a00:1450:4864:20::12c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fc179766-71e8-11ef-a0b5-8be0dac302b0; Fri, 13 Sep 2024 17:58:14 +0200 (CEST) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-53654dbde59so3215273e87.1 for ; Fri, 13 Sep 2024 08:58:14 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5365f9038e3sm2348008e87.187.2024.09.13.08.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 08:58:13 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fc179766-71e8-11ef-a0b5-8be0dac302b0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726243094; x=1726847894; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w3WDspjii0VAltRM3qKmp7xdoXVUt03Mt88o9yu2SuU=; b=eSvrYwSDnk+niRAMDJBMjJ1pv5ffSMBNIfLheInhyzLESUYm//9w0fyTrnr0S58wCx ZGLnbKpd2eP2Z1IrFYdDbwGrMAYN7bMI3pb7XwTGnosgogjTJZyJvtE+++eGfnaleC2n G/8mPtWtnC1ofaUzBUc10zpGMtoTfPa/bX417yqV6eVlk92WGktkznUdwR5enX2QuCJS W7bDU/UaDAMvZmBLpOEPQRoO72N9Kc5AiqVHPgbRlaYlRwpu2zmFB5qEGZPQDYfbe7f+ ydkaK71Uj5QrcmfQJI0+VfiZsEpq5lTxZSl+lz8Z52ApwwSj125SnZcD0FCcdhmGA4Al GsIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726243094; x=1726847894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w3WDspjii0VAltRM3qKmp7xdoXVUt03Mt88o9yu2SuU=; b=qkC5Fv5trSsh9olb234jADMIlYDbxpAZNEj5dMNjHcRdzgU7hgSj245n9DVPYTBtU5 u319kg6/8U6NzxO2q4YzsYyMkEjfjKQ9T4qrbFkKBZvoC2yU4cSSA/zJM3GBno8D4sx/ 3XrPYi9Iq4hte79ZP5dl7u0C5faEfIAI+HhQg0FujRM0IACucsR8qFhsdsZ7RA7SXWg2 BVpA89D0NSNgWYyHhnu31zXlDlQfAdO8oAabWammsUsaMVFCsgDVK8eGCIWRsdbe+Np8 fiCtn1WKvAl9bRXsNLdmb8RDEMmp+Z51g8O4VfTq1UL2k5kVHBZwQIcG4zrAHiliaCBs UwPA== X-Gm-Message-State: AOJu0Yzef0v5GxKESBpq5x8Vbrv2ugqTT342sd3Tty12IF6eAN/F+R50 jZS+62LVLjLOPCsKrrPPIW633bNJ5i2BmzUeVvf2UC/Tw3jjKisyy56czg== X-Google-Smtp-Source: AGHT+IEV22gr645i54OwDfW4/fkvAvM/YGHI09du8oRmJzzMSGy+jufcsMNcBBxReOI/Hm3WhWmdVA== X-Received: by 2002:a05:6512:3d04:b0:52c:ccb3:71f7 with SMTP id 2adb3069b0e04-53679075adcmr2385565e87.9.1726243093846; Fri, 13 Sep 2024 08:58:13 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v7 6/8] xen/riscv: introduce and initialize SBI RFENCE extension Date: Fri, 13 Sep 2024 17:57:44 +0200 Message-ID: <699cd9930bd49183ba8eab767030ef0c057b14c3.1726242605.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Introduce functions to work with the SBI RFENCE extension for issuing various fence operations to remote CPUs. Add the sbi_init() function along with auxiliary functions and macro definitions for proper initialization and checking the availability of SBI extensions. Currently, this is implemented only for RFENCE. Introduce sbi_remote_sfence_vma() to send SFENCE_VMA instructions to a set of target HARTs. This will support the implementation of flush_xen_tlb_range_va(). Integrate __sbi_rfence_v02 from Linux kernel 6.6.0-rc4 with minimal modifications: - Adapt to Xen code style. - Use cpuid_to_hartid() instead of cpuid_to_hartid_map[]. - Update BIT(...) to BIT(..., UL). - Rename __sbi_rfence_v02_call to sbi_rfence_v02_real and remove the unused arg5. - Handle NULL cpu_mask to execute rfence on all CPUs by calling sbi_rfence_v02_real(..., 0UL, -1UL,...) instead of creating hmask. - change type for start_addr and size to vaddr_t and size_t. - Add an explanatory comment about when batching can and cannot occur, and why batching happens in the first place. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V7: - fix some comment identations. - put as much as possible parameters on a line for sbi_remote_sfence_vma. --- Changes in V6: - align with zeros the definition of SBI_SPEC_VERSION_MINOR_MASK. - drop fallthrough in sbi_err_map_xen_errno() between 'case SBI_ERR_FAILURE' and default. - update return type of sbi_{major,minor}_version() to unsigned int. - move BUG_ON(ret.value < 0); inside if ( !ret.error ) in sbi_ext_base_func(). - print fid as %#lx instead of %lu. - print ret.error instead of what sbi_err_map_xen_errno() as it may lose information. - drop unrelated information in the comment of the for_each_cpu cycle in sbi_rfence_v02(). - small refactoring in sbi_rfence_v02(): making uniform path for returning result variable. - rename start_addr argument to start for sbi_remote_sfence_vma(). - use sbi_err_map_xen_errno() inside sbi_probe_extension() to return an error value instead of -EOPNOTSUPP. - s/unsigned long start/vaddr_t start - s/unsgined long size/size_t size - update the commit message. --- Changes in V5: - update the comment for sbi_has_rfence(). - update the comment for sbi_remote_sfence_vma(). - update the prototype of sbi_remote_sfence_vma() and declare cpu_mask argument as pointer to const. - use MASK_EXTR() for sbi_{major, minor}_version(). - redefine SBI_SPEC_VERSION_MAJOR_MASK as 0x7F000000 - drop SBI_SPEC_VERSION_MAJOR_SHIFT as unneeded. - add BUG_ON(ret.value < 0) inside sbi_ext_base_func() to be sure that ret.value is always >= 0 as SBI spec explicitly doesn't say that. - s/__sbi_rfence_v02_real/sbi_rfence_v02_real - s/__sbi_rfence_v02/sbi_rfence_v02 - s/__sbi_rfence/sbi_rfence - fold cases inside sbi_rfence_v02_real() - mark sbi_rfence_v02 with cf_check. - code style fixes in sbi_rfence_v02(). - add the comment with explanation of algorithm used in sbi_rfence_v02(). - use __ro_after_init for sbi_rfence variable. - add ASSERT(sbi_rfebce) inside sbi_remote_sfence_vma to be sure that it is not NULL. - drop local variable ret inside sbi_init() and init sbi_spec_version directly by return value of sbi_get_spec_version() as this function should always be must always succeed. - add the comment above sbi_get_spec_version(). - add BUG_ON for sbi_fw_id and sbi_fw_version() to be sure that they have correct values. - make sbi_fw_id, sbi_fw_version as local because they are used only once for printk(). - s/veriosn/version - drop BUG_ON("At the moment flush_xen_tlb_range_va() uses SBI rfence...") as now we have ASSERT() in the flace where sbi_rfence is actually used. - update the commit message. - s/BUG_ON("Ooops. SBI spec version 0.1 detected. Need to add support")/panic("Ooops. SBI ..."); --- Changes in V4: - update the commit message. - code style fixes - update return type of sbi_has_rfence() from int to bool and drop conditional operator inside implementation. - Update mapping of SBI_ERR_FAILURE in sbi_err_map_xen_errno(). - Update return type of sbi_spec_is_0_1() and drop conditional operator inside implementation. - s/0x%lx/%#lx - update the comment above declaration of sbi_remote_sfence_vma() with more detailed explanation what the function does. - update prototype of sbi_remote_sfence_vma(). Now it receives cpumask_t and returns int. - refactor __sbi_rfence_v02() take from the Linux kernel as it takes into account a case that hart id could be from different hbase. For example, the case when hart IDs are the following 0, 3, 65, 2. Or the case when hart IDs are unsorted: 0 3 1 2. - drop sbi_cpumask_to_hartmask() as it is not needed anymore - Update the prototype of sbi_remote_sfence_vma() and implemntation accordingly to the fact it returns 'int'. - s/flush_xen_tlb_one_local/flush_tlb_one_local --- Changes in V3: - new patch. --- xen/arch/riscv/include/asm/sbi.h | 62 +++++++ xen/arch/riscv/sbi.c | 273 ++++++++++++++++++++++++++++++- xen/arch/riscv/setup.c | 3 + 3 files changed, 337 insertions(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/sbi.h index 4d72a2295e..5947fed779 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -12,9 +12,42 @@ #ifndef __ASM_RISCV_SBI_H__ #define __ASM_RISCV_SBI_H__ +#include + #define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 #define SBI_EXT_0_1_SHUTDOWN 0x8 +#define SBI_EXT_BASE 0x10 +#define SBI_EXT_RFENCE 0x52464E43 + +/* SBI function IDs for BASE extension */ +#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 +#define SBI_EXT_BASE_GET_IMP_ID 0x1 +#define SBI_EXT_BASE_GET_IMP_VERSION 0x2 +#define SBI_EXT_BASE_PROBE_EXT 0x3 + +/* SBI function IDs for RFENCE extension */ +#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1 +#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x3 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID 0x4 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5 +#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6 + +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f000000 +#define SBI_SPEC_VERSION_MINOR_MASK 0x00ffffff + +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILURE (-1) +#define SBI_ERR_NOT_SUPPORTED (-2) +#define SBI_ERR_INVALID_PARAM (-3) +#define SBI_ERR_DENIED (-4) +#define SBI_ERR_INVALID_ADDRESS (-5) + +#define SBI_SPEC_VERSION_DEFAULT 0x1 + struct sbiret { long error; long value; @@ -34,4 +67,33 @@ void sbi_console_putchar(int ch); void sbi_shutdown(void); +/* + * Check underlying SBI implementation has RFENCE + * + * @return true for supported AND false for not-supported + */ +bool sbi_has_rfence(void); + +/* + * Instructs the remote harts to execute one or more SFENCE.VMA + * instructions, covering the range of virtual addresses between + * [start_addr, start_addr + size). + * + * Returns 0 if IPI was sent to all the targeted harts successfully + * or negative value if start_addr or size is not valid. + * + * @hart_mask a cpu mask containing all the target harts. + * @param start virtual address start + * @param size virtual address range size + */ +int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, + size_t size); + +/* + * Initialize SBI library + * + * @return 0 on success, otherwise negative errno on failure + */ +int sbi_init(void); + #endif /* __ASM_RISCV_SBI_H__ */ diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index c7984344bc..4209520389 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -5,13 +5,26 @@ * (anup.patel@wdc.com). * * Modified by Bobby Eshleman (bobby.eshleman@gmail.com). + * Modified by Oleksii Kurochko (oleksii.kurochko@gmail.com). * * Copyright (c) 2019 Western Digital Corporation or its affiliates. - * Copyright (c) 2021-2023 Vates SAS. + * Copyright (c) 2021-2024 Vates SAS. */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include #include +static unsigned long __ro_after_init sbi_spec_version = SBI_SPEC_VERSION_DEFAULT; + struct sbiret sbi_ecall(unsigned long ext, unsigned long fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, @@ -38,6 +51,26 @@ struct sbiret sbi_ecall(unsigned long ext, unsigned long fid, return ret; } +static int sbi_err_map_xen_errno(int err) +{ + switch ( err ) + { + case SBI_SUCCESS: + return 0; + case SBI_ERR_DENIED: + return -EACCES; + case SBI_ERR_INVALID_PARAM: + return -EINVAL; + case SBI_ERR_INVALID_ADDRESS: + return -EFAULT; + case SBI_ERR_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SBI_ERR_FAILURE: + default: + return -ENOSYS; + }; +} + void sbi_console_putchar(int ch) { sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0); @@ -47,3 +80,241 @@ void sbi_shutdown(void) { sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); } + +static unsigned int sbi_major_version(void) +{ + return MASK_EXTR(sbi_spec_version, SBI_SPEC_VERSION_MAJOR_MASK); +} + +static unsigned int sbi_minor_version(void) +{ + return MASK_EXTR(sbi_spec_version, SBI_SPEC_VERSION_MINOR_MASK); +} + +static long sbi_ext_base_func(long fid) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0); + + if ( !ret.error ) + { + /* + * I wasn't able to find a case in the SBI spec where sbiret.value + * could be negative. + * + * Unfortunately, the spec does not specify the possible values of + * sbiret.value, but based on the description of the SBI function, + * ret.value >= 0 when sbiret.error = 0. SPI spec specify only + * possible value for sbiret.error (<= 0 whwere 0 is SBI_SUCCESS ). + * + * Just to be sure that SBI base extension functions one day won't + * start to return a negative value for sbiret.value when + * sbiret.error < 0 BUG_ON() is added. + */ + BUG_ON(ret.value < 0); + + return ret.value; + } + else + return ret.error; +} + +static int sbi_rfence_v02_real(unsigned long fid, + unsigned long hmask, unsigned long hbase, + vaddr_t start, size_t size, + unsigned long arg4) +{ + struct sbiret ret = {0}; + int result = 0; + + switch ( fid ) + { + case SBI_EXT_RFENCE_REMOTE_FENCE_I: + ret = sbi_ecall(SBI_EXT_RFENCE, fid, hmask, hbase, + 0, 0, 0, 0); + break; + + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA: + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA: + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA: + ret = sbi_ecall(SBI_EXT_RFENCE, fid, hmask, hbase, + start, size, 0, 0); + break; + + case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID: + case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID: + case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID: + ret = sbi_ecall(SBI_EXT_RFENCE, fid, hmask, hbase, + start, size, arg4, 0); + break; + + default: + printk("%s: unknown function ID [%#lx]\n", + __func__, fid); + result = -EINVAL; + break; + }; + + if ( ret.error ) + { + result = sbi_err_map_xen_errno(ret.error); + printk("%s: hbase=%lu hmask=%#lx failed (error %ld)\n", + __func__, hbase, hmask, ret.error); + } + + return result; +} + +static int cf_check sbi_rfence_v02(unsigned long fid, + const cpumask_t *cpu_mask, + vaddr_t start, size_t size, + unsigned long arg4, unsigned long arg5) +{ + unsigned long hartid, cpuid, hmask = 0, hbase = 0, htop = 0; + int result = -EINVAL; + + /* + * hart_mask_base can be set to -1 to indicate that hart_mask can be + * ignored and all available harts must be considered. + */ + if ( !cpu_mask ) + return sbi_rfence_v02_real(fid, 0UL, -1UL, start, size, arg4); + + for_each_cpu ( cpuid, cpu_mask ) + { + /* + * Hart IDs might not necessarily be numbered contiguously in + * a multiprocessor system. + * + * This means that it is possible for the hart ID mapping to look like: + * 0, 1, 3, 65, 66, 69 + * In such cases, more than one call to sbi_rfence_v02_real() will be + * needed, as a single hmask can only cover sizeof(unsigned long) CPUs: + * 1. sbi_rfence_v02_real(hmask=0b1011, hbase=0) + * 2. sbi_rfence_v02_real(hmask=0b1011, hbase=65) + * + * The algorithm below tries to batch as many harts as possible before + * making an SBI call. However, batching may not always be possible. + * For example, consider the hart ID mapping: + * 0, 64, 1, 65, 2, 66 (1) + * + * Generally, batching is also possible for (1): + * First (0,1,2), then (64,65,66). + * It just requires a different approach and updates to the current + * algorithm. + */ + hartid = cpuid_to_hartid(cpuid); + if ( hmask ) + { + if ( hartid + BITS_PER_LONG <= htop || + hbase + BITS_PER_LONG <= hartid ) + { + result = sbi_rfence_v02_real(fid, hmask, hbase, + start, size, arg4); + hmask = 0; + if ( result ) + break; + } + else if ( hartid < hbase ) + { + /* shift the mask to fit lower hartid */ + hmask <<= hbase - hartid; + hbase = hartid; + } + } + + if ( !hmask ) + { + hbase = hartid; + htop = hartid; + } + else if ( hartid > htop ) + htop = hartid; + + hmask |= BIT(hartid - hbase, UL); + } + + if ( hmask ) + result = sbi_rfence_v02_real(fid, hmask, hbase, + start, size, arg4); + + return result; +} + +static int (* __ro_after_init sbi_rfence)(unsigned long fid, + const cpumask_t *cpu_mask, + vaddr_t start, + size_t size, + unsigned long arg4, + unsigned long arg5); + +int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, + size_t size) +{ + ASSERT(sbi_rfence); + + return sbi_rfence(SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, + cpu_mask, start, size, 0, 0); +} + +/* This function must always succeed. */ +#define sbi_get_spec_version() \ + sbi_ext_base_func(SBI_EXT_BASE_GET_SPEC_VERSION) + +#define sbi_get_firmware_id() \ + sbi_ext_base_func(SBI_EXT_BASE_GET_IMP_ID) + +#define sbi_get_firmware_version() \ + sbi_ext_base_func(SBI_EXT_BASE_GET_IMP_VERSION) + +int sbi_probe_extension(long extid) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid, + 0, 0, 0, 0, 0); + if ( !ret.error && ret.value ) + return ret.value; + + return sbi_err_map_xen_errno(ret.error); +} + +static bool sbi_spec_is_0_1(void) +{ + return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT); +} + +bool sbi_has_rfence(void) +{ + return (sbi_rfence != NULL); +} + +int __init sbi_init(void) +{ + sbi_spec_version = sbi_get_spec_version(); + + printk("SBI specification v%u.%u detected\n", + sbi_major_version(), sbi_minor_version()); + + if ( !sbi_spec_is_0_1() ) + { + long sbi_fw_id = sbi_get_firmware_id(); + long sbi_fw_version = sbi_get_firmware_version(); + + BUG_ON((sbi_fw_id < 0) || (sbi_fw_version < 0)); + + printk("SBI implementation ID=%#lx Version=%#lx\n", + sbi_fw_id, sbi_fw_version); + + if ( sbi_probe_extension(SBI_EXT_RFENCE) > 0 ) + { + sbi_rfence = sbi_rfence_v02; + printk("SBI v0.2 RFENCE extension detected\n"); + } + } + else + panic("Ooops. SBI spec version 0.1 detected. Need to add support"); + + return 0; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 0fd6c37b61..e73248c035 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -48,6 +49,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, trap_init(); + sbi_init(); + #ifdef CONFIG_SELF_TESTS test_macros_from_bug_h(); #endif From patchwork Fri Sep 13 15:57:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13803802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9EC3FA375E for ; Fri, 13 Sep 2024 15:58:48 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.798304.1208534 (Exim 4.92) (envelope-from ) id 1sp8gx-000321-B3; Fri, 13 Sep 2024 15:58:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 798304.1208534; Fri, 13 Sep 2024 15:58:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8gx-00031r-72; Fri, 13 Sep 2024 15:58:39 +0000 Received: by outflank-mailman (input) for mailman id 798304; Fri, 13 Sep 2024 15:58:38 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8gc-0000AA-8s for xen-devel@lists.xenproject.org; Fri, 13 Sep 2024 15:58:38 +0000 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [2a00:1450:4864:20::135]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id fcb3fabf-71e8-11ef-99a2-01e77a169b0f; Fri, 13 Sep 2024 17:58:15 +0200 (CEST) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-5356aa9a0afso1851079e87.2 for ; Fri, 13 Sep 2024 08:58:15 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5365f9038e3sm2348008e87.187.2024.09.13.08.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 08:58:14 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fcb3fabf-71e8-11ef-99a2-01e77a169b0f DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726243095; x=1726847895; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7tG9IHIE2XvixCfCqKHWu10gmiZ0roIKtRDnZVF0kH4=; b=VbaIXvEP8xqeMxOhxyMpc6D+0sPkgwHaFniRx5teVHd8w+z1EEf7Prfn/K5S80TjKd /jZyEUn174YZfQE0y5QiIruhP6dnIyiIFmXPfCFwXRpnJ5qm6FgbxNyk8oBx5fAmvb3g lfbmdBSFBYsHlqEDex5eULpkwD66w8KSTFQpTuSERMm2LjhQZmeNiB8dXI4ZaTB5nSUx 59TivTWLC+bnCGxk1+yJTQTE4kObFCRPwjBKkjK/3hj2woxhdVyh+A8h6vc70PO/lO6M nP2wUqqqYVijTXqIBpAoXPE7LTK47jNi2tbdYSFWYdtQun2KukKh4Do2dZxS8sbalGih sWgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726243095; x=1726847895; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7tG9IHIE2XvixCfCqKHWu10gmiZ0roIKtRDnZVF0kH4=; b=YHnXd81K/dGa92wOrump3S2i5uAfwhsui3rArCBl0qOE/dc6aaO1lL8wCLCWxyhjyu QUggu15oNtppvT2ldifeNFqM4BKWWalOaspPXyTvdd4oA0nQwst4FPl9wPc+rbRwz3H9 sMYLjLcml8NXBxPfC8mlCQmR8sbBrc1Q3Gy1eviDW/d/S7prStvaUtFehDzfhpc9DPAZ 6VW9jPaJwUuzzvH2rqrEU0QaeKNVMMvqu/fkfTpbUp4Nq6PTT9cfPGf03bkbZ3ulwvh0 R0ZqtS01hzqufg2nXTA8AECtKhglrHJOhqn9BEtpuX7dyMQQ+MvtvgWXeAP4QrKxD3MT 8K2g== X-Gm-Message-State: AOJu0YxG272vlT+y3DbHO24cL+mDVHkrgKtia98UFrEKwOHifQm7fK2a tW2nMlKUeshsKvNE7RvMVq8HvVxtgO0hBmz+q1WJ95bQHj8DTNhlBGumFw== X-Google-Smtp-Source: AGHT+IEP5Ve0SAHfQazPqF9nIyhZQhiOlTvX2DA9krSJhQNaPqRJa1K2XQyf0FDea5ABNNKGtBdXLg== X-Received: by 2002:a05:6512:b16:b0:536:7362:5912 with SMTP id 2adb3069b0e04-5367fee6dc5mr3121432e87.30.1726243094655; Fri, 13 Sep 2024 08:58:14 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v7 7/8] xen/riscv: page table handling Date: Fri, 13 Sep 2024 17:57:45 +0200 Message-ID: <582c4cee40222e80faf1e465c011b07eeaf2c19f.1726242605.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: MIME-Version: 1.0 Implement map_pages_to_xen() which requires several functions to manage page tables and entries: - pt_update() - pt_mapping_level() - pt_update_entry() - pt_next_level() - pt_check_entry() To support these operations, add functions for creating, mapping, and unmapping Xen tables: - create_table() - map_table() - unmap_table() Introduce PTE_SMALL to indicate that 4KB mapping is needed and PTE_POPULATE. In addition introduce flush_tlb_range_va() for TLB flushing across CPUs after updating the PTE for the requested mapping. Signed-off-by: Oleksii Kurochko --- Changes in V7: - rename PTE_XWV_BITS to PTE_LEAF_MASK. - drop PTE_XWV_MASK, PTE_RWX_MASK. - introduce PTE_ACCESS_MASK. - update the ASSERT and the comment about it in pte_is_mapping(). - add the same ASSERT as in pte_is_mapping() to pte_is_table(). - update the comment above pte_is_table(). - use PTE_ACCESS_MASK inside pte_is_{table,mapping} instead of encoding access bit explicitly. - define SATP_PPN_MASK using SATP{32,64}_PPN. - drop inclusion of #include in riscv/pt.c as xen/mm.h is included. - use pfn_to_paddr() in get_root_page() instead of open-coding of pfn_to_paddr(). - update if the comment and the if (...) in pt_update_entry() above the check in case of pt_next_level() returns XEN_TABLE_MAP_FAILED. - update the the comment above pt_update(): drop unecessary mentioning of INVALID_MFN and blanks inside parentheses. - drop "full stops" in printk(). - correct the condition in ASSERT() in map_pages_to_xen(). - clear permission bits before updating the permissions in pt_update_entry(). --- Changes in V6: - update the commit message. - correct the comment above flush_tlb_range_va(). - add PTE_READABLE to the check of pte.rwx permissions in pte_is_mapping(). - s/printk/dprintk in pt_check_entry(). - drop unnecessary ASSERTS() in pt_check_entry(). - drop checking of PTE_VALID flags in /* Sanity check when removing a mapping */ because of the earlier check. - drop ASSERT(flags & PTE_POPULATE) in /* Sanity check when populating the page-table */ section as in the earlier if it is checked. - pt_next_level() changes: - invert if ( alloc_tbl ) condition. - drop local variable ret. - pt_update_entry() changes: - invert definition of alloc_tbl. - update the comment inside "if ( rc == XEN_TABLE_MAP_FAILED )". - drop else for mentioned above if (...). - clear some PTE flags before update. - s/xen_pt_lock/pt_lock - use PFN_DOWN() for vfn variable definition in pt_update(). - drop definition of PTE_{R,W,X}_MASK. - introduce PTE_XWV_BITS and PTE_XWV_MASK() for convenience and use them in if (...) in pt_update(). - update the comment above pt_update(). - change memset(&pte, 0x00, sizeof(pte)) to pte.pte = 0. - add the comment above pte_is_table(). - add ASSERT in pte_is_mapping() to check the cases which are reserved for future use. --- Changes in V5: - s/xen_{un}map/{un}map - introduce PTE_SMALL instead of PTE_BLOCK. - update the comment above defintion of PTE_4K_PAGES. - code style fixes. - s/RV_STAGE1_MODE > SATP_MODE_SV48/RV_STAGE1_MODE > SATP_MODE_SV39 around DECLARE_OFFSETS macros. - change type of root_maddr from unsgined long to maddr_t. - drop duplicated check ( if (rc) break ) in pt_update() inside while cycle. - s/1U/1UL - put 'spin_unlock(&xen_pt_lock);' ahead of TLB flush in pt_update(). - update the commit message. - update the comment above ASSERT() in map_pages_to_xen() and also update the check within ASSERT() to check that flags has PTE_VALID bit set. - update the comment above pt_update() function. - add the comment inside pt_check_entry(). - update the TLB flushing region in pt_update(). - s/alloc_only/alloc_tbl --- Changes in V4: - update the commit message. - drop xen_ prefix for functions: xen_pt_update(), xen_pt_mapping_level(), xen_pt_update_entry(), xen_pt_next_level(), xen_pt_check_entry(). - drop 'select GENERIC_PT' for CONFIG_RISCV. There is no GENERIC_PT anymore. - update implementation of flush_xen_tlb_range_va and s/flush_xen_tlb_range_va/flush_tlb_range_va - s/pte_get_mfn/mfn_from_pte. Others similar definitions I decided not to touch as they were introduced before and this patter of naming such type of macros will be applied for newly introduced macros. - drop _PAGE_* definitions and use analogues of PTE_*. - introduce PTE_{W,X,R}_MASK and drop PAGE_{XN,W,X}_MASK. Also drop _PAGE_{*}_BIT - introduce PAGE_HYPERVISOR_RX. - drop unused now l3_table_offset. - drop struct pt_t as it was used only for one function. If it will be needed in the future pt_t will be re-introduced. - code styles fixes in pte_is_table(). drop level argument from t. - update implementation and prototype of pte_is_mapping(). - drop level argument from pt_next_level(). - introduce definition of SATP_PPN_MASK. - isolate PPN of CSR_SATP before shift by PAGE_SHIFT. - drop set_permission() functions as it is not used more then once. - update prototype of pt_check_entry(): drop level argument as it is not used. - pt_check_entry(): - code style fixes - update the sanity check when modifying an entry - update the sanity check when when removing a mapping. - s/read_only/alloc_only. - code style fixes for pt_next_level(). - pt_update_entry() changes: - drop arch_level variable inisde pt_update_entry() - drop convertion near virt to paddr_t in DECLARE_OFFSETS(offsets, virt); - pull out "goto out inside first 'for' cycle. - drop braces for 'if' cases which has only one line. - ident 'out' label with one blank. - update the comment above alloc_only and also definition to take into account that if pte population was requested or not. - drop target variable and rename arch_target argument of the function to target. - pt_mapping_level() changes: - move the check if PTE_BLOCK should be mapped on the top of the function. - change int i to unsigned int and update 'for' cycle correspondingly. - update prototye of pt_update(): - drop the comment above nr_mfns and drop const to be consistent with other arguments. - always flush TLB at the end of the function as non-present entries can be put in the TLB. - add fence before TLB flush to ensure that PTEs are all updated before flushing. - s/XEN_TABLE_NORMAL_PAGE/XEN_TABLE_NORMAL - add a check in map_pages_to_xen() the mfn is not INVALID_MFN. - add the comment on top of pt_update() how mfn = INVALID_MFN is considered. - s/_PAGE_BLOCK/PTE_BLOCK. - add the comment with additional explanation for PTE_BLOCK. - drop defintion of FIRST_SIZE as it isn't used. --- Changes in V3: - new patch. ( Technically it is reworked version of the generic approach which I tried to suggest in the previous version ) --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/flushtlb.h | 9 + xen/arch/riscv/include/asm/mm.h | 2 + xen/arch/riscv/include/asm/page.h | 86 ++++ xen/arch/riscv/include/asm/riscv_encoding.h | 2 + xen/arch/riscv/mm.c | 9 - xen/arch/riscv/pt.c | 427 ++++++++++++++++++++ 7 files changed, 527 insertions(+), 9 deletions(-) create mode 100644 xen/arch/riscv/pt.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 6832549133..a5eb2aed4b 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o obj-y += mm.o +obj-y += pt.o obj-$(CONFIG_RISCV_64) += riscv64/ obj-y += sbi.o obj-y += setup.o diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include/asm/flushtlb.h index f4a735fd6c..43214f5e95 100644 --- a/xen/arch/riscv/include/asm/flushtlb.h +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -5,12 +5,21 @@ #include #include +#include + /* Flush TLB of local processor for address va. */ static inline void flush_tlb_one_local(vaddr_t va) { asm volatile ( "sfence.vma %0" :: "r" (va) : "memory" ); } +/* Flush a range of VA's hypervisor mappings from the TLB of all processors. */ +static inline void flush_tlb_range_va(vaddr_t va, size_t size) +{ + BUG_ON(!sbi_has_rfence()); + sbi_remote_sfence_vma(NULL, va, size); +} + /* * Filter the given set of CPUs, removing those that definitely flushed their * TLB since @page_timestamp. diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h index a0bdc2bc3a..ce1557bb27 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -42,6 +42,8 @@ static inline void *maddr_to_virt(paddr_t ma) #define virt_to_mfn(va) __virt_to_mfn(va) #define mfn_to_virt(mfn) __mfn_to_virt(mfn) +#define mfn_from_pte(pte) maddr_to_mfn(pte_to_paddr(pte)) + struct page_info { /* Each frame can be threaded onto a doubly-linked list. */ diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm/page.h index eb79cb9409..2c26e91367 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -21,6 +21,11 @@ #define XEN_PT_LEVEL_MAP_MASK(lvl) (~(XEN_PT_LEVEL_SIZE(lvl) - 1)) #define XEN_PT_LEVEL_MASK(lvl) (VPN_MASK << XEN_PT_LEVEL_SHIFT(lvl)) +/* + * PTE format: + * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 + * PFN reserved for SW D A G U X W R V + */ #define PTE_VALID BIT(0, UL) #define PTE_READABLE BIT(1, UL) #define PTE_WRITABLE BIT(2, UL) @@ -34,15 +39,50 @@ #define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITABLE) #define PTE_TABLE (PTE_VALID) +#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE) #define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITABLE) +#define PAGE_HYPERVISOR_RX (PTE_VALID | PTE_READABLE | PTE_EXECUTABLE) #define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW +/* + * The PTE format does not contain the following bits within itself; + * they are created artificially to inform the Xen page table + * handling algorithm. These bits should not be explicitly written + * to the PTE entry. + */ +#define PTE_SMALL BIT(10, UL) +#define PTE_POPULATE BIT(11, UL) + +#define PTE_LEAF_MASK (PTE_WRITABLE | PTE_EXECUTABLE | PTE_VALID) +#define PTE_ACCESS_MASK (PTE_READABLE | PTE_WRITABLE | PTE_EXECUTABLE) + /* Calculate the offsets into the pagetables for a given VA */ #define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl)) #define pt_index(lvl, va) (pt_linear_offset((lvl), (va)) & VPN_MASK) +#define PAGETABLE_ORDER_MASK ((_AC(1, U) << PAGETABLE_ORDER) - 1) +#define TABLE_OFFSET(offs) (_AT(unsigned int, offs) & PAGETABLE_ORDER_MASK) + +#if RV_STAGE1_MODE > SATP_MODE_SV39 +#error "need to to update DECLARE_OFFSETS macros" +#else + +#define l0_table_offset(va) TABLE_OFFSET(pt_linear_offset(0, va)) +#define l1_table_offset(va) TABLE_OFFSET(pt_linear_offset(1, va)) +#define l2_table_offset(va) TABLE_OFFSET(pt_linear_offset(2, va)) + +/* Generate an array @var containing the offset for each level from @addr */ +#define DECLARE_OFFSETS(var, addr) \ + const unsigned int var[] = { \ + l0_table_offset(addr), \ + l1_table_offset(addr), \ + l2_table_offset(addr), \ + } + +#endif + /* Page Table entry */ typedef struct { #ifdef CONFIG_RISCV_64 @@ -68,6 +108,52 @@ static inline bool pte_is_valid(pte_t p) return p.pte & PTE_VALID; } +/* + * From the RISC-V spec: + * The V bit indicates whether the PTE is valid; if it is 0, all other bits + * in the PTE are don’t-cares and may be used freely by software. + * + * If V=1 the encoding of PTE R/W/X bits could be find in Table 4.5. + * + * Table 4.5 summarizes the encoding of the permission bits. + * X W R Meaning + * 0 0 0 Pointer to next level of page table. + * 0 0 1 Read-only page. + * 0 1 0 Reserved for future use. + * 0 1 1 Read-write page. + * 1 0 0 Execute-only page. + * 1 0 1 Read-execute page. + * 1 1 0 Reserved for future use. + * 1 1 1 Read-write-execute page. + */ +inline bool pte_is_table(const pte_t p) +{ + /* + * According to the spec if V=1 and W=1 then R also needs to be 1 as + * R = 0 is reserved for future use ( look at the Table 4.5 ) so check + * in ASSERT that if (V==1 && W==1) then R isn't 0. + * + * PAGE_HYPERVISOR_RW contains PTE_VALID too. + */ + ASSERT(((p.pte & PAGE_HYPERVISOR_RW) != (PTE_VALID | PTE_WRITABLE))); + + return ((p.pte & (PTE_VALID | PTE_ACCESS_MASK)) == PTE_VALID); +} + +static inline bool pte_is_mapping(/*const*/ pte_t p) +{ + /* + * According to the spec if V=1 and W=1 then R also needs to be 1 as + * R = 0 is reserved for future use ( look at the Table 4.5 ) so check + * in ASSERT that if (V==1 && W==1) then R isn't 0. + * + * PAGE_HYPERVISOR_RW contains PTE_VALID too. + */ + ASSERT(((p.pte & PAGE_HYPERVISOR_RW) != (PTE_VALID | PTE_WRITABLE))); + + return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK); +} + static inline void invalidate_icache(void) { BUG_ON("unimplemented"); diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/include/asm/riscv_encoding.h index 58abe5eccc..e31e94e77e 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -164,6 +164,7 @@ #define SSTATUS_SD SSTATUS64_SD #define SATP_MODE SATP64_MODE #define SATP_MODE_SHIFT SATP64_MODE_SHIFT +#define SATP_PPN_MASK SATP64_PPN #define HGATP_PPN HGATP64_PPN #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT @@ -174,6 +175,7 @@ #define SSTATUS_SD SSTATUS32_SD #define SATP_MODE SATP32_MODE #define SATP_MODE_SHIFT SATP32_MODE_SHIFT +#define SATP_PPN_MASK SATP32_PPN #define HGATP_PPN HGATP32_PPN #define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index b8ff91cf4e..e8430def14 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -369,12 +369,3 @@ int destroy_xen_mappings(unsigned long s, unsigned long e) BUG_ON("unimplemented"); return -1; } - -int map_pages_to_xen(unsigned long virt, - mfn_t mfn, - unsigned long nr_mfns, - unsigned int flags) -{ - BUG_ON("unimplemented"); - return -1; -} diff --git a/xen/arch/riscv/pt.c b/xen/arch/riscv/pt.c new file mode 100644 index 0000000000..fec5326907 --- /dev/null +++ b/xen/arch/riscv/pt.c @@ -0,0 +1,427 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static inline const mfn_t get_root_page(void) +{ + paddr_t root_maddr = pfn_to_paddr(csr_read(CSR_SATP) & SATP_PPN_MASK); + + return maddr_to_mfn(root_maddr); +} + +/* Sanity check of the entry. */ +static bool pt_check_entry(pte_t entry, mfn_t mfn, unsigned int flags) +{ + /* + * See the comment about the possible combination of (mfn, flags) in + * the comment above pt_update(). + */ + + /* Sanity check when modifying an entry. */ + if ( (flags & PTE_VALID) && mfn_eq(mfn, INVALID_MFN) ) + { + /* We don't allow modifying an invalid entry. */ + if ( !pte_is_valid(entry) ) + { + dprintk(XENLOG_ERR, "Modifying invalid entry is not allowed\n"); + return false; + } + + /* We don't allow modifying a table entry */ + if ( pte_is_table(entry) ) + { + dprintk(XENLOG_ERR, "Modifying a table entry is not allowed\n"); + return false; + } + } + /* Sanity check when inserting a mapping */ + else if ( flags & PTE_VALID ) + { + /* + * We don't allow replacing any valid entry. + * + * Note that the function pt_update() relies on this + * assumption and will skip the TLB flush (when Svvptc + * extension will be ratified). The function will need + * to be updated if the check is relaxed. + */ + if ( pte_is_valid(entry) ) + { + if ( pte_is_mapping(entry) ) + dprintk(XENLOG_ERR, "Changing MFN for valid PTE is not allowed (%#"PRI_mfn" -> %#"PRI_mfn")\n", + mfn_x(mfn_from_pte(entry)), mfn_x(mfn)); + else + dprintk(XENLOG_ERR, "Trying to replace table with mapping\n"); + return false; + } + } + /* Sanity check when removing a mapping. */ + else if ( !(flags & PTE_POPULATE) ) + { + /* We should be here with an invalid MFN. */ + ASSERT(mfn_eq(mfn, INVALID_MFN)); + + /* We don't allow removing a table */ + if ( pte_is_table(entry) ) + { + dprintk(XENLOG_ERR, "Removing a table is not allowed\n"); + return false; + } + } + /* Sanity check when populating the page-table. No check so far. */ + else + { + /* We should be here with an invalid MFN */ + ASSERT(mfn_eq(mfn, INVALID_MFN)); + } + + return true; +} + +static pte_t *map_table(mfn_t mfn) +{ + /* + * During early boot, map_domain_page() may be unusable. Use the + * PMAP to map temporarily a page-table. + */ + if ( system_state == SYS_STATE_early_boot ) + return pmap_map(mfn); + + return map_domain_page(mfn); +} + +static void unmap_table(const pte_t *table) +{ + /* + * During early boot, map_table() will not use map_domain_page() + * but the PMAP. + */ + if ( system_state == SYS_STATE_early_boot ) + pmap_unmap(table); + else + unmap_domain_page(table); +} + +static int create_table(pte_t *entry) +{ + mfn_t mfn; + void *p; + pte_t pte; + + if ( system_state != SYS_STATE_early_boot ) + { + struct page_info *pg = alloc_domheap_page(NULL, 0); + + if ( pg == NULL ) + return -ENOMEM; + + mfn = page_to_mfn(pg); + } + else + mfn = alloc_boot_pages(1, 1); + + p = map_table(mfn); + clear_page(p); + unmap_table(p); + + pte = pte_from_mfn(mfn, PTE_TABLE); + write_pte(entry, pte); + + return 0; +} + +#define XEN_TABLE_MAP_FAILED 0 +#define XEN_TABLE_SUPER_PAGE 1 +#define XEN_TABLE_NORMAL 2 + +/* + * Take the currently mapped table, find the corresponding entry, + * and map the next table, if available. + * + * The alloc_tbl parameters indicates whether intermediate tables should + * be allocated when not present. + * + * Return values: + * XEN_TABLE_MAP_FAILED: Either alloc_only was set and the entry + * was empty, or allocating a new page failed. + * XEN_TABLE_NORMAL: next level or leaf mapped normally + * XEN_TABLE_SUPER_PAGE: The next entry points to a superpage. + */ +static int pt_next_level(bool alloc_tbl, pte_t **table, unsigned int offset) +{ + pte_t *entry; + mfn_t mfn; + + entry = *table + offset; + + if ( !pte_is_valid(*entry) ) + { + if ( !alloc_tbl ) + return XEN_TABLE_MAP_FAILED; + + if ( create_table(entry) ) + return XEN_TABLE_MAP_FAILED; + } + + if ( pte_is_mapping(*entry) ) + return XEN_TABLE_SUPER_PAGE; + + mfn = mfn_from_pte(*entry); + + unmap_table(*table); + *table = map_table(mfn); + + return XEN_TABLE_NORMAL; +} + +/* Update an entry at the level @target. */ +static int pt_update_entry(mfn_t root, unsigned long virt, + mfn_t mfn, unsigned int target, + unsigned int flags) +{ + int rc; + unsigned int level = HYP_PT_ROOT_LEVEL; + pte_t *table; + /* + * The intermediate page table shouldn't be allocated when MFN isn't + * valid and we are not populating page table. + * This means we either modify permissions or remove an entry, or + * inserting brand new entry. + * + * See the comment above pt_update() for an additional explanation about + * combinations of (mfn, flags). + */ + bool alloc_tbl = !mfn_eq(mfn, INVALID_MFN) || (flags & PTE_POPULATE); + pte_t pte, *entry; + + /* convenience aliases */ + DECLARE_OFFSETS(offsets, virt); + + table = map_table(root); + for ( ; level > target; level-- ) + { + rc = pt_next_level(alloc_tbl, &table, offsets[level]); + if ( rc == XEN_TABLE_MAP_FAILED ) + { + rc = 0; + + /* + * We are here because pt_next_level has failed to map + * the intermediate page table (e.g the table does not exist + * and the pt couldn't be allocated). It is a valid case when + * removing a mapping as it may not exist in the page table. + * In this case, just ignore it. + */ + if ( flags & (PTE_VALID | PTE_POPULATE) ) + { + printk("%s: Unable to map level %u\n", __func__, level); + rc = -ENOMEM; + } + + goto out; + } + + if ( rc != XEN_TABLE_NORMAL ) + break; + } + + if ( level != target ) + { + printk("%s: Shattering superpage is not supported\n", __func__); + rc = -EOPNOTSUPP; + goto out; + } + + entry = table + offsets[level]; + + rc = -EINVAL; + if ( !pt_check_entry(*entry, mfn, flags) ) + goto out; + + /* We are removing the page */ + if ( !(flags & PTE_VALID) ) + /* + * there is also a check in pt_check_entry() which check that + * mfn=INVALID_MFN + */ + pte.pte = 0; + else + { + /* We are inserting a mapping => Create new pte. */ + if ( !mfn_eq(mfn, INVALID_MFN) ) + pte = pte_from_mfn(mfn, PTE_VALID); + else /* We are updating the permission => Copy the current pte. */ + { + pte = *entry; + pte.pte &= ~(flags & PTE_ACCESS_MASK); + } + + /* update permission according to the flags */ + pte.pte |= (flags & PTE_ACCESS_MASK) | PTE_ACCESSED | PTE_DIRTY; + } + + write_pte(entry, pte); + + rc = 0; + + out: + unmap_table(table); + + return rc; +} + +/* Return the level where mapping should be done */ +static int pt_mapping_level(unsigned long vfn, mfn_t mfn, unsigned long nr, + unsigned int flags) +{ + unsigned int level = 0; + unsigned long mask; + unsigned int i; + + /* + * Use a larger mapping than 4K unless the caller specifically requests + * 4K mapping + */ + if ( unlikely(flags & PTE_SMALL) ) + return level; + + /* + * Don't take into account the MFN when removing mapping (i.e + * MFN_INVALID) to calculate the correct target order. + * + * `vfn` and `mfn` must be both superpage aligned. + * They are or-ed together and then checked against the size of + * each level. + * + * `left` ( variable declared in pt_update() ) is not included + * and checked separately to allow superpage mapping even if it + * is not properly aligned (the user may have asked to map 2MB + 4k). + */ + mask = !mfn_eq(mfn, INVALID_MFN) ? mfn_x(mfn) : 0; + mask |= vfn; + + for ( i = HYP_PT_ROOT_LEVEL; i != 0; i-- ) + { + if ( !(mask & (BIT(XEN_PT_LEVEL_ORDER(i), UL) - 1)) && + (nr >= BIT(XEN_PT_LEVEL_ORDER(i), UL)) ) + { + level = i; + break; + } + } + + return level; +} + +static DEFINE_SPINLOCK(pt_lock); + +/* + * If `mfn` equals `INVALID_MFN`, it indicates that the following page table + * update operation might be related to either: + * - populating the table (PTE_POPULATE will be set additionaly), + * - destroying a mapping (PTE_VALID=0), + * - modifying an existing mapping (PTE_VALID=1). + * + * If `mfn` != INVALID_MFN and flags has PTE_VALID bit set then it means that + * inserting will be done. + */ +static int pt_update(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + int rc = 0; + unsigned long vfn = PFN_DOWN(virt); + unsigned long left = nr_mfns; + + const mfn_t root = get_root_page(); + + /* + * It is bad idea to have mapping both writeable and + * executable. + * When modifying/creating mapping (i.e PTE_VALID is set), + * prevent any update if this happen. + */ + if ( (flags & PTE_LEAF_MASK) == PTE_LEAF_MASK ) + { + printk("Mappings should not be both Writeable and Executable\n"); + return -EINVAL; + } + + if ( !IS_ALIGNED(virt, PAGE_SIZE) ) + { + printk("The virtual address is not aligned to the page-size\n"); + return -EINVAL; + } + + spin_lock(&pt_lock); + + while ( left ) + { + unsigned int order, level; + + level = pt_mapping_level(vfn, mfn, left, flags); + order = XEN_PT_LEVEL_ORDER(level); + + ASSERT(left >= BIT(order, UL)); + + rc = pt_update_entry(root, vfn << PAGE_SHIFT, mfn, level, flags); + if ( rc ) + break; + + vfn += 1UL << order; + if ( !mfn_eq(mfn, INVALID_MFN) ) + mfn = mfn_add(mfn, 1UL << order); + + left -= (1UL << order); + } + + /* Ensure that PTEs are all updated before flushing */ + RISCV_FENCE(rw, rw); + + spin_unlock(&pt_lock); + + /* + * Always flush TLB at the end of the function as non-present entries + * can be put in the TLB. + * + * The remote fence operation applies to the entire address space if + * either: + * - start and size are both 0, or + * - size is equal to 2^XLEN-1. + * + * TODO: come up with something which will allow not to flash the entire + * address space. + */ + flush_tlb_range_va(0, 0); + + return rc; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + /* + * Ensure that flags has PTE_VALID bit as map_pages_to_xen() is supposed + * to create a mapping. + * + * Ensure that we have a valid MFN before proceeding. + * + * If the MFN is invalid, pt_update() might misinterpret the operation, + * treating it as either a population, a mapping destruction, + * or a mapping modification. + */ + ASSERT(!mfn_eq(mfn, INVALID_MFN) && (flags & PTE_VALID)); + + return pt_update(virt, mfn, nr_mfns, flags); +} From patchwork Fri Sep 13 15:57:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13803801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A62BFFA375B for ; Fri, 13 Sep 2024 15:58:48 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.798305.1208545 (Exim 4.92) (envelope-from ) id 1sp8gy-0003Ni-Nk; Fri, 13 Sep 2024 15:58:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 798305.1208545; Fri, 13 Sep 2024 15:58:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8gy-0003NW-L1; Fri, 13 Sep 2024 15:58:40 +0000 Received: by outflank-mailman (input) for mailman id 798305; Fri, 13 Sep 2024 15:58:39 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sp8gw-0000AA-VZ for xen-devel@lists.xenproject.org; Fri, 13 Sep 2024 15:58:39 +0000 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [2a00:1450:4864:20::134]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id fd1cd72d-71e8-11ef-99a2-01e77a169b0f; Fri, 13 Sep 2024 17:58:16 +0200 (CEST) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-53654dbde59so3215303e87.1 for ; Fri, 13 Sep 2024 08:58:16 -0700 (PDT) Received: from fedora.. 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Also, initialization of device_tree_flattened happens using early_fdt_map(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V6-V7: - Nothing changed. Only rebase. --- Changes in V5: - drop usage of PTE_BLOCK for flag argument of map_pages_to_xen() in early_fdt_map() as block mapping is now default behaviour. Also PTE_BLOCK was dropped in the patch "xen/riscv: page table handling". --- Changes in V4: - s/_PAGE_BLOCK/PTE_BLOCK - Add Acked-by: Jan Beulich - unwarap two lines in panic() in case when device_tree_flattened is NULL so grep-ing for any part of the message line will always produce a hit. - slightly update the commit message. --- Changes in V3: - Code style fixes - s/SZ_2M/MB(2) - fix condition to check if early_fdt_map() in setup.c return NULL or not. --- Changes in V2: - rework early_fdt_map to use map_pages_to_xen() - move call early_fdt_map() to C code after MMU is enabled. --- xen/arch/riscv/include/asm/mm.h | 2 ++ xen/arch/riscv/mm.c | 55 +++++++++++++++++++++++++++++++++ xen/arch/riscv/setup.c | 7 +++++ 3 files changed, 64 insertions(+) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h index ce1557bb27..4b7b00b850 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -259,4 +259,6 @@ static inline unsigned int arch_get_dma_bitsize(void) void setup_fixmap_mappings(void); +void *early_fdt_map(paddr_t fdt_paddr); + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index e8430def14..4a628aef83 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -1,13 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include +#include #include #include #include #include +#include #include #include @@ -369,3 +372,55 @@ int destroy_xen_mappings(unsigned long s, unsigned long e) BUG_ON("unimplemented"); return -1; } + +void * __init early_fdt_map(paddr_t fdt_paddr) +{ + /* We are using 2MB superpage for mapping the FDT */ + paddr_t base_paddr = fdt_paddr & XEN_PT_LEVEL_MAP_MASK(1); + paddr_t offset; + void *fdt_virt; + uint32_t size; + int rc; + + /* + * Check whether the physical FDT address is set and meets the minimum + * alignment requirement. Since we are relying on MIN_FDT_ALIGN to be at + * least 8 bytes so that we always access the magic and size fields + * of the FDT header after mapping the first chunk, double check if + * that is indeed the case. + */ + BUILD_BUG_ON(MIN_FDT_ALIGN < 8); + if ( !fdt_paddr || fdt_paddr % MIN_FDT_ALIGN ) + return NULL; + + /* The FDT is mapped using 2MB superpage */ + BUILD_BUG_ON(BOOT_FDT_VIRT_START % MB(2)); + + rc = map_pages_to_xen(BOOT_FDT_VIRT_START, maddr_to_mfn(base_paddr), + MB(2) >> PAGE_SHIFT, + PAGE_HYPERVISOR_RO); + if ( rc ) + panic("Unable to map the device-tree.\n"); + + offset = fdt_paddr % XEN_PT_LEVEL_SIZE(1); + fdt_virt = (void *)BOOT_FDT_VIRT_START + offset; + + if ( fdt_magic(fdt_virt) != FDT_MAGIC ) + return NULL; + + size = fdt_totalsize(fdt_virt); + if ( size > BOOT_FDT_VIRT_SIZE ) + return NULL; + + if ( (offset + size) > MB(2) ) + { + rc = map_pages_to_xen(BOOT_FDT_VIRT_START + MB(2), + maddr_to_mfn(base_paddr + MB(2)), + MB(2) >> PAGE_SHIFT, + PAGE_HYPERVISOR_RO); + if ( rc ) + panic("Unable to map the device-tree\n"); + } + + return fdt_virt; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index e73248c035..2980e300c6 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -57,6 +58,12 @@ void __init noreturn start_xen(unsigned long bootcpu_id, setup_fixmap_mappings(); + device_tree_flattened = early_fdt_map(dtb_addr); + if ( !device_tree_flattened ) + panic("Invalid device tree blob at physical address %#lx. The DTB must be 8-byte aligned and must not exceed %lld bytes in size.\n\n" + "Please check your bootloader.\n", + dtb_addr, BOOT_FDT_VIRT_SIZE); + printk("All set up\n"); machine_halt();