From patchwork Fri Sep 13 17:32:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Mattson X-Patchwork-Id: 13803882 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3780D84A5E for ; Fri, 13 Sep 2024 17:32:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726248774; cv=none; b=THNvEabo8RFFwSz+vIiLf7fnchbobMifduD4jtxxdk8Jjy7m3wMpapEfY/YWoKPiMflnCkxRQoPWrtoRFlt5n1JpfwO0f6cb7Lgj/LfSJUNjWXVdFq3bsJR50XTKQc944ytnxeFK1+X30000rk0kzht2BcKse1u+coN2cy16jwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726248774; c=relaxed/simple; bh=HDuqfoGAVFaFiIFfM0Hgx7ESE0/KySm9U402yKd83Lk=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=faVsuTeJYrD0akO/rYFGdpJbz8lXe4+C0UVXhI1zfnkKVuGcYqIEPvZ0dPy83EynmDEc/DbsVoAymwcoKytPWSQ97FgyZdo4dslBu9A5o0nwur4Y+jULR63NjFeZ72tHZpOdxiFcPSJK3uC0Rgde99Xa3eUY+ey4FmLUUklQtmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=IJ1d30kc; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="IJ1d30kc" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2d8b7c662ccso3158963a91.0 for ; Fri, 13 Sep 2024 10:32:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1726248772; x=1726853572; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=0xC0WDg0DA01ClxmzXesXFMgeFghs8OuAlIxAFkxwlI=; b=IJ1d30kcqdzwnIyrlfd16smjmHeUr/D7KDywAsdo1k+965L2M8xCAcvTGuI7PvWqFb OX7W8Vt7BNMUMv5z9lW4MTol8f7fuPXnEgzNUcgEarS5f6eJeTpwimDSf5mcEV26xP4c riJBwPY2I1DohmdoFt9OW3E2W77aKGqkUoDaQ8o1ZpR5e7IGbY9vAU82AQ8UCJX7nhm4 suXkbXDVQXJAwwgKHwKrblDIcoRB5sco70RyU63JMuKoTs8JH6jxVZn8w3k1PfZ97eIF bOpHshaZ3TTc8ojPJbKu8LnAZdbZ+geyCPxSqOt0UdPRpDzshrxhLT9RRKXTfeqgW9T6 eJKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726248772; x=1726853572; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=0xC0WDg0DA01ClxmzXesXFMgeFghs8OuAlIxAFkxwlI=; b=H42xPlcKOylcrT2ONLVXaTQlSEvwhhrdcSbBBq+A0YLNQG/IsvKJZ2WWCf27khCplA b6NJ6bqsn69n2Hf+V73d3xWZFI2b6vzcx5RgTRvE0ZQhS7aUyqzx955zF3r7lf3G+ijt 4/GF+wY9XxssEbDX/3OjosNV08v93DSRbCDrfUdPCZ5oo9h2OKpqZhMABvvtybWlZfl1 pCu46f1nueaKI4SSwqtEClwQ4Gz+R2+EIYOEWnLET9Y+3/Q2Vlfo7XX2OpQKc1vEdR2/ u8ubT8PHDklJzri+wWuLruZaoQiixo2RRrcOIAVqlgD8oaMMyX3+FANwoYvozt2soAJL SkYQ== X-Forwarded-Encrypted: i=1; AJvYcCXMe7a4gNMYusGAw2Kawm1htYKiCEbQG03n0byo3sdHsM/y+2qFQOiDyYKmE3GHfU5fMhQ=@vger.kernel.org X-Gm-Message-State: AOJu0YyF1Qas/rycRNM8SEXerc5EWNWb0Er6sdleAhwFJUvK6htH7x8Y +YnJ8YFDbYICIzw4S5e9npfTIJXAUwQw2yagaJYd68uGMcVY4imp6U8QRch1VHyuw1Bswpx8JHY WsapdCexHHA== X-Google-Smtp-Source: AGHT+IHMNOAn6ONfLm0s0lShKg1+JX+PSnwD4/Fe9XkheUIM13sgRhSgr1mgasZb8r9b3ATfihXftl8+FLb4gQ== X-Received: from loggerhead.c.googlers.com ([fda3:e722:ac3:cc00:f3:525d:ac13:60e1]) (user=jmattson job=sendgmr) by 2002:a17:90a:f60a:b0:2d2:453:1501 with SMTP id 98e67ed59e1d1-2db9ff6b19amr14420a91.2.1726248772274; Fri, 13 Sep 2024 10:32:52 -0700 (PDT) Date: Fri, 13 Sep 2024 10:32:27 -0700 In-Reply-To: <20240913173242.3271406-1-jmattson@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240913173242.3271406-1-jmattson@google.com> X-Mailer: git-send-email 2.46.0.662.g92d0881bb0-goog Message-ID: <20240913173242.3271406-2-jmattson@google.com> Subject: [PATCH v4 1/3] x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET From: Jim Mattson To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Pawan Gupta , Josh Poimboeuf , Jim Mattson , Sandipan Das , Kai Huang , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Venkatesh Srinivas AMD's initial implementation of IBPB did not clear the return address predictor. Beginning with Zen4, AMD's IBPB *does* clear the return address predictor. This behavior is enumerated by CPUID.80000008H:EBX.IBPB_RET[bit 30]. Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID, when determining cross-vendor capabilities. Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson --- arch/x86/include/asm/cpufeatures.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index cabd6b58e8ec..a222a24677d7 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -215,7 +215,7 @@ #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* Disable Speculative Store Bypass. */ #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* AMD SSBD implementation via LS_CFG MSR */ #define X86_FEATURE_IBRS ( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */ -#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without RSB flush */ +#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */ #define X86_FEATURE_STIBP ( 7*32+27) /* "stibp" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_ZEN ( 7*32+28) /* Generic flag for all Zen and newer */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* L1TF workaround PTE inversion */ @@ -348,6 +348,7 @@ #define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Performance Control */ #define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ #define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Confusion */ +#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */ #define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ From patchwork Fri Sep 13 17:32:28 2024 Content-Type: text/plain; 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Peter Anvin" , Sean Christopherson , Paolo Bonzini , Pawan Gupta , Josh Poimboeuf , Jim Mattson , Sandipan Das , Kai Huang , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Tom Lendacky This is an inherent feature of IA32_PRED_CMD[0], so it is trivially virtualizable (as long as IA32_PRED_CMD[0] is virtualized). Suggested-by: Tom Lendacky Signed-off-by: Jim Mattson --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 2617be544480..ec7b2ca3b4d3 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -751,7 +751,7 @@ void kvm_set_cpu_caps(void) F(CLZERO) | F(XSAVEERPTR) | F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | - F(AMD_PSFD) + F(AMD_PSFD) | F(AMD_IBPB_RET) ); /* From patchwork Fri Sep 13 17:32:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Mattson X-Patchwork-Id: 13803884 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2057212BEBB for ; Fri, 13 Sep 2024 17:32:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 13 Sep 2024 10:32:56 -0700 (PDT) Date: Fri, 13 Sep 2024 10:32:29 -0700 In-Reply-To: <20240913173242.3271406-1-jmattson@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240913173242.3271406-1-jmattson@google.com> X-Mailer: git-send-email 2.46.0.662.g92d0881bb0-goog Message-ID: <20240913173242.3271406-4-jmattson@google.com> Subject: [PATCH v4 3/3] KVM: x86: AMD's IBPB is not equivalent to Intel's IBPB From: Jim Mattson To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Pawan Gupta , Josh Poimboeuf , Jim Mattson , Sandipan Das , Kai Huang , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Venkatesh Srinivas From Intel's documention [1], "CPUID.(EAX=07H,ECX=0):EDX[26] enumerates support for indirect branch restricted speculation (IBRS) and the indirect branch predictor barrier (IBPB)." Further, from [2], "Software that executed before the IBPB command cannot control the predicted targets of indirect branches (4) executed after the command on the same logical processor," where footnote 4 reads, "Note that indirect branches include near call indirect, near jump indirect and near return instructions. Because it includes near returns, it follows that **RSB entries created before an IBPB command cannot control the predicted targets of returns executed after the command on the same logical processor.**" [emphasis mine] On the other hand, AMD's IBPB "may not prevent return branch predictions from being specified by pre-IBPB branch targets" [3]. However, some AMD processors have an "enhanced IBPB" [terminology mine] which does clear the return address predictor. This feature is enumerated by CPUID.80000008:EDX.IBPB_RET[bit 30] [4]. Adjust the cross-vendor features enumerated by KVM_GET_SUPPORTED_CPUID accordingly. [1] https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html [2] https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/speculative-execution-side-channel-mitigations.html#Footnotes [3] https://www.amd.com/en/resources/product-security/bulletin/amd-sb-1040.html [4] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf Fixes: 0c54914d0c52 ("KVM: x86: use Intel speculation bugs and features as derived in generic x86 code") Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson --- arch/x86/kvm/cpuid.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index ec7b2ca3b4d3..600d79ea22be 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -690,7 +690,9 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); - if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) + if (boot_cpu_has(X86_FEATURE_AMD_IBPB_RET) && + boot_cpu_has(X86_FEATURE_AMD_IBPB) && + boot_cpu_has(X86_FEATURE_AMD_IBRS)) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); if (boot_cpu_has(X86_FEATURE_STIBP)) kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); @@ -759,8 +761,12 @@ void kvm_set_cpu_caps(void) * arch/x86/kernel/cpu/bugs.c is kind enough to * record that in cpufeatures so use them. */ - if (boot_cpu_has(X86_FEATURE_IBPB)) + if (boot_cpu_has(X86_FEATURE_IBPB)) { kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) && + !boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) + kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB_RET); + } if (boot_cpu_has(X86_FEATURE_IBRS)) kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); if (boot_cpu_has(X86_FEATURE_STIBP))