From patchwork Sat Sep 14 11:27:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13804379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7B59C02191 for ; Sat, 14 Sep 2024 11:28:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e8Evo768Ww9Y3xJQnW3o763ZWy3db6sd1I/g2zdZHk8=; b=Wg/8Ex9wESpMPO 3qW9wySePhAVeLuJWietpQ4be0WnFjpkd7TkFYfVJMuJWKZgQjGs1cEoL6cuhhCrfWrhS74ADe74F 33RpR0fDb8ng9SR3Qb4YwYxUdUx4lkL4LP1eJWJu0k1656Tmlx34VqWs9e3nU0TWcYMbI+Tjmz3Mm O8r3lw/o0o5hB1UJNNKUPMcRSRC3qchfWtAsL1pG9x242zhOkbYB+KD8MEJun8Cju+WT1CRVAzShy CeOOqo5yQNKBs9T+GWt0PfIkAc23B57UG8xkn7kQOgcwyi37mgiKVj1FicL8a4o6rf89G7df3ZL+8 tr8KrwUC+8rX2+F4rZ4A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1spQx8-00000000bSP-1nuT; Sat, 14 Sep 2024 11:28:34 +0000 Received: from mail-il1-x12a.google.com ([2607:f8b0:4864:20::12a]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1spQx5-00000000bRz-1Clf for linux-phy@lists.infradead.org; Sat, 14 Sep 2024 11:28:32 +0000 Received: by mail-il1-x12a.google.com with SMTP id e9e14a558f8ab-3a046d4c465so10196885ab.3 for ; Sat, 14 Sep 2024 04:28:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726313310; x=1726918110; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sc6l/7+wAK/3eeXDnGFKIjH8BtySZh1MPIxSosqGzxg=; b=Cd3Wcfie/wH1IKv20OXt2JYsA13Y7oTQoRV8TuUNhmr7Ylh7KZZgVQlNVt+IHsA+uH wL90zbxKoBPN9svJxr5uFbGuCz7OxVZzVFPmRTKAsgyC9rReae/MxXIY/ay6P2MtU6Pf VBOAX1Q8tPapKPd4aiHU0Bj71hR+3k7OOqlu7J+H8iQRzA60c/lJ9SKh4AhoVD5QT0VM ompSOAfX/W6llbvbSDkH9QE5Hys+ubM9gkJ2NlT3i/IqSuzEDitkK0G01jwyovX8VbPg W+1UPe+0DevHJv+rcUlYrRwZwi7ErT7JrkrqF/sutF4TZSuCvzJ0gzwpcRybat04ixMx pAWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726313310; x=1726918110; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sc6l/7+wAK/3eeXDnGFKIjH8BtySZh1MPIxSosqGzxg=; b=UFBqopUrO6B6bH21LTsOV4E0j84dNcnaGnfRxoqOliftpc3+C6MlFMj1epFTlA3lc0 mgMni1GbjZODwHq4ZWEAWFHoSZF/8rqMkVIPpMn/5jDiOlY5GA+rALGw+W0OywzB/fDg QkGFzf/gUQ0JzMcLBFp06yzZM0JcxWr8ZL3I0B5n0znfGBbCI8asyiUnz1cpto1FNuV6 +rGoAdWlNKDR653lbRPuwI0WJanN2vIfnNaInDTJ+c5j2CHkj1sjO4zUBFssNkYQ/rIV /tXI0Re43Qv+b063Gfx6zQAWD5px8am6c1jriPBl1GsT78eedSbUvHZ7OIKcOe4bWgXz cltA== X-Gm-Message-State: AOJu0YyCTnZmve03f9FkW0NWsGmcQZZS7q2+hAMMOHwad/qlncLaCoaS erygVYZ+xvETVPld+XMZ7T2xwAEY4TvMPC2C8XOoz1nR+XdfsM0ThvDwtA== X-Google-Smtp-Source: AGHT+IGCjWY9rQrAIMBaOzkf5OBza0yShUyJL8vHDv8VnOkYzVumhtb4cOJIniD5Jp+Z353515syaQ== X-Received: by 2002:a05:6e02:1b0a:b0:39b:3980:3288 with SMTP id e9e14a558f8ab-3a0848af762mr87789765ab.1.1726313309456; Sat, 14 Sep 2024 04:28:29 -0700 (PDT) Received: from aford-System-Version.lan (c-75-72-166-104.hsd1.mn.comcast.net. [75.72.166.104]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4d37ed35572sm350307173.131.2024.09.14.04.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Sep 2024 04:28:28 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, neil.armstrong@linaro.org, Adam Ford , Marco Felsch , Vinod Koul , Kishon Vijay Abraham I , Lucas Stach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-kernel@vger.kernel.org Subject: [PATCH V8 1/5] phy: freescale: fsl-samsung-hdmi: Replace register defines with macro Date: Sat, 14 Sep 2024 06:27:45 -0500 Message-ID: <20240914112816.520224-2-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240914112816.520224-1-aford173@gmail.com> References: <20240914112816.520224-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240914_042831_353544_D6E47D79 X-CRM114-Status: GOOD ( 15.27 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org There are 47 registers defined as PHY_REG_xx were xx goes from 00 to 47. Simplify this by replacing them all with a macro which is passed the register number to return the proper register offset. Signed-off-by: Adam Ford Reviewed-by: Marco Felsch Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf Reviewed-by: Dominique Martinet Tested-by: Dominique Martinet --- V7: No change V6: No change --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 133 ++++++------------- 1 file changed, 43 insertions(+), 90 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 9048cdc760c2..acea7008aefc 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -14,76 +14,29 @@ #include #include -#define PHY_REG_00 0x00 -#define PHY_REG_01 0x04 -#define PHY_REG_02 0x08 -#define PHY_REG_08 0x20 -#define PHY_REG_09 0x24 -#define PHY_REG_10 0x28 -#define PHY_REG_11 0x2c - -#define PHY_REG_12 0x30 -#define REG12_CK_DIV_MASK GENMASK(5, 4) - -#define PHY_REG_13 0x34 -#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) - -#define PHY_REG_14 0x38 -#define REG14_TOL_MASK GENMASK(7, 4) -#define REG14_RP_CODE_MASK GENMASK(3, 1) -#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0) - -#define PHY_REG_15 0x3c -#define PHY_REG_16 0x40 -#define PHY_REG_17 0x44 -#define PHY_REG_18 0x48 -#define PHY_REG_19 0x4c -#define PHY_REG_20 0x50 - -#define PHY_REG_21 0x54 -#define REG21_SEL_TX_CK_INV BIT(7) -#define REG21_PMS_S_MASK GENMASK(3, 0) - -#define PHY_REG_22 0x58 -#define PHY_REG_23 0x5c -#define PHY_REG_24 0x60 -#define PHY_REG_25 0x64 -#define PHY_REG_26 0x68 -#define PHY_REG_27 0x6c -#define PHY_REG_28 0x70 -#define PHY_REG_29 0x74 -#define PHY_REG_30 0x78 -#define PHY_REG_31 0x7c -#define PHY_REG_32 0x80 +#define PHY_REG(reg) (reg * 4) +#define REG12_CK_DIV_MASK GENMASK(5, 4) + +#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) + +#define REG14_TOL_MASK GENMASK(7, 4) +#define REG14_RP_CODE_MASK GENMASK(3, 1) +#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0) + +#define REG21_SEL_TX_CK_INV BIT(7) +#define REG21_PMS_S_MASK GENMASK(3, 0) /* * REG33 does not match the ref manual. According to Sandor Yu from NXP, * "There is a doc issue on the i.MX8MP latest RM" * REG33 is being used per guidance from Sandor */ +#define REG33_MODE_SET_DONE BIT(7) +#define REG33_FIX_DA BIT(1) -#define PHY_REG_33 0x84 -#define REG33_MODE_SET_DONE BIT(7) -#define REG33_FIX_DA BIT(1) - -#define PHY_REG_34 0x88 -#define REG34_PHY_READY BIT(7) -#define REG34_PLL_LOCK BIT(6) -#define REG34_PHY_CLK_READY BIT(5) - -#define PHY_REG_35 0x8c -#define PHY_REG_36 0x90 -#define PHY_REG_37 0x94 -#define PHY_REG_38 0x98 -#define PHY_REG_39 0x9c -#define PHY_REG_40 0xa0 -#define PHY_REG_41 0xa4 -#define PHY_REG_42 0xa8 -#define PHY_REG_43 0xac -#define PHY_REG_44 0xb0 -#define PHY_REG_45 0xb4 -#define PHY_REG_46 0xb8 -#define PHY_REG_47 0xbc +#define REG34_PHY_READY BIT(7) +#define REG34_PLL_LOCK BIT(6) +#define REG34_PHY_CLK_READY BIT(5) #define PHY_PLL_DIV_REGS_NUM 6 @@ -369,29 +322,29 @@ struct reg_settings { }; static const struct reg_settings common_phy_cfg[] = { - { PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 }, - { PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 }, - { PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 }, + { PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 }, + { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 }, + { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 }, /* REG12 pixclk specific */ /* REG13 pixclk specific */ /* REG14 pixclk specific */ - { PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c }, - { PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 }, - { PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 }, + { PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c }, + { PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 }, + { PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 }, /* REG21 pixclk specific */ - { PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 }, - { PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f }, - { PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 }, - { PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 }, - { PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 }, - { PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 }, - { PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 }, - { PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 }, - { PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 }, - { PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 }, - { PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f }, - { PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 }, - { PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 } + { PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 }, + { PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f }, + { PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 }, + { PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 }, + { PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 }, + { PHY_REG(32), 0x00 }, { PHY_REG(33), 0x80 }, + { PHY_REG(34), 0x00 }, { PHY_REG(35), 0x00 }, + { PHY_REG(36), 0x00 }, { PHY_REG(37), 0x00 }, + { PHY_REG(38), 0x00 }, { PHY_REG(39), 0x00 }, + { PHY_REG(40), 0x00 }, { PHY_REG(41), 0xe0 }, + { PHY_REG(42), 0x83 }, { PHY_REG(43), 0x0f }, + { PHY_REG(44), 0x3E }, { PHY_REG(45), 0xf8 }, + { PHY_REG(46), 0x00 }, { PHY_REG(47), 0x00 } }; struct fsl_samsung_hdmi_phy { @@ -442,7 +395,7 @@ fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, } writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), - phy->regs + PHY_REG_21); + phy->regs + PHY_REG(21)); } static void @@ -469,7 +422,7 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, break; } - writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12); + writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12)); /* * Calculation for the frequency lock detector target code (fld_tg_code) @@ -489,11 +442,11 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, /* FLD_TOL and FLD_RP_CODE taken from downstream driver */ writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code), - phy->regs + PHY_REG_13); + phy->regs + PHY_REG(13)); writeb(FIELD_PREP(REG14_TOL_MASK, 2) | FIELD_PREP(REG14_RP_CODE_MASK, 2) | FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8), - phy->regs + PHY_REG_14); + phy->regs + PHY_REG(14)); } static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, @@ -503,7 +456,7 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, u8 val; /* HDMI PHY init */ - writeb(REG33_FIX_DA, phy->regs + PHY_REG_33); + writeb(REG33_FIX_DA, phy->regs + PHY_REG(33)); /* common PHY registers */ for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++) @@ -511,14 +464,14 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, /* set individual PLL registers PHY_REG2 ... PHY_REG7 */ for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) - writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG_02 + i * 4); + writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); - writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33); + writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33)); - ret = readb_poll_timeout(phy->regs + PHY_REG_34, val, + ret = readb_poll_timeout(phy->regs + PHY_REG(34), val, val & REG34_PLL_LOCK, 50, 20000); if (ret) dev_err(phy->dev, "PLL failed to lock\n"); From patchwork Sat Sep 14 11:27:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13804380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40F6AC02191 for ; Sat, 14 Sep 2024 11:28:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Kd8y+4Trp6IV48kzLBxQb4QtZpVyn43LVGaXxgfE0n4=; b=kph1zIDB+D4ygP u7Ln+GB/ZQ7vXsjX4Q64/f3XkbIsLxkHDsUqGNkM1EVDjMgezCm08WczVK94gIhlVA1vwi2jqxNr3 KwH85haRRliq35p2Uz6K+DnOTeTW6+zQqNXHZ3hsVyrxzF8gK57yQEVddZrTvDP1JTrS5xHIqcCAa GjFpFzrM5dPJEyZRXr2d9maJKPGXwn7Bny/jo2bT7Q6n6WN7JuIl8OkZ3Kd7+5KLKcjBzHbVR/UD7 c+qBfcxb7SBWfC/6Twmyj69bhtKmOexep62gnZwl5GBOx6o1V5tjb7sf6fQAUi4g/+Cz8wHJQ6NZ0 YF+UtNXvMHMkJ5+jcPuA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1spQxC-00000000bUK-3VaX; Sat, 14 Sep 2024 11:28:38 +0000 Received: from mail-il1-x129.google.com ([2607:f8b0:4864:20::129]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1spQxA-00000000bSz-2gTK for linux-phy@lists.infradead.org; Sat, 14 Sep 2024 11:28:38 +0000 Received: by mail-il1-x129.google.com with SMTP id e9e14a558f8ab-3a08c5a2bddso8210385ab.2 for ; Sat, 14 Sep 2024 04:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726313315; x=1726918115; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tUqDak0O3QXqMSK46gM4L1oImDEknZFw9hO3+gSGP9E=; b=LYN/4tTD98OIzslNQ7UMPJSPK+EyzP5OOFbo2gPRpDQYPoiIhhc7kMYI9lKuRpVtnt K4NWt5G1EcdfcSt+mF/3ikyN4nrAIxOy6lhoj7KsHy8wYtw0c/OeLn7FY/rdMa/4HCGc 9oTmYHHRfybHfX8OE+3z+T2Ri/etNt4zw/M4dN7U8b70TG3B5ina+pGGhiuniGNVFCde DQR6HF4BRadalO8QYhuJIkLsKPHFCuwBV0nOYEtV/Whp6/bVPC89smd2udaCO1BVwpv4 FC1MJsLKSlwvFGZDHrrdU1Y4HKt93H+KPiL3XzvJJhgegWIgeJtwB30r24LmAfJVnXE8 S4ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726313315; x=1726918115; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tUqDak0O3QXqMSK46gM4L1oImDEknZFw9hO3+gSGP9E=; b=qcmvMB10pzDdMak1P+d0REfJ9iT7kD/tgOYGmBspS1YoTdrmMOW3JV/lJZD14L4h1h 3DA4tboEbB5AygPb/fDEh8RWdbhVMvq3KXPgL/6evPKHoKvsNfKuiUYWaQpPI+FCNkgD 0Q/bEa6RarFPWokF6kI18P+NUV7ar27BUK1aILb5TfZXBcmk5+pGZQ5mv5qHhkAXFsTq 5ELS/dM4/sYu6scEP9nY8RpJPhAdFK2nURMC/Hwh8VzaGFUfFngeA0r56FaPpxRuGgxQ yPWmSeuCSOvoB91/ltZtK1tGfGnHs6fMBiond56J82DkawTj+ihpDeuDe/01RG6tVx+g 5RsA== X-Gm-Message-State: AOJu0YxpJ3LEcNqmh7utX6aC0HGCNSy5wEba4femYlhttouJ097XW5uu sH7cNHiZk0nDTYeJwDmXiVeuneDDspr2LGtrWYwYRgWWgBJtopyMVoRh7g== X-Google-Smtp-Source: AGHT+IGtPFYjznHVWoDep8DJKi1LGKBj4gH/E/hrp7OfcL8Bw58Bk3unjUUFazFUIVuJuUFyjo2VvA== X-Received: by 2002:a05:6e02:1a0e:b0:39f:558a:e404 with SMTP id e9e14a558f8ab-3a0848ac716mr99880625ab.4.1726313315075; Sat, 14 Sep 2024 04:28:35 -0700 (PDT) Received: from aford-System-Version.lan (c-75-72-166-104.hsd1.mn.comcast.net. [75.72.166.104]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4d37ed35572sm350307173.131.2024.09.14.04.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Sep 2024 04:28:34 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, neil.armstrong@linaro.org, Adam Ford , Marco Felsch , Vinod Koul , Kishon Vijay Abraham I , Lucas Stach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-kernel@vger.kernel.org Subject: [PATCH V8 2/5] phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookup Date: Sat, 14 Sep 2024 06:27:46 -0500 Message-ID: <20240914112816.520224-3-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240914112816.520224-1-aford173@gmail.com> References: <20240914112816.520224-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240914_042836_699270_243FE3BB X-CRM114-Status: GOOD ( 10.87 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The value of 'S' is writen to two places, PHY_REG3[7:4] and PHY_REG21[3:0]. There is a lookup table which contains the value of PHY_REG3. Rather than using a switch statement based on the pixel clock to search for the value of 'S' again, just shift the contents of PHY_REG3[7:4] >> 4 and place the value in PHY_REG21[3:0]. Doing this can eliminate an entire function. Signed-off-by: Adam Ford Reviewed-by: Marco Felsch Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf Reviewed-by: Dominique Martinet Tested-by: Dominique Martinet --- V7: No Change V6: No Change --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 39 ++------------------ 1 file changed, 4 insertions(+), 35 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index acea7008aefc..4f6874226f9a 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -364,40 +364,6 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) return container_of(hw, struct fsl_samsung_hdmi_phy, hw); } -static void -fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, - const struct phy_config *cfg) -{ - u8 div = 0x1; - - switch (cfg->pixclk) { - case 22250000 ... 33750000: - div = 0xf; - break; - case 35000000 ... 40000000: - div = 0xb; - break; - case 43200000 ... 47500000: - div = 0x9; - break; - case 50349650 ... 63500000: - div = 0x7; - break; - case 67500000 ... 90000000: - div = 0x5; - break; - case 94000000 ... 148500000: - div = 0x3; - break; - case 154000000 ... 297000000: - div = 0x1; - break; - } - - writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), - phy->regs + PHY_REG(21)); -} - static void fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *cfg) @@ -466,7 +432,10 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); - fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); + /* High nibble of pll_div_regs[1] contains S which also gets written to REG21 */ + writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, + cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21)); + fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33)); From patchwork Sat Sep 14 11:27:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13804381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6D8FC02191 for ; Sat, 14 Sep 2024 11:28:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XRVgR9qlUA6NavH4Nb8nlcpZBdESGDaNu8O29kF2yaU=; b=bQOiXpg8XcZe4S ZSOv2gCOPYPkIVzA3JrC2rvszghl6NSjDQ6ACyjh3qUKRVJebWfZ15inOfqbLVeFncJQSVzzdD/Bs GwRQRTY7el2gprX4wkuPh6FpCvupoHGpZcDd4BCYBWyI+/haQwubh5yaxqZ5MSerkWOJxsXUwJZnN d3PXFeTk8roUrhb1hPhDLXbpUPz/GasuexC2aOTsujHfXYZhnwXKRFRBNy7d9LMdPjhbAeKA0STxp w+yVAB8tqNDmIMYuL//Up0wUfarGlIsQ8RXtxtU8g5aOTIlQSG7nxfL2taU1UiPCHWpT7DTB68R+4 hGMd9oGGlaj/O4g5E3lQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1spQxK-00000000bWS-1S9H; Sat, 14 Sep 2024 11:28:46 +0000 Received: from mail-io1-xd36.google.com ([2607:f8b0:4864:20::d36]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1spQxG-00000000bVk-3lRL for linux-phy@lists.infradead.org; Sat, 14 Sep 2024 11:28:45 +0000 Received: by mail-io1-xd36.google.com with SMTP id ca18e2360f4ac-82aef2c1e5fso63632739f.1 for ; Sat, 14 Sep 2024 04:28:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726313321; x=1726918121; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B9HxPAJshHdDvtOGJE9jxZxcZZCQzRJA0uViSfjtafg=; b=HK8coT5j+tczfjZIHwRP1w9AKjZ2IEq8FTxKX26i1EUjOMe5OWkXNATW2OTUNafrpV 0CmZ1Hc4nh2jaHJ8XVDhJbrBFIwVrq7eCaG/6/3kOs2GQFDvtaEVh6IZze47MFSHN3RJ /2Ke6t07SlhnKXTc18HHiAUKeK9XJx62vGT2CaxAbsZRg5HgjyseuXE2Dgsuo8Do/PQN rH1pnbz+n9Ufn6rptQjDoZDhT++zZXGuyk4Ey2GTtioiWrN40z2V5SRY+0lUmkufLpgC Aqx00Dm3iKd0LfR1eodFD643tUJ5QMIvbfujfbv3llFlGba0vKvqqE4E5/KE6zqFejs6 xGXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726313321; x=1726918121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B9HxPAJshHdDvtOGJE9jxZxcZZCQzRJA0uViSfjtafg=; b=stCsk8xv4BVhr6Eoks4da5cspsKtbh736JLR+JyvP2KtacPpXxwZhYpDLLdeADXXHj tVJQvhUaPclYEXmqzcAd54BkHNJCRdYS35u+58yEroXw7V0b5xTs/8ybIU3cFBhwZEh2 IqBWss4xc3Ni+FOdWxA8aBV5J0QEejRmB6Y3co9ZYwG3KiSD9TUxugZcfkayjImnYxpJ aZ4h8lKdg4w+lkEWiIH2hYmsr2n96o2ZLtB5Io9NHptGjqermzSLzI2RHUns7nSXJKJd Lv3Nv3SdzSIBjgjXpELUGPPFXVXw2m6DJytwIgIahnA3ENEtYTYJ1PRz43snxXIQSDml UbXg== X-Gm-Message-State: AOJu0Yz89ZY1sT6Y7/zHkIvv8155PX5nA1hTG/c81DF7t7N5L2GoRkyJ KN5bj2JOg8ZhRmVFZspXWgRkJsB+WA/BhJbTUl/IHKvc6liAZy03OviLBg== X-Google-Smtp-Source: AGHT+IE9iCn2Hniu9fo5kvOOtdcxCYiyTWsa6pOGJTLEz77gy4cXouFI/xiMSphckcnlNd35hZJkrw== X-Received: by 2002:a05:6e02:12e7:b0:3a0:8eb3:5160 with SMTP id e9e14a558f8ab-3a08eb35230mr38510585ab.11.1726313320714; Sat, 14 Sep 2024 04:28:40 -0700 (PDT) Received: from aford-System-Version.lan (c-75-72-166-104.hsd1.mn.comcast.net. [75.72.166.104]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4d37ed35572sm350307173.131.2024.09.14.04.28.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Sep 2024 04:28:40 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, neil.armstrong@linaro.org, Adam Ford , Vinod Koul , Kishon Vijay Abraham I , Marco Felsch , Lucas Stach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-kernel@vger.kernel.org Subject: [PATCH V8 3/5] phy: freescale: fsl-samsung-hdmi: Support dynamic integer Date: Sat, 14 Sep 2024 06:27:47 -0500 Message-ID: <20240914112816.520224-4-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240914112816.520224-1-aford173@gmail.com> References: <20240914112816.520224-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240914_042842_974261_62BE779A X-CRM114-Status: GOOD ( 18.44 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org There is currently a look-up table for a variety of resolutions. Since the phy has the ability to dynamically calculate the values necessary to use the intger divider which should allow more resolutions without having to update the look-up-table. If the lookup table cannot find an exact match, fall back to the dynamic calculator of the integer divider. Previously, the value of P was hard-coded to 1, this required an update to the phy_pll_cfg table to add in the extra value into the table, so if the value of P is calculated to be something else by the PMS calculator, the calculated_phy_pll_cfg structure can be used instead without having to keep track of which method was used. Signed-off-by: Adam Ford Reviewed-by: Dominique Martinet Tested-by: Dominique Martinet Reviewed-by: Frieder Schrempf --- V8: Fix VCO note and remove one goto by using a helper function V7: Refactored much of the code to create smaller helper functions to eliminate redundant code and improve code flow and comment readability. Any t-b and s-o-b tags removed due to the extent of the changes. V6: Fix comment typos and remove an unnecesary extra calculation by using the cached value. V5: No Change V4: No Change V3: Change size of pll_div_regs to include PHY_REG01 (P) Create calculated_phy_pll_cfg to containe the values Eliminate the PMS calculation from fsl_samsung_hdmi_phy_configure Make the LUT primary and fall back to integer calculator in phy_clk_round_rate. Check the range right away to ensure it's reaonsable rather than trying to find a clock only to learn it's outside the range. Overall added notes and comments where stuff may not be intuitive. V2: Update phy_clk_round_rate and phy_clk_set_rate to both support the integer clock PMS calculator. --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 377 +++++++++++++------ 1 file changed, 270 insertions(+), 107 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 4f6874226f9a..029de69fbeaf 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -16,6 +16,8 @@ #define PHY_REG(reg) (reg * 4) +#define REG01_PMS_P_MASK GENMASK(3, 0) +#define REG03_PMS_S_MASK GENMASK(7, 4) #define REG12_CK_DIV_MASK GENMASK(5, 4) #define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) @@ -38,281 +40,296 @@ #define REG34_PLL_LOCK BIT(6) #define REG34_PHY_CLK_READY BIT(5) -#define PHY_PLL_DIV_REGS_NUM 6 +#ifndef MHZ +#define MHZ (1000UL * 1000UL) +#endif + +#define PHY_PLL_DIV_REGS_NUM 7 struct phy_config { u32 pixclk; u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM]; }; +/* + * The calculated_phy_pll_cfg only handles integer divider for PMS, + * meaning the last four entries will be fixed, but the first three will + * be calculated by the PMS calculator. + */ +static struct phy_config calculated_phy_pll_cfg = { + .pixclk = 0, + .pll_div_regs = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 }, +}; + +/* The lookup table contains values for which the fractional divder is used */ static const struct phy_config phy_pll_cfg[] = { { .pixclk = 22250000, - .pll_div_regs = { 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 }, }, { .pixclk = 23750000, - .pll_div_regs = { 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, }, { .pixclk = 24000000, - .pll_div_regs = { 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 24024000, - .pll_div_regs = { 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, }, { .pixclk = 25175000, - .pll_div_regs = { 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, }, { .pixclk = 25200000, - .pll_div_regs = { 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 26750000, - .pll_div_regs = { 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, }, { .pixclk = 27000000, - .pll_div_regs = { 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 27027000, - .pll_div_regs = { 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk = 29500000, - .pll_div_regs = { 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, }, { .pixclk = 30750000, - .pll_div_regs = { 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, + .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, }, { .pixclk = 30888000, - .pll_div_regs = { 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, + .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, }, { .pixclk = 33750000, - .pll_div_regs = { 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk = 35000000, - .pll_div_regs = { 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, }, { .pixclk = 36000000, - .pll_div_regs = { 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 36036000, - .pll_div_regs = { 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk = 40000000, - .pll_div_regs = { 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 43200000, - .pll_div_regs = { 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 43243200, - .pll_div_regs = { 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk = 44500000, - .pll_div_regs = { 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, + .pll_div_regs = { 0xd1, 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, }, { .pixclk = 47000000, - .pll_div_regs = { 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, }, { .pixclk = 47500000, - .pll_div_regs = { 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, }, { .pixclk = 50349650, - .pll_div_regs = { 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, }, { .pixclk = 50400000, - .pll_div_regs = { 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 53250000, - .pll_div_regs = { 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, + .pll_div_regs = { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, }, { .pixclk = 53500000, - .pll_div_regs = { 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, }, { .pixclk = 54000000, - .pll_div_regs = { 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 54054000, - .pll_div_regs = { 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk = 59000000, - .pll_div_regs = { 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, }, { .pixclk = 59340659, - .pll_div_regs = { 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, + .pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, }, { .pixclk = 59400000, - .pll_div_regs = { 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 61500000, - .pll_div_regs = { 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, + .pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, }, { .pixclk = 63500000, - .pll_div_regs = { 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk = 67500000, - .pll_div_regs = { 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 }, }, { .pixclk = 70000000, - .pll_div_regs = { 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, }, { .pixclk = 72000000, - .pll_div_regs = { 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 72072000, - .pll_div_regs = { 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk = 74176000, - .pll_div_regs = { 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, + .pll_div_regs = { 0xd1, 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, }, { .pixclk = 74250000, - .pll_div_regs = { 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, + .pll_div_regs = { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, }, { .pixclk = 78500000, - .pll_div_regs = { 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, }, { .pixclk = 80000000, - .pll_div_regs = { 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 82000000, - .pll_div_regs = { 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, + .pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, }, { .pixclk = 82500000, - .pll_div_regs = { 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, + .pll_div_regs = { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, }, { .pixclk = 89000000, - .pll_div_regs = { 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, }, { .pixclk = 90000000, - .pll_div_regs = { 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk = 94000000, - .pll_div_regs = { 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 }, }, { .pixclk = 95000000, - .pll_div_regs = { 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 }, }, { .pixclk = 98901099, - .pll_div_regs = { 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 }, + .pll_div_regs = { 0xd1, 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 }, }, { .pixclk = 99000000, - .pll_div_regs = { 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, + .pll_div_regs = { 0xd1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, }, { .pixclk = 100699300, - .pll_div_regs = { 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, }, { .pixclk = 100800000, - .pll_div_regs = { 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 102500000, - .pll_div_regs = { 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, + .pll_div_regs = { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, }, { .pixclk = 104750000, - .pll_div_regs = { 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 }, + .pll_div_regs = { 0xd1, 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 }, }, { .pixclk = 106500000, - .pll_div_regs = { 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 }, + .pll_div_regs = { 0xd1, 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 }, }, { .pixclk = 107000000, - .pll_div_regs = { 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, }, { .pixclk = 108000000, - .pll_div_regs = { 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 108108000, - .pll_div_regs = { 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk = 118000000, - .pll_div_regs = { 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, }, { .pixclk = 118800000, - .pll_div_regs = { 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 123000000, - .pll_div_regs = { 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, + .pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, }, { .pixclk = 127000000, - .pll_div_regs = { 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk = 135000000, - .pll_div_regs = { 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk = 135580000, - .pll_div_regs = { 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b }, + .pll_div_regs = { 0xd1, 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b }, }, { .pixclk = 137520000, - .pll_div_regs = { 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, + .pll_div_regs = { 0xd1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, }, { .pixclk = 138750000, - .pll_div_regs = { 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, + .pll_div_regs = { 0xd1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, }, { .pixclk = 140000000, - .pll_div_regs = { 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, }, { .pixclk = 144000000, - .pll_div_regs = { 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 148352000, - .pll_div_regs = { 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, + .pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, }, { .pixclk = 148500000, - .pll_div_regs = { 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, + .pll_div_regs = { 0xd1, 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, }, { .pixclk = 154000000, - .pll_div_regs = { 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, + .pll_div_regs = { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, }, { .pixclk = 157000000, - .pll_div_regs = { 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, }, { .pixclk = 160000000, - .pll_div_regs = { 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 }, }, { .pixclk = 162000000, - .pll_div_regs = { 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 }, + .pll_div_regs = { 0xd1, 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 }, }, { .pixclk = 164000000, - .pll_div_regs = { 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b }, + .pll_div_regs = { 0xd1, 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b }, }, { .pixclk = 165000000, - .pll_div_regs = { 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, + .pll_div_regs = { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, }, { .pixclk = 180000000, - .pll_div_regs = { 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 185625000, - .pll_div_regs = { 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, }, { .pixclk = 188000000, - .pll_div_regs = { 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 }, }, { .pixclk = 198000000, - .pll_div_regs = { 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 }, + .pll_div_regs = { 0xd1, 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 }, }, { .pixclk = 205000000, - .pll_div_regs = { 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b }, + .pll_div_regs = { 0xd1, 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b }, }, { .pixclk = 209500000, - .pll_div_regs = { 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 }, + .pll_div_regs = { 0xd1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 }, }, { .pixclk = 213000000, - .pll_div_regs = { 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, + .pll_div_regs = { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, }, { .pixclk = 216000000, - .pll_div_regs = { 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 216216000, - .pll_div_regs = { 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk = 237600000, - .pll_div_regs = { 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 254000000, - .pll_div_regs = { 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, + .pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk = 277500000, - .pll_div_regs = { 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, + .pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, }, { .pixclk = 288000000, - .pll_div_regs = { 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, + .pll_div_regs = { 0xd1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 297000000, - .pll_div_regs = { 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, + .pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, }, }; @@ -322,7 +339,8 @@ struct reg_settings { }; static const struct reg_settings common_phy_cfg[] = { - { PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 }, + { PHY_REG(0), 0x00 }, + /* PHY_REG(1-7) pix clk specific */ { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 }, { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 }, /* REG12 pixclk specific */ @@ -415,6 +433,83 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, phy->regs + PHY_REG(14)); } +static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s) +{ + unsigned long best_freq = 0; + u32 min_delta = 0xffffffff; + u8 _p, best_p; + u16 _m, best_m; + u8 _s, best_s; + + /* + * Figure 13-78 of the reference manual states the PLL should be TMDS x 5 + * while the TMDS_CLKO should be the PLL / 5. So to calculate the PLL, + * take the pix clock x 5, then return the value of the PLL / 5. + */ + fout *= 5; + + /* The ref manual states the values of 'P' range from 1 to 11 */ + for (_p = 1; _p <= 11; ++_p) { + for (_s = 1; _s <= 16; ++_s) { + u64 tmp; + u32 delta; + + /* s must be one or even */ + if (_s > 1 && (_s & 0x01) == 1) + _s++; + + /* _s cannot be 14 per the TRM */ + if (_s == 14) + continue; + + /* + * TODO: Ref Manual doesn't state the range of _m + * so this should be further refined if possible. + * This range was set based on the original values + * in the lookup table + */ + tmp = (u64)fout * (_p * _s); + do_div(tmp, 24 * MHZ); + _m = tmp; + if (_m < 0x30 || _m > 0x7b) + continue; + + /* + * Rev 2 of the Ref Manual states the + * VCO can range between 750MHz and + * 3GHz. The VCO is assumed to be + * Fvco = (M * f_ref) / P, + * where f_ref is 24MHz. + */ + tmp = (u64)_m * 24 * MHZ; + do_div(tmp, _p); + if (tmp < 750 * MHZ || + tmp > 3000 * MHZ) + continue; + + /* Final frequency after post-divider */ + do_div(tmp, _s); + + delta = abs(fout - tmp); + if (delta < min_delta) { + best_p = _p; + best_s = _s; + best_m = _m; + min_delta = delta; + best_freq = tmp; + } + } + } + + if (best_freq) { + *p = best_p; + *m = best_m; + *s = best_s; + } + + return best_freq / 5; +} + static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *cfg) { @@ -428,13 +523,13 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++) writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg); - /* set individual PLL registers PHY_REG2 ... PHY_REG7 */ + /* set individual PLL registers PHY_REG1 ... PHY_REG7 */ for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) - writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4); + writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(1) + i * 4); - /* High nibble of pll_div_regs[1] contains S which also gets written to REG21 */ + /* High nibble of PHY_REG3 and low nibble of PHY_REG21 both contain 'S' */ writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, - cfg->pll_div_regs[1] >> 4), phy->regs + PHY_REG(21)); + cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21)); fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); @@ -459,34 +554,102 @@ static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, return phy->cur_cfg->pixclk; } -static long phy_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) +/* Helper function to lookup the available fractional-divider rate */ +static const struct phy_config *fsl_samsung_hdmi_phy_lookup_rate(unsigned long rate) { int i; + /* Search the lookup table */ for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) if (phy_pll_cfg[i].pixclk <= rate) - return phy_pll_cfg[i].pixclk; + break; + + return &phy_pll_cfg[i]; +} + +static void fsl_samsung_hdmi_calculate_phy(struct phy_config *cal_phy, unsigned long rate, + u8 p, u16 m, u8 s) +{ + cal_phy->pixclk = rate; + cal_phy->pll_div_regs[0] = FIELD_PREP(REG01_PMS_P_MASK, p); + cal_phy->pll_div_regs[1] = m; + cal_phy->pll_div_regs[2] = FIELD_PREP(REG03_PMS_S_MASK, s-1); + /* pll_div_regs 3-6 are fixed and pre-defined already */ +} + +static long phy_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + const struct phy_config *fract_div_phy; + u32 int_div_clk; + u16 m; + u8 p, s; + + /* If the clock is out of range return error instead of searching */ + if (rate > 297000000 || rate < 22250000) + return -EINVAL; + + /* Search the fractional divider lookup table */ + fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate); - return -EINVAL; + /* If the rate is an exact match, return that value */ + if (rate == fract_div_phy->pixclk) + return fract_div_phy->pixclk; + + /* If the exact match isn't found, calculate the integer divider */ + int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s); + + /* If the int_div_clk rate is an exact match, return that value */ + if (int_div_clk == rate) + return int_div_clk; + + /* If neither rate is an exact match, use the value from the LUT */ + return fract_div_phy->pixclk; +} + +static int phy_use_fract_div(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *fract_div_phy) +{ + phy->cur_cfg = fract_div_phy; + dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider rate = %u\n", + phy->cur_cfg->pixclk); + return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); } static int phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); - int i; + const struct phy_config *fract_div_phy; + u32 int_div_clk; + u16 m; + u8 p, s; - for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) - if (phy_pll_cfg[i].pixclk <= rate) - break; + /* Search the fractional divider lookup table */ + fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate); - if (i < 0) - return -EINVAL; + /* If the rate is an exact match, use that value */ + if (fract_div_phy->pixclk == rate) + return phy_use_fract_div(phy, fract_div_phy); - phy->cur_cfg = &phy_pll_cfg[i]; + /* + * If the rate from the fractional divider is not exact, check the integer divider, + * and use it if that value is an exact match. + */ + int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s); + if (int_div_clk == rate) { + dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate = %u\n", + int_div_clk); + + fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m, s); + phy->cur_cfg = &calculated_phy_pll_cfg; + return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); + } - return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); + /* + * If neither the fractional divider nor the integer divider can find an exact value + * fall back to using the fractional divider + */ + return phy_use_fract_div(phy, fract_div_phy); } static const struct clk_ops phy_clk_ops = { From patchwork Sat Sep 14 11:27:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13804382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7271C02191 for ; Sat, 14 Sep 2024 11:28:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KtpAmy9e0F518NaAqPR6lRdysTDX6jaBwxDAi+Eyia8=; b=l25YQ2KOGpMEJK q0lHurVGJi72ME86M1q2tsRCuTfW2avnIUyZhvidiCEjUvnAUHAYQFEG16xMDoTDvnVGhmC69snHZ smCuu+E2JDNbjgeWNMrlHijQF0p/P1ImrFcKD5FqPdToT/rYTGfxJ86iSpGfa9Ka1Oc7OoOyMSK40 Y1t2v4DPClaDPM4FZpigLFT1Rt0Jx0cm9fjEMVTvW2j/cV3P0DslKDIyBPmjWr4XQoqqkIp82TT7J KIycOl+2Xhh8Q7x65tIzO5ZvH2NM58MWt6oTbrVvDmO4L9qUJ66vtCJDHu3QzTCrizCcdOS8mFK62 VQJwvbbrtNeiKOJrKyyA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1spQxO-00000000bXL-07Pu; Sat, 14 Sep 2024 11:28:50 +0000 Received: from mail-il1-x136.google.com ([2607:f8b0:4864:20::136]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1spQxM-00000000bWr-0Heb for linux-phy@lists.infradead.org; Sat, 14 Sep 2024 11:28:49 +0000 Received: by mail-il1-x136.google.com with SMTP id e9e14a558f8ab-39f54ab8e69so13357405ab.1 for ; Sat, 14 Sep 2024 04:28:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726313326; x=1726918126; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8xV6n2xfd+FaMO8WaO3/5kzB5Pnz5Y6CJYYgXfk9V5E=; b=iSAibDOPGZRUkVWrmLOlZexnswficxsCuo2O8iTJM5GeE1maB/Mdq7aXiHmi4WXocZ ixzPy6y9GfAcbG56N8U0DxQI6G4lnKoXFiptVC27axLiFIXmOjF5tcvDKsxgN2OJ6eUd xdcDbC6QOP3XFQEwxKpJATxn7dGjlDjhM3F0j/J/C/Kgsn/DaIHp45al8S7gKiTlgg03 0RHdEKaOsbgv0+Q9d+0wJGa+f+j4yoxYzxRYDNviMUu1tbdJrQOb6Tyusi6pag6sGO3T y0o0n2yPvSiKEz/PxDhnRcvfvW20jr1uQYNgPGXdxid4GB/V8jgs28/kKPwtFxK4XqGc iR0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726313326; x=1726918126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8xV6n2xfd+FaMO8WaO3/5kzB5Pnz5Y6CJYYgXfk9V5E=; b=qMIBkfCRPAhokcTvFIwp2KQc3a4XtGKganZ6vae3s/GSspvGMu76YPZFLUZh/EYWHk xWJdqhKTllBLRw0ISg3DzR2chclCoAz/eEYyY/U9is6vJjy/iPIiRWA+jQryUCUfufH1 WmkEq25DbW1TQpDkwx/JLPCbU4bnu84nnY4mOORuBvSwAkJAS2Vvkp+wVdiBHIAD+Or7 ulVMbX5Oqz08UwBAJ15ZnWGiSSCCAvNuJsabpOlhu7YyZqk4GXWMLJ8/lsrvPFQ4kPKU hTte+2L1s3I9UqGO1Lo4b18eSf42UCIGmcr8H0mAQQ2EwY2+TGFbQUBxOAOU3zdTepq7 Wz7w== X-Gm-Message-State: AOJu0YzFx2ku3b/un50cWaK4lwnbFs2W5Kqby6GUim0B2aKJalVTTncu 3L6HEbYLDf1QLyqRMLu2fV/6Iz5ExB5lbE/xb09BR+xSD7yePf7hei7Z3g== X-Google-Smtp-Source: AGHT+IG0kreIWwWBWw+JlyvPmBrdaLkQSyVHwsDgbT6YhqxbLTJUYIJBECAP9is+NklLbzzo8R1hJg== X-Received: by 2002:a05:6e02:1547:b0:375:a3eb:bfcd with SMTP id e9e14a558f8ab-3a074c642f5mr114413285ab.8.1726313326421; Sat, 14 Sep 2024 04:28:46 -0700 (PDT) Received: from aford-System-Version.lan (c-75-72-166-104.hsd1.mn.comcast.net. [75.72.166.104]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4d37ed35572sm350307173.131.2024.09.14.04.28.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Sep 2024 04:28:45 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, neil.armstrong@linaro.org, Adam Ford , Vinod Koul , Kishon Vijay Abraham I , Marco Felsch , Lucas Stach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-kernel@vger.kernel.org Subject: [PATCH V8 4/5] phy: freescale: fsl-samsung-hdmi: Use closest divider Date: Sat, 14 Sep 2024 06:27:48 -0500 Message-ID: <20240914112816.520224-5-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240914112816.520224-1-aford173@gmail.com> References: <20240914112816.520224-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240914_042848_131330_639C758E X-CRM114-Status: GOOD ( 20.74 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Currently, if the clock values cannot be set to the exact rate, the round_rate and set_rate functions use the closest value found in the look-up-table. In preparation of removing values from the LUT that can be calculated evenly with the integer calculator, it's necessary to ensure to check both the look-up-table and the integer divider clock values to get the closest values to the requested value. It does this by measuring the difference between the requested clock value and the closest value in both integer divider calucator and the fractional clock look-up-table. Which ever has the smallest difference between them is returned as the closest rate. Signed-off-by: Adam Ford Reviewed-by: Dominique Martinet Tested-by: Dominique Martinet Reviewed-by: Frieder Schrempf --- V8: Replace Goto statement with calls to helper functions use ABS for both integer and fractional divider entries. V7: Because of the previous patch refactoring, the flow of this patch changed quite a bit to use more help functions and goto statements to hopefully make the code flow better and improve comment readability. Because of the change, I removed s-o-b and r-b, and t-b tags. V6: Simplify the calculation of the closest rate and fix a situation where the integer divider values may not be properly setup before they are used. Fixup some comments V5: No Change V4: New to series --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 40 ++++++++++++++------ 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 029de69fbeaf..381742e8b618 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -577,6 +577,16 @@ static void fsl_samsung_hdmi_calculate_phy(struct phy_config *cal_phy, unsigned /* pll_div_regs 3-6 are fixed and pre-defined already */ } +static u32 fsl_samsung_hdmi_phy_get_closest_rate(unsigned long rate, + u32 int_div_clk, u32 frac_div_clk) +{ + /* Calculate the absolute value of the differences and return whichever is closest */ + if (abs((long)rate - (long)int_div_clk) < abs((long)(rate - (long)frac_div_clk))) + return int_div_clk; + + return frac_div_clk; +} + static long phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { @@ -615,6 +625,15 @@ static int phy_use_fract_div(struct fsl_samsung_hdmi_phy *phy, const struct phy_ return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); } +static int phy_use_integer_div(struct fsl_samsung_hdmi_phy *phy, + const struct phy_config *int_div_clk) +{ + phy->cur_cfg = &calculated_phy_pll_cfg; + dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate = %u\n", + phy->cur_cfg->pixclk); + return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); +} + static int phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -636,20 +655,19 @@ static int phy_clk_set_rate(struct clk_hw *hw, * and use it if that value is an exact match. */ int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s); - if (int_div_clk == rate) { - dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate = %u\n", - int_div_clk); - - fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m, s); - phy->cur_cfg = &calculated_phy_pll_cfg; - return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); - } + fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m, s); + if (int_div_clk == rate) + return phy_use_integer_div(phy, &calculated_phy_pll_cfg); /* - * If neither the fractional divider nor the integer divider can find an exact value - * fall back to using the fractional divider + * Compare the difference between the integer clock and the fractional clock against + * the desired clock and which whichever is closest. */ - return phy_use_fract_div(phy, fract_div_phy); + if (fsl_samsung_hdmi_phy_get_closest_rate(rate, int_div_clk, + fract_div_phy->pixclk) == fract_div_phy->pixclk) + return phy_use_fract_div(phy, fract_div_phy); + else + return phy_use_integer_div(phy, &calculated_phy_pll_cfg); } static const struct clk_ops phy_clk_ops = { From patchwork Sat Sep 14 11:27:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13804383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BC2EC02190 for ; Sat, 14 Sep 2024 11:29:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sC7boK3OiGfd2UpKB9wuTDwEOVjYsMTqt/mWRHddsNo=; b=1VLfNu2tfY49WU 7VdK1bu04xdpGGkeisU49bnXRc84xQIuptOTjzqqG3MuVBNMZDh266G5XjCkZzrZ6ZgOjhR8zl7Fm Sd/fx8Bc34/aPT30ELiG/D8Vk8Cu5zxf7ym36iItQCpdoHKEr4bN09+8JIM2grAUfrEs45ftTshV/ TV4WfkRrDiUg1sW7yFrcCYn8eprGEe2khdxGu7BBoYqEhaxdFB1p4weL62RZJsvhkqNnKfPxKyrMj Ay5Z7ekVQUeWbSIPNFoO+IfxWLK7HYjcPGKNgo2sqtJ6wPbkov4/Qiw2ZLbXD2Ha0b6s0IkCyJpqe 8skYh6C0WmzMl//du0xA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1spQxa-00000000baL-0K2L; Sat, 14 Sep 2024 11:29:02 +0000 Received: from mail-il1-x12a.google.com ([2607:f8b0:4864:20::12a]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1spQxR-00000000bYv-0sAS for linux-phy@lists.infradead.org; Sat, 14 Sep 2024 11:29:01 +0000 Received: by mail-il1-x12a.google.com with SMTP id e9e14a558f8ab-3a0981e63ecso2560595ab.2 for ; Sat, 14 Sep 2024 04:28:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726313332; x=1726918132; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sSOtDV13EsH13T8HUC8031Ji7hP36lxfaxCfZokXgSE=; b=mDksaa6Xkek/gvHlMGsa56iCNNOGnqh1ywmaTcMLCEhKwbsBEC+mHiG3VJ0vTnJTe1 6ppX8x2CVBvsfPiEfPnPrv1+dkGj4AKyw3vNPLBCt2Epi7SNtk98dnor3pYZ5swT6sDY 17ARhl5LcHrGxftz4rRQUc4nrT9MG4m2J5K+Oa0ITd5hN9GBVrfNuQLAOpp5WwP8Lafa 4P4PcHM52LQpvdPqKcMWi6XJ4OsklN7AE4LLlmbPV7hNnb+PfGFGTilAYX2PD+S6ZrzL 0lrn0QtMrEcJZSzE/2OuWc5HbTbpP9NzMQb5t+cWVD14nC5WMPQzxVWL+SNROUDfY2L9 GHTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726313332; x=1726918132; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sSOtDV13EsH13T8HUC8031Ji7hP36lxfaxCfZokXgSE=; b=Bm7bpHTDLkx4kRVRcdXz5ZihugJst4LX100SzmlFFs0f20l3QBu391X6Orn0vi4K+r YoOUISVreOIRMjD/fnt2OxjWW0KRpRDCVcGplTqanB7iNV8liLSTGLabUKXbW1zUiDg3 2pcYWkEhPvVoSh+4gvILY5CUu2t4oUduirLmBmZos/BA5HRqboxrTD19RE30KfUmDZjG ZlHfqTuY4ct6Gq8LKtrToaB5wfPNSPRhjjRvqmJGzrtO6CwI2pTGGWswDjLGCNDKHr96 ZYxCnpHEQ8nFPcAK97NiSfXX6N+dBO0DID3XpF/pQvEt0fyEcyytcSzCf2S2PdX4vPfV e7Kg== X-Gm-Message-State: AOJu0Yyah5EqexXiQ0tBt6yYL2Bev/i7ai4ETu/rgErFoXHBZ5tfMYR2 QpNqfTz6EPto8tV1sM9mxwwJ0QN2u8QgpoGe7PyuHUdFZYV8bFy91wvd6A== X-Google-Smtp-Source: AGHT+IGe3qB/5u0s66kBMwo65iRp4B8oJ43nXLtmCTfmLkCisrIx/PFxw2b3CNp6PXdUB11UXzOWgw== X-Received: by 2002:a05:6e02:1fce:b0:39d:323d:89b2 with SMTP id e9e14a558f8ab-3a08495e116mr104995395ab.26.1726313331931; Sat, 14 Sep 2024 04:28:51 -0700 (PDT) Received: from aford-System-Version.lan (c-75-72-166-104.hsd1.mn.comcast.net. [75.72.166.104]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4d37ed35572sm350307173.131.2024.09.14.04.28.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Sep 2024 04:28:51 -0700 (PDT) From: Adam Ford To: linux-phy@lists.infradead.org Cc: dominique.martinet@atmark-techno.com, linux-imx@nxp.com, festevam@gmail.com, frieder.schrempf@kontron.de, aford@beaconembedded.com, Sandor.yu@nxp.com, neil.armstrong@linaro.org, Adam Ford , Vinod Koul , Kishon Vijay Abraham I , Marco Felsch , Lucas Stach , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-kernel@vger.kernel.org Subject: [PATCH V8 5/5] phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entries Date: Sat, 14 Sep 2024 06:27:49 -0500 Message-ID: <20240914112816.520224-6-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240914112816.520224-1-aford173@gmail.com> References: <20240914112816.520224-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240914_042853_272184_2EBCFC26 X-CRM114-Status: GOOD ( 10.38 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The lookup table contains entries which use the integer divider instead of just the fractional divider. Since the set and round functions check both the integer divider values and the LUT values, it's no longer necessary to keep the integer divider values in the lookup table, as can be dynamically calcuated. Signed-off-by: Adam Ford Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf Reviewed-by: Dominique Martinet Tested-by: Dominique Martinet --- V8: No change V7: No Change V6: Fix typos in commit message V5: No Change V4: New to series --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 83 +++----------------- 1 file changed, 13 insertions(+), 70 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 381742e8b618..a08c1bfa657c 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -69,25 +69,16 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 23750000, .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, - }, { - .pixclk = 24000000, - .pll_div_regs = { 0xd1, 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 24024000, .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, }, { .pixclk = 25175000, .pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, - }, { - .pixclk = 25200000, - .pll_div_regs = { 0xd1, 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 26750000, .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 27000000, - .pll_div_regs = { 0xd1, 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 27027000, .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, }, { @@ -105,18 +96,9 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 35000000, .pll_div_regs = { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 36000000, - .pll_div_regs = { 0xd1, 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 36036000, .pll_div_regs = { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk = 40000000, - .pll_div_regs = { 0xd1, 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, - }, { - .pixclk = 43200000, - .pll_div_regs = { 0xd1, 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 43243200, .pll_div_regs = { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, @@ -132,19 +114,13 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 50349650, .pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, - }, { - .pixclk = 50400000, - .pll_div_regs = { 0xd1, 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 53250000, .pll_div_regs = { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, }, { .pixclk = 53500000, .pll_div_regs = { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 54000000, - .pll_div_regs = { 0xd1, 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 54054000, .pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, }, { @@ -153,10 +129,7 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 59340659, .pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, - }, { - .pixclk = 59400000, - .pll_div_regs = { 0xd1, 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 61500000, .pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, }, { @@ -168,10 +141,7 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 70000000, .pll_div_regs = { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 72000000, - .pll_div_regs = { 0xd1, 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 72072000, .pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, }, { @@ -183,10 +153,7 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 78500000, .pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, - }, { - .pixclk = 80000000, - .pll_div_regs = { 0xd1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 82000000, .pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, }, { @@ -213,10 +180,7 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 100699300, .pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, - }, { - .pixclk = 100800000, - .pll_div_regs = { 0xd1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 102500000, .pll_div_regs = { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, }, { @@ -228,19 +192,13 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 107000000, .pll_div_regs = { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, - }, { - .pixclk = 108000000, - .pll_div_regs = { 0xd1, 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 108108000, .pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, }, { .pixclk = 118000000, .pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, - }, { - .pixclk = 118800000, - .pll_div_regs = { 0xd1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 123000000, .pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, }, { @@ -261,10 +219,7 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 140000000, .pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, - }, { - .pixclk = 144000000, - .pll_div_regs = { 0xd1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 148352000, .pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, }, { @@ -288,9 +243,6 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 165000000, .pll_div_regs = { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, - }, { - .pixclk = 180000000, - .pll_div_regs = { 0xd1, 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 185625000, .pll_div_regs = { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, @@ -309,25 +261,16 @@ static const struct phy_config phy_pll_cfg[] = { }, { .pixclk = 213000000, .pll_div_regs = { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, - }, { - .pixclk = 216000000, - .pll_div_regs = { 0xd1, 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, }, { .pixclk = 216216000, .pll_div_regs = { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, - }, { - .pixclk = 237600000, - .pll_div_regs = { 0xd1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 254000000, .pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk = 277500000, .pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, - }, { - .pixclk = 288000000, - .pll_div_regs = { 0xd1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, - }, { + }, { .pixclk = 297000000, .pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, },