From patchwork Mon Sep 16 09:49:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13805230 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EB10152E0C; Mon, 16 Sep 2024 09:50:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726480238; cv=none; b=S1pfIZhmdqDseD5AIxcemuILz9+vP3grH5LDEcOkPRDydr+UKuymjZsoktKoz3R45nj/+lOWK0SYu/HZdYMLW/qD07VrGiaCEVCAmaBI6e/sFWF54ztFgcCc8MBWh8xzwbZQH5PP/bOSDu5sIJw3v/slu4+9RokL5dY3ISx0EJE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726480238; c=relaxed/simple; bh=7bl2ZEDuC0zZI5FlRxCu17AXg0qnwONuc0subfjdRWI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=apMrwY3x7D2geM5ApBYMiZZ9wMrj+qrWbbKwd0vfdEOCZd3+VJmXXimlhffF2dF59BCgtfFu385+QYCz36HV1kNXnzd5iy6hGqM+/R03CaR46R44XocB/ztezWK0ZxiDMGpt1mhZK+yc6W/WAQnWgKtG4Cp+Kr1UtPOCQv6FE38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=TV9Rcxu9; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="TV9Rcxu9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1726480236; x=1758016236; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=7bl2ZEDuC0zZI5FlRxCu17AXg0qnwONuc0subfjdRWI=; b=TV9Rcxu9ajbB49QC7jp0UjGa2PrusVVQeGANR8HyVUX7dvT9KSELZ5i+ yYtpQkx5F+wychjL5922h5QKhmog8m88aFYi5d9vtz4EkCqFG8jKlItJ/ zwjJAoqWlsGSUiLcxTHzcfucsool9dpocfaw9RzXRqWHc7/haANHNYals Wfh1oPPPyxmjK73t6XfgdE1wFwyxhm/fAU9eb/aXKG5e+fw5mzX4slpoP GNT5cj0UOLp08+cUr25+aib/SIVYuldskAv2Mz0RlQTSsGBEwaOIoyNCp 0kh9GSsttJeQFon91U4H0A8lWvCQwQhTCTpwuo++r2CpkYN3Q7X83Z14o Q==; X-CSE-ConnectionGUID: FMt8JCZwTJSUmtKKgkwdXA== X-CSE-MsgGUID: 1t0XNRlTShmtFNu1yaLadg== X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="199259963" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 16 Sep 2024 02:50:35 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 16 Sep 2024 02:50:16 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 16 Sep 2024 02:50:14 -0700 From: Daniel Machon Date: Mon, 16 Sep 2024 11:49:19 +0200 Subject: [PATCH 1/4] dt-bindings: clock: add support for lan969x Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240916-lan969x-clock-v1-1-0e150336074d@microchip.com> References: <20240916-lan969x-clock-v1-0-0e150336074d@microchip.com> In-Reply-To: <20240916-lan969x-clock-v1-0-0e150336074d@microchip.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kavyasree Kotagiri , Steen Hegelund , Horatiu Vultur CC: , , X-Mailer: b4 0.14-dev Lan969x is going to reuse the existing lan966x clock driver - document that by adding compatible strings for the different SKU's that we support. Signed-off-by: Daniel Machon Acked-by: Conor Dooley --- .../devicetree/bindings/clock/microchip,lan966x-gck.yaml | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml index df2bec188706..16106e8b637f 100644 --- a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml @@ -16,7 +16,18 @@ description: | properties: compatible: - const: microchip,lan966x-gck + oneOf: + - enum: + - microchip,lan966x-gck + - microchip,lan9691-gck + - items: + - enum: + - microchip,lan9698-gck + - microchip,lan9696-gck + - microchip,lan9694-gck + - microchip,lan9693-gck + - microchip,lan9692-gck + - const: microchip,lan9691-gck reg: minItems: 1 From patchwork Mon Sep 16 09:49:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13805231 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42FE914B07A; Mon, 16 Sep 2024 09:50:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726480239; cv=none; b=ZardCDoHH4NzLAyXMAaRQiriyn9c4lSa7GAFK9fsZzohd+aWgYJN0XAvLW6h55lvB3XmT+oIAXUAfIDNemh22sIspA1Yis80WLC/+qcT9/76q9HLHzU1Q2isvpq/hWdMOUMPh5aDV/rmjRGq02MfLv9+I8pxl8SAjBUwt+xLfp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726480239; c=relaxed/simple; bh=IMTQEf/JsEhNn9hxmAfyuprjfemrvmpeaN0K8J1Fyo4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ttQ0D587mo/yPJtQcnZDxh9cDeh8FDDBEslgMBmmnl0p7Ba3Fl9Ybrj+YdyIxCb0xNmkGSj5bToTvTRzV+xqPc+GZfMpVsdceOS1pXYLq8mE3itIoDkRTHV0jkkC8ZrbiLC/q1Iws4fNOobMynSA9VmFmuRF5dbjax9+iUNi3Tg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=BuNgnnO4; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="BuNgnnO4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1726480238; x=1758016238; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=IMTQEf/JsEhNn9hxmAfyuprjfemrvmpeaN0K8J1Fyo4=; b=BuNgnnO4ZMhjXnrUjWHIojSXKy7aZvRLa0sf/JV0PTq6D6xSg9Dh/xus zTHFz/eQ/4D9z5tfEXOU4PZ/NTenF63xJZUeXmOTvs//X1L5w0tU2iIWs 56Sj5ta13cwUSgX3v3HVoEdKw9Z2Pb68G6ldC+8L6nnCe7fDGHH26mAzh XjmIQexrgQn0eMMIkS4TOj5tQZJwjSMzrJxmiSo/C6LQJTx3chHWbfIfP 3FfwbRR9e0jV9Lx2t/MmaCgazK72rxKoWOK9c5SdMl3dSE3Y7tcoKtKjq id2wZp/CE4DXKYTbr8UjIn/elt/8J16DDb3FF9mFJ5OQTDdXT5L19KByC A==; X-CSE-ConnectionGUID: FMt8JCZwTJSUmtKKgkwdXA== X-CSE-MsgGUID: qpwBePRKSymtVYn7wrpYAg== X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="199259965" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 16 Sep 2024 02:50:35 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 16 Sep 2024 02:50:19 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 16 Sep 2024 02:50:17 -0700 From: Daniel Machon Date: Mon, 16 Sep 2024 11:49:20 +0200 Subject: [PATCH 2/4] clk: lan966x: make clk_names const char * const Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240916-lan969x-clock-v1-2-0e150336074d@microchip.com> References: <20240916-lan969x-clock-v1-0-0e150336074d@microchip.com> In-Reply-To: <20240916-lan969x-clock-v1-0-0e150336074d@microchip.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kavyasree Kotagiri , Steen Hegelund , Horatiu Vultur CC: , , X-Mailer: b4 0.14-dev Change clk_names to const char * const to silence checkpatch in subsequent patches. Signed-off-by: Daniel Machon --- drivers/clk/clk-lan966x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-lan966x.c b/drivers/clk/clk-lan966x.c index 870fd7df50c1..4dbd4eb0e507 100644 --- a/drivers/clk/clk-lan966x.c +++ b/drivers/clk/clk-lan966x.c @@ -24,7 +24,7 @@ #define DIV_MAX 255 -static const char *clk_names[N_CLOCKS] = { +static const char * const clk_names[N_CLOCKS] = { "qspi0", "qspi1", "qspi2", "sdmmc0", "pi", "mcan0", "mcan1", "flexcom0", "flexcom1", "flexcom2", "flexcom3", From patchwork Mon Sep 16 09:49:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13805228 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B45B14A4C1; Mon, 16 Sep 2024 09:50:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726480232; cv=none; b=RDfnkMu7XuJHdQ9/IJt5tiR4BkunpjYrrdRMBAh1QO/0i0NB8aLRti71JgjV2M0SiuktUzNkr+ewQsLskHHTAXfCuTmzR9bgvDpxiOg9cf0+pXEcabeV1ZF9Vbw10h1GHP9sW/Cd8p7FROrAnZYoP1Aq+UOasU+tztFZ3XldbR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726480232; c=relaxed/simple; bh=3snNzhZdAaieMyjpY/9scwKbiNQl/gdpYsT+IY699NI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=kPbVtvQaWijJh8SSRig8gnOkRERLrDI0oJO3+YS9VgyNqhCYFeNHscA0OvC01dv7vC5rTABdTLyzqTJVKPF3xKfLnU553OLdEKxgNCglRIyy3rX+Gwj61tKWKpkvf6XotD7dU8DbPmQ8N9+KueV/+qaFiUxDfCh+6kDNyPfSMJs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=S1Val37B; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="S1Val37B" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1726480231; x=1758016231; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=3snNzhZdAaieMyjpY/9scwKbiNQl/gdpYsT+IY699NI=; b=S1Val37BF9fzuqyq9JCLIEH+MQ1+8y5xJXz9MI79O5XZh0rFaTOULeaS Cm9xFPbH+JLKmKfTHmaH36IJsR77e6s20qa92wWD1JwJGW+dZ63+Dfy4o vugQSj1tY/uElor+fYu9LRJnvCWdT0o8CKJHAXv0nPZ5bn/aIsiBp7xkd vSK55m+PKVdkOQUNhqHo27Ykt7bkbntcxQ7HJ02SKL0OoEuzPLJLMDMTN D3OZoz60VqjxmjqUbiG/zMKe3DWG4KbaKhSG7tkBLWPjYLmJmy7Fh8grk ZWyo6qFiCWOkg4p0kwcEioJpdid99vStj36Tb5op9THM2LMZeKZ/ZIIgI A==; X-CSE-ConnectionGUID: As66prBtTYKW6R/VrMccAw== X-CSE-MsgGUID: 2jWW2n5pRUSoqnM+mjjQPg== X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="262821348" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 16 Sep 2024 02:50:28 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 16 Sep 2024 02:50:21 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 16 Sep 2024 02:50:19 -0700 From: Daniel Machon Date: Mon, 16 Sep 2024 11:49:21 +0200 Subject: [PATCH 3/4] clk: lan966x: prepare driver for lan969x support Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240916-lan969x-clock-v1-3-0e150336074d@microchip.com> References: <20240916-lan969x-clock-v1-0-0e150336074d@microchip.com> In-Reply-To: <20240916-lan969x-clock-v1-0-0e150336074d@microchip.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kavyasree Kotagiri , Steen Hegelund , Horatiu Vultur CC: , , X-Mailer: b4 0.14-dev In preparation for lan969x support, add private match data for lan966x and add variables for: peripheral clock names, clock gate names, number of total clocks and number of generic clocks. Use the variables throughout. Signed-off-by: Daniel Machon --- drivers/clk/clk-lan966x.c | 56 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 40 insertions(+), 16 deletions(-) diff --git a/drivers/clk/clk-lan966x.c b/drivers/clk/clk-lan966x.c index 4dbd4eb0e507..b25330159446 100644 --- a/drivers/clk/clk-lan966x.c +++ b/drivers/clk/clk-lan966x.c @@ -24,7 +24,7 @@ #define DIV_MAX 255 -static const char * const clk_names[N_CLOCKS] = { +static const char * const lan966x_clk_names[] = { "qspi0", "qspi1", "qspi2", "sdmmc0", "pi", "mcan0", "mcan1", "flexcom0", "flexcom1", "flexcom2", "flexcom3", @@ -53,7 +53,7 @@ struct clk_gate_soc_desc { int bit_idx; }; -static const struct clk_gate_soc_desc clk_gate_desc[] = { +static const struct clk_gate_soc_desc lan966x_clk_gate_desc[] = { { "uhphs", 11 }, { "udphs", 10 }, { "mcramc", 9 }, @@ -61,6 +61,22 @@ static const struct clk_gate_soc_desc clk_gate_desc[] = { { } }; +struct lan966x_match_data { + char *name; + const char * const *clk_name; + const struct clk_gate_soc_desc *clk_gate_desc; + u8 num_generic_clks; + u8 num_total_clks; +}; + +static struct lan966x_match_data lan966x_desc = { + .name = "lan966x", + .clk_name = lan966x_clk_names, + .clk_gate_desc = lan966x_clk_gate_desc, + .num_total_clks = 18, + .num_generic_clks = 14, +}; + static DEFINE_SPINLOCK(clk_gate_lock); static void __iomem *base; @@ -186,24 +202,26 @@ static struct clk_hw *lan966x_gck_clk_register(struct device *dev, int i) }; static int lan966x_gate_clk_register(struct device *dev, + const struct lan966x_match_data *data, struct clk_hw_onecell_data *hw_data, void __iomem *gate_base) { - int i; + for (int i = data->num_generic_clks; i < data->num_total_clks; ++i) { + int idx = i - data->num_generic_clks; + const struct clk_gate_soc_desc *desc; - for (i = GCK_GATE_UHPHS; i < N_CLOCKS; ++i) { - int idx = i - GCK_GATE_UHPHS; + desc = &data->clk_gate_desc[idx]; hw_data->hws[i] = - devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name, - "lan966x", 0, gate_base, - clk_gate_desc[idx].bit_idx, + devm_clk_hw_register_gate(dev, desc->name, + data->name, 0, gate_base, + desc->bit_idx, 0, &clk_gate_lock); if (IS_ERR(hw_data->hws[i])) return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]), "failed to register %s clock\n", - clk_gate_desc[idx].name); + desc->name); } return 0; @@ -211,13 +229,19 @@ static int lan966x_gate_clk_register(struct device *dev, static int lan966x_clk_probe(struct platform_device *pdev) { + const struct lan966x_match_data *data; struct clk_hw_onecell_data *hw_data; struct device *dev = &pdev->dev; void __iomem *gate_base; struct resource *res; int i, ret; - hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS), + data = device_get_match_data(dev); + if (!data) + return -EINVAL; + + hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, + data->num_total_clks), GFP_KERNEL); if (!hw_data) return -ENOMEM; @@ -228,10 +252,10 @@ static int lan966x_clk_probe(struct platform_device *pdev) init.ops = &lan966x_gck_ops; - hw_data->num = GCK_GATE_UHPHS; + hw_data->num = data->num_generic_clks; - for (i = 0; i < GCK_GATE_UHPHS; i++) { - init.name = clk_names[i]; + for (i = 0; i < data->num_generic_clks; i++) { + init.name = data->clk_name[i]; hw_data->hws[i] = lan966x_gck_clk_register(dev, i); if (IS_ERR(hw_data->hws[i])) { dev_err(dev, "failed to register %s clock\n", @@ -246,9 +270,9 @@ static int lan966x_clk_probe(struct platform_device *pdev) if (IS_ERR(gate_base)) return PTR_ERR(gate_base); - hw_data->num = N_CLOCKS; + hw_data->num = data->num_total_clks; - ret = lan966x_gate_clk_register(dev, hw_data, gate_base); + ret = lan966x_gate_clk_register(dev, data, hw_data, gate_base); if (ret) return ret; } @@ -257,7 +281,7 @@ static int lan966x_clk_probe(struct platform_device *pdev) } static const struct of_device_id lan966x_clk_dt_ids[] = { - { .compatible = "microchip,lan966x-gck", }, + { .compatible = "microchip,lan966x-gck", .data = &lan966x_desc }, { } }; MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids); From patchwork Mon Sep 16 09:49:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13805229 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEECC14B967; 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X-CSE-ConnectionGUID: As66prBtTYKW6R/VrMccAw== X-CSE-MsgGUID: J4pw1vvcTTqwz1VwMuEp6Q== X-IronPort-AV: E=Sophos;i="6.10,233,1719903600"; d="scan'208";a="262821349" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 16 Sep 2024 02:50:29 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 16 Sep 2024 02:50:23 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 16 Sep 2024 02:50:21 -0700 From: Daniel Machon Date: Mon, 16 Sep 2024 11:49:22 +0200 Subject: [PATCH 4/4] clk: lan966x: add support for lan969x SoC clock driver Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240916-lan969x-clock-v1-4-0e150336074d@microchip.com> References: <20240916-lan969x-clock-v1-0-0e150336074d@microchip.com> In-Reply-To: <20240916-lan969x-clock-v1-0-0e150336074d@microchip.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kavyasree Kotagiri , Steen Hegelund , Horatiu Vultur CC: , , X-Mailer: b4 0.14-dev Add support for the lan969x SoC clock driver in the existing lan966x driver. The lan969x clock controller contains 3 PLLs - cpu_clk, ddr_clk and sys_clk (same as lan966x) which generates and supplies the clock to various peripherals within the SoC. Signed-off-by: Daniel Machon --- drivers/clk/clk-lan966x.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/clk-lan966x.c b/drivers/clk/clk-lan966x.c index b25330159446..9b928e4a1c62 100644 --- a/drivers/clk/clk-lan966x.c +++ b/drivers/clk/clk-lan966x.c @@ -31,6 +31,13 @@ static const char * const lan966x_clk_names[] = { "flexcom4", "timer1", "usb_refclk", }; +static const char * const lan969x_clk_names[] = { + "qspi0", "qspi2", "sdmmc0", "sdmmc1", + "mcan0", "mcan1", "flexcom0", + "flexcom1", "flexcom2", "flexcom3", + "timer1", "usb_refclk", +}; + struct lan966x_gck { struct clk_hw hw; void __iomem *reg; @@ -61,6 +68,13 @@ static const struct clk_gate_soc_desc lan966x_clk_gate_desc[] = { { } }; +static const struct clk_gate_soc_desc lan969x_clk_gate_desc[] = { + { "usb_drd", 10 }, + { "mcramc", 9 }, + { "hmatrix", 8 }, + { } +}; + struct lan966x_match_data { char *name; const char * const *clk_name; @@ -77,6 +91,14 @@ static struct lan966x_match_data lan966x_desc = { .num_generic_clks = 14, }; +static struct lan966x_match_data lan969x_desc = { + .name = "lan969x", + .clk_name = lan969x_clk_names, + .clk_gate_desc = lan969x_clk_gate_desc, + .num_total_clks = 15, + .num_generic_clks = 12, +}; + static DEFINE_SPINLOCK(clk_gate_lock); static void __iomem *base; @@ -282,6 +304,7 @@ static int lan966x_clk_probe(struct platform_device *pdev) static const struct of_device_id lan966x_clk_dt_ids[] = { { .compatible = "microchip,lan966x-gck", .data = &lan966x_desc }, + { .compatible = "microchip,lan9691-gck", .data = &lan969x_desc }, { } }; MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids);