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[27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:51:34 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Jessica Clarke , Richard Henderson Subject: [PATCH v7 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Date: Tue, 17 Sep 2024 01:51:03 +1000 Message-Id: <20240916155119.14610-2-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 bsd-user/riscv/target_arch_cpu.h diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h new file mode 100644 index 0000000000..f8d85e01ad --- /dev/null +++ b/bsd-user/riscv/target_arch_cpu.h @@ -0,0 +1,40 @@ +/* + * RISC-V CPU init and loop + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_CPU_H +#define TARGET_ARCH_CPU_H + +#include "target_arch.h" +#include "signal-common.h" + +#define TARGET_DEFAULT_CPU_MODEL "max" + +static inline void target_cpu_init(CPURISCVState *env, + struct target_pt_regs *regs) +{ + int i; + + for (i = 1; i < 32; i++) { + env->gpr[i] = regs->regs[i]; + } + + env->pc = regs->sepc; +} + +#endif /* TARGET_ARCH_CPU_H */ From patchwork Mon Sep 16 15:51:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B0EFC3ABA2 for ; Mon, 16 Sep 2024 15:52:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE0v-0006hP-DH; Mon, 16 Sep 2024 11:51:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE0s-0006Zk-TB; Mon, 16 Sep 2024 11:51:42 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE0r-0000Tg-9K; Mon, 16 Sep 2024 11:51:42 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-206f9b872b2so41786665ad.3; Mon, 16 Sep 2024 08:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501899; x=1727106699; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DTvqmRJjCBmmQsqoIM7XAGZfiD8autBgUlGw18dRGRE=; b=RamcKIBnEaEngPmAbAvjx7/iAqCH7QvaivcQi7/hoeo00hCh0LCKTI10g33V0BAexG GxNufUfbEGobqR9lQVdyWhXvZZsQzsQqPjFNJ+UVRY8AeiiVFL1dcqY9mz9lNK3na8GK RHTbShMFjnnHcfbPOe+X2b8QE65D+P9o18Xwh/Fbm5HcMHMmxI0KNnToM6jUOb4CeWde 7xpXQMeDZ8wqgz4ioh736HJTThcp0gdyNhbXc/D0tDLdB3TOYRceEIz0oX1DdyeGO9k/ UBosZigybUI4B0i/jtLOlefGeGOhmQAKJ+sLTkGlAAYQot98B45Pya8+ZKkpdR62ra9A r0vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501899; x=1727106699; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DTvqmRJjCBmmQsqoIM7XAGZfiD8autBgUlGw18dRGRE=; b=CCOblTx68PMAK41ez8JsA088iCnYHcChdDNBds3kIWQXIkB9C8MbvwK/4Fh3Op9fPm IjDHcbjq1TUVtZqdE1TGwGMaROJRfW2aGtAbhYMdp3WtNo9uyCSf3x9bcIvgHGhECbft XXQcL3mdn+5a3QHU8USPdLljCPa7l8A5G/1GCv6Up81mJa+MksIFvLKAEDL/hkiaB/hO G/SUmfbjJRe6F9SXP/X+bbM5yCZ8fAFTNzuiJGKjUM2s9bds1mLQh9XQNymJd0tXDlSW UDLzk1Xw90J452pMHFLRMVh/BiEMtgoNfDGe9fX/pSs2cKo0dkw0OPqSwkAGxqOwSGmx wSaA== X-Forwarded-Encrypted: i=1; AJvYcCWAu5EatYhICXqqI98bkkjPzR/xaQlbqdgTqQcOq4hHPCqY+uf92vFxevsb+T7ZNrIdc0aTNRxhUHzf@nongnu.org X-Gm-Message-State: AOJu0YwQxwYbaCpeud89yW4qFRLXYVfPEpAgEy29WsQwFsd1rFOlLKJq krvLOk5Ta2iWc1j/+M8iplJJ9GZqGduq7FLT8N1erUJlLuQbz93NmCQGNHh1 X-Google-Smtp-Source: AGHT+IF9pU7/Z5xK+JkHH4+aN6lAbbuxA8xbDiGb0/8wVvgAUciROjQePtLbm8OXWdap21CL4vZ6oA== X-Received: by 2002:a17:903:41cc:b0:207:6d2:2645 with SMTP id d9443c01a7336-2076e46177cmr234336705ad.47.1726501898795; Mon, 16 Sep 2024 08:51:38 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:51:38 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Jessica Clarke , Kyle Evans , Richard Henderson Subject: [PATCH v7 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Date: Tue, 17 Sep 2024 01:51:04 +1000 Message-Id: <20240916155119.14610-3-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 94 ++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index f8d85e01ad..9c31d9dc4c 100644 --- a/bsd-user/riscv/target_arch_cpu.h +++ b/bsd-user/riscv/target_arch_cpu.h @@ -37,4 +37,98 @@ static inline void target_cpu_init(CPURISCVState *env, env->pc = regs->sepc; } +static inline void target_cpu_loop(CPURISCVState *env) +{ + CPUState *cs = env_cpu(env); + int trapnr; + abi_long ret; + unsigned int syscall_num; + int32_t signo, code; + + for (;;) { + cpu_exec_start(cs); + trapnr = cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + signo = 0; + + switch (trapnr) { + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + case RISCV_EXCP_U_ECALL: + syscall_num = env->gpr[xT0]; + env->pc += TARGET_INSN_SIZE; + /* Compare to cpu_fetch_syscall_args() in riscv/riscv/trap.c */ + if (TARGET_FREEBSD_NR___syscall == syscall_num || + TARGET_FREEBSD_NR_syscall == syscall_num) { + ret = do_freebsd_syscall(env, + env->gpr[xA0], + env->gpr[xA1], + env->gpr[xA2], + env->gpr[xA3], + env->gpr[xA4], + env->gpr[xA5], + env->gpr[xA6], + env->gpr[xA7], + 0); + } else { + ret = do_freebsd_syscall(env, + syscall_num, + env->gpr[xA0], + env->gpr[xA1], + env->gpr[xA2], + env->gpr[xA3], + env->gpr[xA4], + env->gpr[xA5], + env->gpr[xA6], + env->gpr[xA7] + ); + } + + /* + * Compare to cpu_set_syscall_retval() in + * riscv/riscv/vm_machdep.c + */ + if (ret >= 0) { + env->gpr[xA0] = ret; + env->gpr[xT0] = 0; + } else if (ret == -TARGET_ERESTART) { + env->pc -= TARGET_INSN_SIZE; + } else if (ret != -TARGET_EJUSTRETURN) { + env->gpr[xA0] = -ret; + env->gpr[xT0] = 1; + } + break; + case RISCV_EXCP_ILLEGAL_INST: + signo = TARGET_SIGILL; + code = TARGET_ILL_ILLOPC; + break; + case RISCV_EXCP_BREAKPOINT: + signo = TARGET_SIGTRAP; + code = TARGET_TRAP_BRKPT; + break; + case EXCP_DEBUG: + signo = TARGET_SIGTRAP; + code = TARGET_TRAP_BRKPT; + break; + default: + fprintf(stderr, "qemu: unhandled CPU exception " + "0x%x - aborting\n", trapnr); + cpu_dump_state(cs, stderr, 0); + abort(); + } + + if (signo) { + force_sig_fault(signo, code, env->pc); + } + + process_pending_signals(env); + } +} + #endif /* TARGET_ARCH_CPU_H */ From patchwork Mon Sep 16 15:51:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7A41C3ABD1 for ; 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[27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:51:42 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions Date: Tue, 17 Sep 2024 01:51:05 +1000 Message-Id: <20240916155119.14610-4-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_cpu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h index 9c31d9dc4c..a93ea3915a 100644 --- a/bsd-user/riscv/target_arch_cpu.h +++ b/bsd-user/riscv/target_arch_cpu.h @@ -131,4 +131,18 @@ static inline void target_cpu_loop(CPURISCVState *env) } } +static inline void target_cpu_clone_regs(CPURISCVState *env, target_ulong newsp) +{ + if (newsp) { + env->gpr[xSP] = newsp; + } + + env->gpr[xA0] = 0; + env->gpr[xT0] = 0; +} + +static inline void target_cpu_reset(CPUArchState *env) +{ +} + #endif /* TARGET_ARCH_CPU_H */ From patchwork Mon Sep 16 15:51:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BA72C3ABA2 for ; Mon, 16 Sep 2024 15:53:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE12-00073D-0Y; Mon, 16 Sep 2024 11:51:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE10-0006v4-3Y; Mon, 16 Sep 2024 11:51:50 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE0y-0000UL-Cp; Mon, 16 Sep 2024 11:51:49 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2068acc8a4fso31355595ad.1; Mon, 16 Sep 2024 08:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501906; x=1727106706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q8SeRNxqA0kdGYXuMPPKRU3j4MVX/4+712bEYl1oABA=; b=e7fps7NagOTBehf4dmz4emnrSS72LqJ320yvMm3wxDVZpTJ99ZF9ZX0hOcVtNZZ+1S +XXyILR7i4oMr4ju/Hf2xi52sTY79Z/lCO9ATCr2aRJNK94esEd9NLdmWsVUUMoUouLC J1hnpYTMz+bmUhoDIBkfQagOdPa3L08ImdtGcQWnxXFo+rD8iH+pJEN9xi/EI/cEF71L bDgPHGYuHeaeiXJNVNvdom+VFImQSC/ozfL3mEsyjvptSpn0vOdbVy+mGO7SAEsMRbHR JuJ/hrO/8DKCjH9GiXxzlXhKl8268QZt3HU7ZpHoc8ndi35RSVwEXQ/eeXnsq4ckgPM4 d4mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501906; x=1727106706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q8SeRNxqA0kdGYXuMPPKRU3j4MVX/4+712bEYl1oABA=; b=t3IIHUg7fe9tLOeq+5SL+J7gS5CkwGHDOo2vb3C/mtsCNVMwd2e9OvY8igcCjk8Azg 9UDnuLAYQ4TP6JYHbMmZqBy3Eu30Kj2gRWyfwib/jt5UgZNocz/KeZSZaNneNqbfDdIs y0fnAH6Aj4fegmD4UjaW2rU1rpOPyFF1EHS+wQ/9KN9xCar+o/dVO+l2+8TykFspugJ2 fzY8ExqmUbnuyrOVVp2oRGOdS5Dv9cD0mSjrXk12a0PQA0EyysQS8sPypgGzGK4i5Yt6 qno2aAdg6JN1A+SOsBdDB2zkVNUHumRFsf9Ny/b6axmgjvIUBfuJJm87IW4LKp+BvuDq Caww== X-Forwarded-Encrypted: i=1; AJvYcCW0Uok1crTMoM/O8IxCizxsFROuV+Uxj0lttXppQ5Neim1pG3RQhHj7hxR9HSTvBlETgyxFc1j6cb5i@nongnu.org X-Gm-Message-State: AOJu0YwjtdxzmHiMbplmgB9H9Zi/IkZxUAIqAHIIA18sQv8sIZlTLtQR n7RkFNgKZ6t0v5kMyOlBArz2PXRVL8xT7g4XDaDth1zc8iRcjoWqdTbzE5dl X-Google-Smtp-Source: AGHT+IFE9rMRERxsAPLM58glQqDq7TEDtku+nN95/z+RWA38CMx/Sbe8XXQXl/ae8LoXEdkY248COw== X-Received: by 2002:a17:903:1c5:b0:206:9ab3:2ec1 with SMTP id d9443c01a7336-2078295da1fmr141000975ad.22.1726501906204; Mon, 16 Sep 2024 08:51:46 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:51:45 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 04/17] bsd-user: Implement RISC-V TLS register setup Date: Tue, 17 Sep 2024 01:51:06 +1000 Message-Id: <20240916155119.14610-5-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch.h | 27 +++++++++++++++++++++++++++ bsd-user/riscv/target_arch_cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 bsd-user/riscv/target_arch.h create mode 100644 bsd-user/riscv/target_arch_cpu.c diff --git a/bsd-user/riscv/target_arch.h b/bsd-user/riscv/target_arch.h new file mode 100644 index 0000000000..26ce07f343 --- /dev/null +++ b/bsd-user/riscv/target_arch.h @@ -0,0 +1,27 @@ +/* + * RISC-V specific prototypes + * + * Copyright (c) 2019 Mark Corbin + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_H +#define TARGET_ARCH_H + +#include "qemu.h" + +void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls); + +#endif /* TARGET_ARCH_H */ diff --git a/bsd-user/riscv/target_arch_cpu.c b/bsd-user/riscv/target_arch_cpu.c new file mode 100644 index 0000000000..44e25d2ddf --- /dev/null +++ b/bsd-user/riscv/target_arch_cpu.c @@ -0,0 +1,29 @@ +/* + * RISC-V CPU related code + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ +#include "qemu/osdep.h" + +#include "target_arch.h" + +#define TP_OFFSET 16 + +/* Compare with cpu_set_user_tls() in riscv/riscv/vm_machdep.c */ +void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls) +{ + env->gpr[xTP] = newtls + TP_OFFSET; +} From patchwork Mon Sep 16 15:51:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 120CEC3ABB2 for ; Mon, 16 Sep 2024 15:52:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE15-0007Ja-NS; Mon, 16 Sep 2024 11:51:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE14-0007Dh-7x; Mon, 16 Sep 2024 11:51:54 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE12-0000Uf-Hj; Mon, 16 Sep 2024 11:51:53 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-205909afad3so47642075ad.2; Mon, 16 Sep 2024 08:51:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501910; x=1727106710; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g4MfaAoEg0D4PG1s02DK0HI+nWn0NbjMokYUO+miRKs=; b=UMTtIHWtK1dsKpHWDYMxdmQYPZUm9ssP6Q25Fci5QG5DLg1Fovbg99mQWdZQ0uWbrr HgvCyB/hdxQ/ppkNyiFvHPO3GRJptPiAEF588ZwVyTunRH8IQGvkypMQ9Dl1ogjfQIfR 8La/jnz+23QxnMRLHj/Q0+uEi48abOzBNYnfnYFiPPWzECKQSmpPPtNXxmXneCzPPd6C m+Tgpjk5B+84SNixsQbKiKjiTxgNhpwx0cky3uJ+cYPPI+ZNIAu+BlINL70djuoF64a5 OwPQWHOSOkJYJaRulNrEvlTVjTDeMmgR29fba2QfqCEMjxLXL3YemRFB/2ssOt8UMQZf nzng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501910; x=1727106710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g4MfaAoEg0D4PG1s02DK0HI+nWn0NbjMokYUO+miRKs=; b=l9aCIWGvsiCDLe/QxM06t1sPBqlUA4RoXIqsyO/ZNnZiCwNyMCoD7BYKLRQr0HdDjy I2uKXcao1tByjE5511+c0JADTIEhDqZVQe4tehyF/iUAE9gvu5GPLyhR7iDoLzAyV/oQ dkFCB9H7QcqApNU3/0adGvkw25vtCU3GRUZKT4hodgme0DHAiNP75rdtZ78tMi3lnHRH VaFqLPbtdPZSOATzXG9D/W/7EKvqk1+ruFBMKPDgj71hciwwJUAlt8OSErz00zwqKMEy bjZEPJYqk3aB1FyeDgby93/XMxZP4NB7So/azPL1vY11joHK0i+8wo2G8aEqzI4RoWlr VPFQ== X-Forwarded-Encrypted: i=1; AJvYcCUWkUHi+hqkyAgMR4C/w7lL+OjJlAeNhaHJUzawLueeE8IwIIC1LNvhZjUutHb3dmqrcZZ8M1SI3isl@nongnu.org X-Gm-Message-State: AOJu0Yw6pLZUplo9Ij5lxUVLC2ub5cqvSMOgHZlacQC6iMTUwf5IkF9I XHR7SgY0GmBKu5v5n1n82AsNF4qe+acVTv3Gn1gU+MzcH9sdZ4zfEX4NcjqT X-Google-Smtp-Source: AGHT+IEVXHvOwF2bRlk50iIDHG4QDwiJtFvyuoa2VzV94BHzd2G6KvXm1mKbo17dcDMocBVIVFE1pw== X-Received: by 2002:a17:902:c40e:b0:206:add9:624 with SMTP id d9443c01a7336-2076e39fc33mr272727285ad.36.1726501910270; Mon, 16 Sep 2024 08:51:50 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:51:49 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Kyle Evans , Richard Henderson Subject: [PATCH v7 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Date: Tue, 17 Sep 2024 01:51:07 +1000 Message-Id: <20240916155119.14610-6-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_elf.h | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bsd-user/riscv/target_arch_elf.h diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_elf.h new file mode 100644 index 0000000000..4eb915e61e --- /dev/null +++ b/bsd-user/riscv/target_arch_elf.h @@ -0,0 +1,42 @@ +/* + * RISC-V ELF definitions + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_ELF_H +#define TARGET_ARCH_ELF_H + +#define elf_check_arch(x) ((x) == EM_RISCV) +#define ELF_START_MMAP 0x80000000 +#define ELF_ET_DYN_LOAD_ADDR 0x100000 +#define ELF_CLASS ELFCLASS64 + +#define ELF_DATA ELFDATA2LSB +#define ELF_ARCH EM_RISCV + +#define ELF_HWCAP get_elf_hwcap() +static uint32_t get_elf_hwcap(void) +{ + RISCVCPU *cpu = RISCV_CPU(thread_cpu); + + return cpu->env.misa_ext_mask; +} + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +#endif /* TARGET_ARCH_ELF_H */ From patchwork Mon Sep 16 15:51:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BAD78C3ABCE for ; Mon, 16 Sep 2024 15:52:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE19-0007Yk-Cc; Mon, 16 Sep 2024 11:51:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE17-0007Sh-TO; Mon, 16 Sep 2024 11:51:58 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE16-0000V6-5J; Mon, 16 Sep 2024 11:51:57 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-206b9455460so35165325ad.0; Mon, 16 Sep 2024 08:51:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501914; x=1727106714; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a+NCEiOZJzboz9w1INUibK6hoUbq+IVFPstbDaWXows=; b=RzV5qcbVa2nj0Lm5jeqORRCcNSD2iolLYMxy5AydgBeRZqEiRc5vqzpYQiKdDItUL4 Rmr9FQog3IDM/nWhpAgxjklPZlOzIcDFG+KdEMTSJffMBDO7z7U3XyFrQdNa88MwyxlG A1YicGiNdgSzqA/m31Ap3kIPbnfTiZULjSv90kBlEWuv7F8qnx6w/0MZwMgm0gnzi0Yb /a0/NZFQeVj1XPteYTpSmkhCZpgbn/hCzbsIkZBcTbN1dSH07kg3bhMzUaJKx+DBrCZ1 FKHHQF3Q0x/Y5RRLFngBJ2aORAmzwf7Uho/lKqTSUjUAsOdKaVuDC64aURWqyz5Y5QUz Qylw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501914; x=1727106714; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a+NCEiOZJzboz9w1INUibK6hoUbq+IVFPstbDaWXows=; b=eVXZW4/s5re+duDQS73bIxea3Ns3tVoOzKW8D20N9rnHtO/iKnLoW0ltAfjRRVwLKy Qhv6TJVeTaexM6uldQXfmeRxkaDh9G+PjA7baCoql02Q/tkKFfgp/No8QameUQp9Ui33 aNvHpHRJBp+T8WJZxS8gg6FS7DapuKwDLw7lSkkguVwsBX4Zs0KTrL9vpajNO5bgPGwh VJ1Wr1SdYctGVGkOmeGzHhqClaTL4igeB2DKZ3ZrrgtBnQKXesVBjpH1rwXNXUhwpgEB Xdst4MP1+cAbl2rKb7dIkPZ407hX7Kb61BRvkEjy8nN2C0TACrphq5IcpFFnIHadpsvE Ki6A== X-Forwarded-Encrypted: i=1; AJvYcCW5bc63mgrDplwxH20IKpf0E5+UAbiM4Trbu2cKd6nxJawhQScEolvCuoc523QzE7qRWIWEf20zf67q@nongnu.org X-Gm-Message-State: AOJu0YwcvDmCHM12G2Iw4BTS6RvOU06JqIjdHRnAz1LoI44fksjhYC9h 3+pkZmS530quZeQgEKY3lzaijORALJdESeNpgBAexdcb1hKVfDao9BvwOw9U X-Google-Smtp-Source: AGHT+IGQT11ilGOBhstWx/nD8trFw8U4pzR5EQtFrIUQBuRY1SZ7BrwGAy98g0ylOQMotX6Zf8uY0g== X-Received: by 2002:a17:902:dac4:b0:205:8b84:d5e8 with SMTP id d9443c01a7336-2076e5a3ed1mr222790015ad.18.1726501913973; Mon, 16 Sep 2024 08:51:53 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.51.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:51:53 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 06/17] bsd-user: Define RISC-V register structures and register copying Date: Tue, 17 Sep 2024 01:51:08 +1000 Message-Id: <20240916155119.14610-7-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added definitions for RISC-V register structures, including general-purpose registers and floating-point registers, in 'target_arch_reg.h'. Implemented the 'target_copy_regs' function to copy register values from the CPU state to the target register structure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_reg.h | 88 ++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 bsd-user/riscv/target_arch_reg.h diff --git a/bsd-user/riscv/target_arch_reg.h b/bsd-user/riscv/target_arch_reg.h new file mode 100644 index 0000000000..12b1c96b61 --- /dev/null +++ b/bsd-user/riscv/target_arch_reg.h @@ -0,0 +1,88 @@ +/* + * RISC-V register structures + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_REG_H +#define TARGET_ARCH_REG_H + +/* Compare with riscv/include/reg.h */ +typedef struct target_reg { + uint64_t ra; /* return address */ + uint64_t sp; /* stack pointer */ + uint64_t gp; /* global pointer */ + uint64_t tp; /* thread pointer */ + uint64_t t[7]; /* temporaries */ + uint64_t s[12]; /* saved registers */ + uint64_t a[8]; /* function arguments */ + uint64_t sepc; /* exception program counter */ + uint64_t sstatus; /* status register */ +} target_reg_t; + +typedef struct target_fpreg { + uint64_t fp_x[32][2]; /* Floating point registers */ + uint64_t fp_fcsr; /* Floating point control reg */ +} target_fpreg_t; + +#define tswapreg(ptr) tswapal(ptr) + +/* Compare with struct trapframe in riscv/include/frame.h */ +static inline void target_copy_regs(target_reg_t *regs, + const CPURISCVState *env) +{ + + regs->ra = tswapreg(env->gpr[1]); + regs->sp = tswapreg(env->gpr[2]); + regs->gp = tswapreg(env->gpr[3]); + regs->tp = tswapreg(env->gpr[4]); + + regs->t[0] = tswapreg(env->gpr[5]); + regs->t[1] = tswapreg(env->gpr[6]); + regs->t[2] = tswapreg(env->gpr[7]); + regs->t[3] = tswapreg(env->gpr[28]); + regs->t[4] = tswapreg(env->gpr[29]); + regs->t[5] = tswapreg(env->gpr[30]); + regs->t[6] = tswapreg(env->gpr[31]); + + regs->s[0] = tswapreg(env->gpr[8]); + regs->s[1] = tswapreg(env->gpr[9]); + regs->s[2] = tswapreg(env->gpr[18]); + regs->s[3] = tswapreg(env->gpr[19]); + regs->s[4] = tswapreg(env->gpr[20]); + regs->s[5] = tswapreg(env->gpr[21]); + regs->s[6] = tswapreg(env->gpr[22]); + regs->s[7] = tswapreg(env->gpr[23]); + regs->s[8] = tswapreg(env->gpr[24]); + regs->s[9] = tswapreg(env->gpr[25]); + regs->s[10] = tswapreg(env->gpr[26]); + regs->s[11] = tswapreg(env->gpr[27]); + + regs->a[0] = tswapreg(env->gpr[10]); + regs->a[1] = tswapreg(env->gpr[11]); + regs->a[2] = tswapreg(env->gpr[12]); + regs->a[3] = tswapreg(env->gpr[13]); + regs->a[4] = tswapreg(env->gpr[14]); + regs->a[5] = tswapreg(env->gpr[15]); + regs->a[6] = tswapreg(env->gpr[16]); + regs->a[7] = tswapreg(env->gpr[17]); + + regs->sepc = tswapreg(env->pc); +} + +#undef tswapreg + +#endif /* TARGET_ARCH_REG_H */ From patchwork Mon Sep 16 15:51:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97F52C3ABB2 for ; Mon, 16 Sep 2024 15:53:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE1E-0007ki-65; Mon, 16 Sep 2024 11:52:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE1C-0007ie-7z; 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[27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:51:57 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 07/17] bsd-user: Add RISC-V signal trampoline setup function Date: Tue, 17 Sep 2024 01:51:09 +1000 Message-Id: <20240916155119.14610-8-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sigtramp.h | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 bsd-user/riscv/target_arch_sigtramp.h diff --git a/bsd-user/riscv/target_arch_sigtramp.h b/bsd-user/riscv/target_arch_sigtramp.h new file mode 100644 index 0000000000..dfe5076739 --- /dev/null +++ b/bsd-user/riscv/target_arch_sigtramp.h @@ -0,0 +1,41 @@ +/* + * RISC-V sigcode + * + * Copyright (c) 2019 Mark Corbin + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARCH_SIGTRAMP_H +#define TARGET_ARCH_SIGTRAMP_H + +/* Compare with sigcode() in riscv/riscv/locore.S */ +static inline abi_long setup_sigtramp(abi_ulong offset, unsigned sigf_uc, + unsigned sys_sigreturn) +{ + uint32_t sys_exit = TARGET_FREEBSD_NR_exit; + + uint32_t sigtramp_code[] = { + /*1*/ const_le32(0x00010513), /*mv a0, sp*/ + /*2*/ const_le32(0x00050513 + (sigf_uc << 20)), /*addi a0,a0,sigf_uc*/ + /*3*/ const_le32(0x00000293 + (sys_sigreturn << 20)),/*li t0,sys_sigreturn*/ + /*4*/ const_le32(0x00000073), /*ecall*/ + /*5*/ const_le32(0x00000293 + (sys_exit << 20)), /*li t0,sys_exit*/ + /*6*/ const_le32(0x00000073), /*ecall*/ + /*7*/ const_le32(0xFF1FF06F) /*b -16*/ + }; + + return memcpy_to_target(offset, sigtramp_code, TARGET_SZSIGCODE); +} +#endif /* TARGET_ARCH_SIGTRAMP_H */ From patchwork Mon Sep 16 15:51:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2458DC3ABB2 for ; Mon, 16 Sep 2024 15:53:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE1H-0007v0-Ao; Mon, 16 Sep 2024 11:52:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE1F-0007qK-LE; Mon, 16 Sep 2024 11:52:05 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE1D-0000Vm-WE; Mon, 16 Sep 2024 11:52:05 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-20696938f86so37566775ad.3; Mon, 16 Sep 2024 08:52:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501922; x=1727106722; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lfzjBG7+9yzLMDJFHDoCCaXekwfn4Gr8dayPzH/NfvM=; b=l3fMrb1Zi5RwagbUbFuB4W5tHFO22ej0GafXuNJTQCN6cu/+wW4Mtr5/6KjPoYhjEL kXq/x13FzAwpid1KmTfLIih7QkOyW9cwdJexD32D2OxuaM9G2G9BJ7yWv60WqhRI1LMs 0oVtW15oXaQcV4Urw/xx9124XwQ1J4c3cHAmxeBt6VCZMNLvJ5gfla+ww751Ox5Xhv7k L8ielXxYUutqNkXj5Ol3KRu0QJABPDJANY1s0+q4OAc1m75rQi0+0j50QBLjRYUDe8C2 VBL9bxTUmCSQqYOoBFIYmnrhxbFofTXmpEECwh8JwDQuZ+auCMkEdme+FiNLd9m13NSM f2Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501922; x=1727106722; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lfzjBG7+9yzLMDJFHDoCCaXekwfn4Gr8dayPzH/NfvM=; b=QnqRDmjqDjsP7DcFxU849L49qu6m4QG384xqUmRkhcnZyvsViVyUEMCtZMi4uNz4Zn JIAOlteU9dUHDZ+oquEHwtyy37SY56ozyIwSRvK8aGV4AD/j0aT+jx9Zrfw1URV3uC+z xfsgTPvT1vhnFkEq08YNmCpShqF1iQUIW1J5dkUtKgIVYPTYzpzTSgSiWlBAFr2qtUsp v1kWQgzm4tjzD5qhK9qwAD/TX5MkT+s4geFkQPngIBf1itjfUuQVtILIAJxVGkOg7tcK t9kB2OFvfL9FJvPThbhY/d49roEQo7AFyIxVUmuBxapFaoph45iDpSi8nyEh0z4gJusi Ak+Q== X-Forwarded-Encrypted: i=1; AJvYcCWfiEH0lxIG2hQN+Z1QjLQx9Rm8HvIWuqiTFPZzaRUcfCMahD2btlXKGAFCBhifyCQoDLjBbKIKfWBN@nongnu.org X-Gm-Message-State: AOJu0YxnduK5ChshQnlPfh+wMkvfqVn+DjV4f8wEJ0rZxDnSMbRgkAGO OP4V262PXWotvVHU8oT7g3K1WEX1bap8dxMfmZzgNM6t+qJrbx0pPNAG6Y7G X-Google-Smtp-Source: AGHT+IGdwUy/oWgWIz5LErbp80hpPvkHbV9jsRdwJZzdto2/X0bPXJK3VchsiBanrX5Di6X6LkPvXg== X-Received: by 2002:a17:902:e842:b0:205:5f35:80a0 with SMTP id d9443c01a7336-2076e460c8bmr263278285ad.57.1726501921500; Mon, 16 Sep 2024 08:52:01 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:01 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 08/17] bsd-user: Implement RISC-V sysarch system call emulation Date: Tue, 17 Sep 2024 01:51:10 +1000 Message-Id: <20240916155119.14610-9-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_sysarch.h | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 bsd-user/riscv/target_arch_sysarch.h diff --git a/bsd-user/riscv/target_arch_sysarch.h b/bsd-user/riscv/target_arch_sysarch.h new file mode 100644 index 0000000000..9af42331b4 --- /dev/null +++ b/bsd-user/riscv/target_arch_sysarch.h @@ -0,0 +1,41 @@ +/* + * RISC-V sysarch() system call emulation + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_SYSARCH_H +#define TARGET_ARCH_SYSARCH_H + +#include "target_syscall.h" +#include "target_arch.h" + +static inline abi_long do_freebsd_arch_sysarch(CPURISCVState *env, int op, + abi_ulong parms) +{ + + return -TARGET_EOPNOTSUPP; +} + +static inline void do_freebsd_arch_print_sysarch( + const struct syscallname *name, abi_long arg1, abi_long arg2, + abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6) +{ + + gemu_log("UNKNOWN OP: %d, " TARGET_ABI_FMT_lx ")", (int)arg1, arg2); +} + +#endif /* TARGET_ARCH_SYSARCH_H */ From patchwork Mon Sep 16 15:51:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805598 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33BB9C3ABB2 for ; Mon, 16 Sep 2024 15:52:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE1S-00088k-0l; Mon, 16 Sep 2024 11:52:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE1L-00085o-Ad; Mon, 16 Sep 2024 11:52:11 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE1I-0000W2-AT; Mon, 16 Sep 2024 11:52:10 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-207115e3056so41536585ad.2; Mon, 16 Sep 2024 08:52:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501926; x=1727106726; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UhgZSr77cs856626csVUMKafDNElH2DCETLtbp74JlY=; b=EVBs03mRzhJ6j6soJGWVZZ9Xjb8kk6vRxvBAN/UcSrNbHvtdHUaDeFcuVN6IckCOSg IMS5rntgEUu+g5rsVGOdVK9gsQzuD2m0dfsyHiSm8JU8dLw3BnxG7S89oMlNWbZZVKtP Cz6cJ7KsiWbEb3U2ya9GsFi6UKJ7W+SiztPJyDyTjN7QmkI2+fQvEKnrKdekkdhoQmko x0k6duufueJ2gkodC2dOSPlaZ/V3IWAaBKYM7Ry5h+2t9I8ebu0FsueUQKRRsiiYe4KW dyrAERDMLxnC8EP3RnIhbb2worzdET2+nAL5kYQZQvSvkXUPMmhFdzKDZBS1g+K2lsZ8 Vg0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501926; x=1727106726; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UhgZSr77cs856626csVUMKafDNElH2DCETLtbp74JlY=; b=qjzBFekKI2H7xOHsx6nRDDtT1MBXxlynOtxcDze9yByef7RqTO71KzHvobs6Nl9zdi 2yHftJxPw2uaofBKWH4DrRQhFSTS8MnKiXXlGYgmdpzFKVFydPgNM4P3+rnJWqBEIiC9 pe4dqILnQ8Az0yt24T/c6fRtRpHDBFWBq4bP8UQS6Jk/6c4yshHPGGHyg0K/HO0ANeJn rbJDguptcYTTwy8ceFxDecGEDoX8oiRi9ai+Fpz0mPfhzVUWHBkkqOY23CKMeYnpVb8D fHowqRkwlsoc3EOvs3wc6krMD/O7P5x5p9P8LcFQvQhDzfLIgCNMVYJf+DbZ4z0OV6G5 3CiQ== X-Forwarded-Encrypted: i=1; AJvYcCUEByYxqX1NyfCIL/a4Q+D5tMrAgyNdHVE0k/Bhu25FnUFSSBiGkCMbQVA3irtjWspnkuYBdBzwiCFF@nongnu.org X-Gm-Message-State: AOJu0YxLWwdfNypdlV8lDVolwaiq1fIS3DWi6FtCSuNl4h43MF9IFOql MMx2msSTt4yEwojSQoPBMlh9p/5QTDyrQHU4x/4Shk+LK7DSbmpn8Baa1gXW X-Google-Smtp-Source: AGHT+IHsP1tJLDPo5pa8Vm+5zmPCTcfhgWn001I1rw6IUBRZ51e+rdV5bYM+vnTET+qL12xFete3Gw== X-Received: by 2002:a17:902:d491:b0:205:56e8:4a4c with SMTP id d9443c01a7336-2076e3d584bmr224174715ad.26.1726501925889; Mon, 16 Sep 2024 08:52:05 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:05 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Jessica Clarke , Kyle Evans , Richard Henderson Subject: [PATCH v7 09/17] bsd-user: Add RISC-V thread setup and initialization support Date: Tue, 17 Sep 2024 01:51:11 +1000 Message-Id: <20240916155119.14610-10-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Implemented functions for setting up and initializing threads in the RISC-V architecture. The 'target_thread_set_upcall' function sets up the stack pointer, program counter, and function argument for new threads. The 'target_thread_init' function initializes thread registers based on the provided image information. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 bsd-user/riscv/target_arch_thread.h diff --git a/bsd-user/riscv/target_arch_thread.h b/bsd-user/riscv/target_arch_thread.h new file mode 100644 index 0000000000..95cd0b6ad7 --- /dev/null +++ b/bsd-user/riscv/target_arch_thread.h @@ -0,0 +1,47 @@ +/* + * RISC-V thread support + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_THREAD_H +#define TARGET_ARCH_THREAD_H + +/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */ +static inline void target_thread_set_upcall(CPURISCVState *regs, + abi_ulong entry, abi_ulong arg, abi_ulong stack_base, + abi_ulong stack_size) +{ + abi_ulong sp; + + sp = ROUND_DOWN(stack_base + stack_size, 16); + + regs->gpr[xSP] = sp; + regs->pc = entry; + regs->gpr[xA0] = arg; +} + +/* Compare with exec_setregs() in riscv/riscv/machdep.c */ +static inline void target_thread_init(struct target_pt_regs *regs, + struct image_info *infop) +{ + regs->sepc = infop->entry; + regs->regs[xRA] = infop->entry; + regs->regs[xA0] = infop->start_stack; + regs->regs[xSP] = ROUND_DOWN(infop->start_stack, 16); +} + +#endif /* TARGET_ARCH_THREAD_H */ From patchwork Mon Sep 16 15:51:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4761DC3ABCE for ; Mon, 16 Sep 2024 15:52:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE1l-0000Lv-My; Mon, 16 Sep 2024 11:52:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE1O-00087G-Or; Mon, 16 Sep 2024 11:52:16 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE1M-0000WB-2i; Mon, 16 Sep 2024 11:52:13 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1fee6435a34so39972135ad.0; Mon, 16 Sep 2024 08:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501930; x=1727106730; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BISuETtEj/uI6CddQsRG+h5xaQo8IxKpbRWv0bTNq7U=; b=f1NRe5DEhoFtBmMfPM7sl9jhA/0wPmqRWkvFdiexOzcCksJbSwz6ToIydTrbiHy/1e KlCkZ37pp0FbgoFD516qtbSodYG4s+DF8P/rt4tuzna6Dsf9Bfm6e2nz3U3G/c5bLBLW 73U0DSspM6eQUSwC0cSIn8+jOKOmAEFyPgzV8eWnU9pVEmnwTVWd4kay2wjkG8zx+gzH Krz95CuK2Vk+2D4LXjNE8TPgwMh0wdEcbjKFHAmZ+FOKNnhIQ1evOB3VU+DG4zNVNljT X/j1aJTUfK/IG+3yU1MD5bTP4PGeMsU4cErN7pSACxOShcoH9PgtTWJDaGFggK/xees0 t7Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501930; x=1727106730; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BISuETtEj/uI6CddQsRG+h5xaQo8IxKpbRWv0bTNq7U=; b=gedDD8dEcCrldEK9r0GvRqsQznxu75DsTgMhMZ40FY5xiqbYYJ7mALN6ogtDL1aU5L sgwbJaZ+HzHdz081gJaBtWR8d8aOuQYzrxUMEwqjmU64j0n5285ea/6mcPx63VG80cVL cIkGgOMDzp7yCGHCPgRvlmF9u4UHezBYvlxvMsiXixFB8KBAyx4X3lz0etkj4wsSMwPG tp6q6WXGGXc6JRziXosUil/xSO2kWvJIzH8ya8oMPSvEg7kqsU1CNZdXDwJuY3wf1R0C vuwZjwaYB9gmb4gNLKG/2KWjd9st5SFecd9ikEJ5coYKMOGx8hIONnN9cspTmyLOBhkL 4BYQ== X-Forwarded-Encrypted: i=1; AJvYcCXhNvUjYi46VaOd8yGXjXBBFQtam7LmzuKTj71HuIwrOk52Q4trCEbj5J4HWE/wIC+C8Jqwt7Uh5eUo@nongnu.org X-Gm-Message-State: AOJu0YwqOhzhQ8ObsNhvOY78LYKH7+yxTxbN/W+plXzQVMWCKj/BlO+x zyEEqiihQQjMaOshRM6BIGqaxLxDnlzd4BnkYGHZKiGFqdk9YUTFi92gbszS X-Google-Smtp-Source: AGHT+IGI/6gvL6AvMc8xaonBXHcuEBGVE3NrKy0i1joHywFWLITRWyVhcPnMmbj/OT8a2Ux7q+exwQ== X-Received: by 2002:a17:902:e809:b0:203:a13a:c49e with SMTP id d9443c01a7336-2076e315920mr251737445ad.1.1726501929764; Mon, 16 Sep 2024 08:52:09 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.52.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:09 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 10/17] bsd-user: Define RISC-V VM parameters and helper functions Date: Tue, 17 Sep 2024 01:51:12 +1000 Message-Id: <20240916155119.14610-11-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added definitions for RISC-V VM parameters, including maximum and default sizes for text, data, and stack, as well as address space limits. Implemented helper functions for retrieving and setting specific values in the CPU state, such as stack pointer and return values. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 bsd-user/riscv/target_arch_vmparam.h diff --git a/bsd-user/riscv/target_arch_vmparam.h b/bsd-user/riscv/target_arch_vmparam.h new file mode 100644 index 0000000000..0f2486def1 --- /dev/null +++ b/bsd-user/riscv/target_arch_vmparam.h @@ -0,0 +1,53 @@ +/* + * RISC-V VM parameters definitions + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_VMPARAM_H +#define TARGET_ARCH_VMPARAM_H + +#include "cpu.h" + +/* Compare with riscv/include/vmparam.h */ +#define TARGET_MAXTSIZ (1 * GiB) /* max text size */ +#define TARGET_DFLDSIZ (128 * MiB) /* initial data size limit */ +#define TARGET_MAXDSIZ (1 * GiB) /* max data size */ +#define TARGET_DFLSSIZ (128 * MiB) /* initial stack size limit */ +#define TARGET_MAXSSIZ (1 * GiB) /* max stack size */ +#define TARGET_SGROWSIZ (128 * KiB) /* amount to grow stack */ + +#define TARGET_VM_MINUSER_ADDRESS (0x0000000000000000UL) +#define TARGET_VM_MAXUSER_ADDRESS (0x0000004000000000UL) + +#define TARGET_USRSTACK (TARGET_VM_MAXUSER_ADDRESS - TARGET_PAGE_SIZE) + +static inline abi_ulong get_sp_from_cpustate(CPURISCVState *state) +{ + return state->gpr[xSP]; +} + +static inline void set_second_rval(CPURISCVState *state, abi_ulong retval2) +{ + state->gpr[xA1] = retval2; +} + +static inline abi_ulong get_second_rval(CPURISCVState *state) +{ + return state->gpr[xA1]; +} + +#endif /* TARGET_ARCH_VMPARAM_H */ From patchwork Mon Sep 16 15:51:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C0C0C3ABB2 for ; Mon, 16 Sep 2024 15:53:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE1p-0000zI-AC; Mon, 16 Sep 2024 11:52:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE1T-0008Bq-Fb; Mon, 16 Sep 2024 11:52:19 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE1Q-0000WU-2q; Mon, 16 Sep 2024 11:52:17 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2057835395aso53623285ad.3; Mon, 16 Sep 2024 08:52:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501934; x=1727106734; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/upld7cTqaC/atkB+nu7yGsbOxCVGK3zsoQHBJP0niw=; b=IFW5nnJoqhH6pkgPhEKHwUF6VsrVpYDudI6kh0IHElvu0L0xZD1jK/4csvvSyjIPey RDB5YmRkkLah55zmt4hxNmI1tdeslj32NgDyx4zgkY8zmfuv7cpgE6Wp06QW4AwVg2F+ P3Wer+j5eJvdX6emig8zR2FBhUsUKDcyimnmDC3B9NVyAloMDC6/Vr0LBDnWqa2ZAnKP GqI4dET8bzHACF0SI4/zhqnPa1ahjcl0WbiH8AygLgzC/cl0mNPSiKc50ol5eWNMw/II boXW3ds1WcrA8ME95dzym3Y/HwhumH87v6DBxWvDqZBUq7UmsltifYsOh+tc0ZvSUuk2 yqIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501934; x=1727106734; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/upld7cTqaC/atkB+nu7yGsbOxCVGK3zsoQHBJP0niw=; b=O0S8gFr3Tme5RFKlBb7RXZzt+7sPJ7FPqhLIhGRj8mAwEgBHC7ShQQRIIVAYxbGmBz psPXgRiuJj4lZqzvSs2u2l1Je7BTKKrjdHzky2pugboyBZfKjK5+3fvlgurBMipe+8ZH GbvGtLcL7P0wQBmyPx6I5Acc+aaIFOyQt+VlKm8pLnRSSHpE1M4PzHr8v8AbeJKSRC/l pfXCEhavjtnejhtQhhad0O2RCJXoCifgeENN8ORWue2MwQMDmbwOcJZvLffAN64E8kO7 EPdxW6i09kpWejqjPIVNWwEtdcE371jVqxU0khDgz7FXmW7jXDj6Q1bm5G00QGYoVGMd ckUw== X-Forwarded-Encrypted: i=1; AJvYcCUlAXbhQMIrZrQOJs6uwy3FuJCeefmzS7Gj//QB/MCXNJ8reu+4clHGUdKC75eqksr/rUTGp1RH7EU4@nongnu.org X-Gm-Message-State: AOJu0YznWF8b2/UtP46mIRaJtt7Ud1WixwCT56VpIiiGR1ehiLQe6b4T bAAsVWgzVysHt6nEWFFE5QscSbtT8HAO1EIw2izVn6HyhQU+xb+qtdqzfWGL X-Google-Smtp-Source: AGHT+IH9NX4eKuyjBx+CXBOPqskHw6LepNBWwIZYET67alIbSRM8IgOyTfuxnWN85+xC5W4DLHE9hA== X-Received: by 2002:a17:903:32c8:b0:207:15f4:2637 with SMTP id d9443c01a7336-2076e30666dmr28698055ad.12.1726501933797; Mon, 16 Sep 2024 08:52:13 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.52.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:13 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Jessica Clarke , Richard Henderson Subject: [PATCH v7 11/17] bsd-user: Define RISC-V system call structures and constants Date: Tue, 17 Sep 2024 01:51:13 +1000 Message-Id: <20240916155119.14610-12-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke Reviewed-by: Richard Henderson --- bsd-user/riscv/target_syscall.h | 38 +++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 bsd-user/riscv/target_syscall.h diff --git a/bsd-user/riscv/target_syscall.h b/bsd-user/riscv/target_syscall.h new file mode 100644 index 0000000000..e7e5231309 --- /dev/null +++ b/bsd-user/riscv/target_syscall.h @@ -0,0 +1,38 @@ +/* + * RISC-V system call definitions + * + * Copyright (c) Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef BSD_USER_RISCV_TARGET_SYSCALL_H +#define BSD_USER_RISCV_TARGET_SYSCALL_H + +/* + * struct target_pt_regs defines the way the registers are stored on the stack + * during a system call. + */ + +struct target_pt_regs { + abi_ulong regs[32]; + abi_ulong sepc; +}; + +#define UNAME_MACHINE "riscv64" + +#define TARGET_HW_MACHINE "riscv" +#define TARGET_HW_MACHINE_ARCH UNAME_MACHINE + +#endif /* BSD_USER_RISCV_TARGET_SYSCALL_H */ From patchwork Mon Sep 16 15:51:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBC69C3ABB2 for ; Mon, 16 Sep 2024 15:54:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE1n-0000hA-4U; Mon, 16 Sep 2024 11:52:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE1W-0008Gw-I3; Mon, 16 Sep 2024 11:52:25 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE1U-0000Wj-L0; Mon, 16 Sep 2024 11:52:21 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2053616fa36so55437505ad.0; Mon, 16 Sep 2024 08:52:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501937; x=1727106737; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cjm2NL6Wgqty15f3ap7G8BavBfHkA8e5dbFy1QdhwG4=; b=DRdcJhw7RaFlYI7hygQRin4no+ltcalPWZwPoA0sWOwdCBr7dM9xE1JEl0lMG0l50P SPKc3DoDMgPG3v9TMhlit8rJ9cwwag8sDH6qyHKvtYsn/iZtw2ZIIj+6KbJ0cj8LBMhN bDKUz0qV8W4PMed1V4ceIbsl8v1y7q4LPKvSOG1cFJJ9nZwW3LrEhTl7+CI5LRIejZrV lmwqGRihMVPnrPbpqy7yRCkthgmIitSpbYOkiJY70RRMVAEe9UX2KcE+FXSX0oFt/XwE ZJn3JquKHn3dXXaPta/8nV87USTDLOT9Nq3uL/KEfCi621KlLs2PZlPOSrlAEygxnvGl ASOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501937; x=1727106737; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cjm2NL6Wgqty15f3ap7G8BavBfHkA8e5dbFy1QdhwG4=; b=k/u5S6+rfrwiMJlPO6wimujtE0Qoczs6C2/Zp3SoOFq/JuPOXkTkmeDw2JA5M/k1VC LgVASbwq8Gvd75isKK1Cc8RdPj1cr5LIfQSkLs8oA2oEYpAjx57sGKVDf8p7H1QpsGyj 8JtxvqHpn0R6OTxYhFFXZvCXRY3JMjoxCURPZSTR1c+ApOP/tp+jCX27Mq/0Vi0MV+el p263J492BNVkfyiu5YRw62sVL+hxxcblwoa5Xk5+bfIWQWMx8OIztoaih5CIBm3mCI0y GO56FhymVEugpL3muzbg7GY/A9Qj2qposQC/6y9JYTDgtucbjHx3QgKeaRSzv7lT6NYg C/XQ== X-Forwarded-Encrypted: i=1; AJvYcCWiFgP4TdejlWbBHWXXuwTMyRzAsA0xFuWTwIbombK0KQ3G2BABWpLWnBnaxTofVF3UzEWosztJYHPH@nongnu.org X-Gm-Message-State: AOJu0YxKv3YTERPGUnGpVnMntumbHa1nquVLCoCm4t2q9QFCg1mGkJx3 fuVarZZNn8XZWkZbmTTg+5G3wX/uzsx6UHBBKStUtZNEZMxEJ4WYSA6IGPBw X-Google-Smtp-Source: AGHT+IHvp6xWy5Uj8koC3hOZr5IcF3pdbi7HmnxV4rlFL/mIqQiq3pzEa1wJCUp5LrklBR/rsn3UIg== X-Received: by 2002:a17:903:2452:b0:207:5d33:a1b8 with SMTP id d9443c01a7336-2076e3eab23mr226920575ad.38.1726501937573; Mon, 16 Sep 2024 08:52:17 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.52.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:17 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 12/17] bsd-user: Add generic RISC-V64 target definitions Date: Tue, 17 Sep 2024 01:51:14 +1000 Message-Id: <20240916155119.14610-13-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Warner Losh Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- bsd-user/riscv/target.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 bsd-user/riscv/target.h diff --git a/bsd-user/riscv/target.h b/bsd-user/riscv/target.h new file mode 100644 index 0000000000..036ddd185e --- /dev/null +++ b/bsd-user/riscv/target.h @@ -0,0 +1,20 @@ +/* + * Riscv64 general target stuff that's common to all aarch details + * + * Copyright (c) 2022 M. Warner Losh + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_H +#define TARGET_H + +/* + * riscv64 ABI does not 'lump' the registers for 64-bit args. + */ +static inline bool regpairs_aligned(void *cpu_env) +{ + return false; +} + +#endif /* TARGET_H */ From patchwork Mon Sep 16 15:51:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CD76C3ABB2 for ; Mon, 16 Sep 2024 15:53:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE1q-0001CO-A3; Mon, 16 Sep 2024 11:52:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE1b-0008Lr-3Z; Mon, 16 Sep 2024 11:52:31 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE1Z-0000X5-7x; Mon, 16 Sep 2024 11:52:26 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1fee6435a34so39974485ad.0; Mon, 16 Sep 2024 08:52:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501941; x=1727106741; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=voYN43OZ7lwbwneNl7z2eHNOhROV9NjNWmAvKPq1wXw=; b=LP3Fu7mBSHL54RqDFBe+MOZLc/3HLeG9E1hRPFWnDwlslKWpUcCEVlk4+XhSs3tZoe CSYWbEmGdpbotGPI/JtvJ4FeUjHmYCdcvOLsO4zmCDWuX18SiJddAKfvVj2o2e2wCND7 pWjzplBtrbrmk4yAh/52pcJXyeDwRlJzHSw8M46ND++LuFbBh/uJ66zW+p/ndM8I3bxF 3cdb5m/5bqfu756FfTis0agrqXQIaX97zXL5Wwit4dbkAAE1pRt1tr05EL5OtsNYFxPD PRkItD84HSrDLUdJmjXDN2WoFbE6lPG53zSIxl3ZbhA7QOzi8HHzj5pXBFJjTFC8LXJ6 g79A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501941; x=1727106741; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=voYN43OZ7lwbwneNl7z2eHNOhROV9NjNWmAvKPq1wXw=; b=tUSU02WYfMoq2Br5vVlXD3NQNxfvvePfSTs4RTDosMs4eBiNAjmDeeNFJcehw7hDPy za6a5205DYhTU99keMUcPX8fADlydN4/QH13Mzj2GFMD8hnLaBaaO1YHjg/l2pYt4muK EWBc2PryqQ23b8gRKUrwX9NGirQqTOVx2wkbGgEnOSQcs+eHLpJmS0rcmC8tRDiguqEW 5mxtMksKmwkDsbgfIZLbORfpdyfAlpyGjrRz/FfbcZq+9ULSAA22eZ0ao+xjDywmYPWE BdonvbGB/n9PAbEfat/qZdogFSfKPzBCxR7HYinSKoTSqmSEzlQiu6Ue4fxb4TNTdwHG uGlQ== X-Forwarded-Encrypted: i=1; AJvYcCWzg75/dQJ4kNAuScLpU+Jq11mbSziaCqCnV/+HrgxEMYwQKB28MtNJsI90JBhQHPX07ZORNvrClN8B@nongnu.org X-Gm-Message-State: AOJu0YwSrBiMHSv9ae74RT/XeH8m73KHsOhkC7xXNbdx72luD9Iuc2t1 ah4ImWzAUrZexzS1HiTvL6X6V8ePUNA+hiT4OMls1UfhklmWq15QM6SdMa6X X-Google-Smtp-Source: AGHT+IFz9LAWYvIZ716tCUa0YLHvfPU8zdanNYfeyDHJ2w9J1P6DYEpVtSn54g93WgcfjQyml5dwSA== X-Received: by 2002:a17:902:e5c8:b0:1fc:2e38:d3de with SMTP id d9443c01a7336-2076e315577mr251668655ad.7.1726501941458; Mon, 16 Sep 2024 08:52:21 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:20 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 13/17] bsd-user: Define RISC-V signal handling structures and constants Date: Tue, 17 Sep 2024 01:51:15 +1000 Message-Id: <20240916155119.14610-14-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/target_arch_signal.h | 75 +++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 bsd-user/riscv/target_arch_signal.h diff --git a/bsd-user/riscv/target_arch_signal.h b/bsd-user/riscv/target_arch_signal.h new file mode 100644 index 0000000000..1a634b865b --- /dev/null +++ b/bsd-user/riscv/target_arch_signal.h @@ -0,0 +1,75 @@ +/* + * RISC-V signal definitions + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef TARGET_ARCH_SIGNAL_H +#define TARGET_ARCH_SIGNAL_H + +#include "cpu.h" + + +#define TARGET_INSN_SIZE 4 /* riscv instruction size */ + +/* Size of the signal trampoline code placed on the stack. */ +#define TARGET_SZSIGCODE ((abi_ulong)(7 * TARGET_INSN_SIZE)) + +/* Compare with riscv/include/_limits.h */ +#define TARGET_MINSIGSTKSZ (1024 * 4) +#define TARGET_SIGSTKSZ (TARGET_MINSIGSTKSZ + 32768) + +struct target_gpregs { + uint64_t gp_ra; + uint64_t gp_sp; + uint64_t gp_gp; + uint64_t gp_tp; + uint64_t gp_t[7]; + uint64_t gp_s[12]; + uint64_t gp_a[8]; + uint64_t gp_sepc; + uint64_t gp_sstatus; +}; + +struct target_fpregs { + uint64_t fp_x[32][2]; + uint64_t fp_fcsr; + uint32_t fp_flags; + uint32_t pad; +}; + +typedef struct target_mcontext { + struct target_gpregs mc_gpregs; + struct target_fpregs mc_fpregs; + uint32_t mc_flags; +#define TARGET_MC_FP_VALID 0x01 + uint32_t mc_pad; + uint64_t mc_spare[8]; +} target_mcontext_t; + +#define TARGET_MCONTEXT_SIZE 864 +#define TARGET_UCONTEXT_SIZE 936 + +#include "target_os_ucontext.h" + +struct target_sigframe { + target_ucontext_t sf_uc; /* = *sf_uncontext */ + target_siginfo_t sf_si; /* = *sf_siginfo (SA_SIGINFO case)*/ +}; + +#define TARGET_SIGSTACK_ALIGN 16 + +#endif /* TARGET_ARCH_SIGNAL_H */ From patchwork Mon Sep 16 15:51:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3FF66C3ABA2 for ; Mon, 16 Sep 2024 15:55:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE1r-0001MR-70; Mon, 16 Sep 2024 11:52:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE1e-0008PX-17; Mon, 16 Sep 2024 11:52:31 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE1b-0000XI-Js; Mon, 16 Sep 2024 11:52:29 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-2068acc8b98so41073755ad.3; Mon, 16 Sep 2024 08:52:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501945; x=1727106745; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7+bsO6A/4UIjh+UAI8JcbcWlILl99UyeWUeQ1BHs21E=; b=nlKjiSdP+4HJwblDeNkYylJVNc3t7CPxKRcW+NWhbwcl9mLEHjtqNQGOwfvIptRW+r pqEeZst1LE6tloYcnD2ZewSqHvqmrW72q2iA3n0XRbjoDzoAyu0utLMvf0sqzYWLzJHe ixqsuxuDa8bzYY378PI0ICVbNFar98nXuUK170jbY/iAHB8kMxebyeZB14xEERCAXyqM dZY7rYshbeMrqF3fhQW97YQtJBs7+DHh8XaYXmmUF9evGz2hGfkmAw8G7zkv4AFDLmPs k/vFjSaNN9Zf3GspziM5P2YHAjvsLznE+9CXgNcK1B8Fkprs6I90btMPiXse9wQSvgrf bGgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501945; x=1727106745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7+bsO6A/4UIjh+UAI8JcbcWlILl99UyeWUeQ1BHs21E=; b=RE/DRJI+pJhoJNqY4P71ly6aLQczCNvnDNqjhsp3wqE3OKBtwpKovCksyvnsUXQaeJ +w5TE+d6078ksJUGYwHaJsWwqtlcDNYJCTf4zV6foK1EaO7+uKTU+N63nBks9XoLuCZs tIKJyKBHsfyM0fNq3Utr6tk5x1bf1FUP22z7W+MQR+7nmtKWpv7Lnj1fzBrRETNdU4U7 fH64TJi+Kbxy8a03gh9+3QSzmyCcNqhV3qBtVig7O+FjBZDfR1M5N8g/xAOizxQrPXa9 QrvEnBkgLF2Ag2uk9N/vTmPYfzHZZk3lEoCodyDi8VKaIinUfQdJldHW8HUoRWymX4Ls C+SA== X-Forwarded-Encrypted: i=1; AJvYcCXmoh3SNxeTjIg8ExsAWAXBwvt55EMT8aAs2s1MkJMe5jwosAwefwgk83a2qQkO9YbfKbVvP5hhw2Qq@nongnu.org X-Gm-Message-State: AOJu0Yw7MEvnNPm58RH7eZJ4+3UuzL/3575EsLmFc+3XqILNjKYJo4np g3xA//yXTQfzgG/PJ0sfHkDCndyLxnrpaxHAfF0vnjv3RWdN8+obEH4+K0xq X-Google-Smtp-Source: AGHT+IE+lLUO/w4LSP+HO92NTOEzp4eSgI9EbsewCkTijnq722+MSZfHXVfs0xn0/PvDHLXpnECwWw== X-Received: by 2002:a17:902:da92:b0:207:1696:6ee1 with SMTP id d9443c01a7336-2076e31f057mr243423705ad.10.1726501945236; Mon, 16 Sep 2024 08:52:25 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:24 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 14/17] bsd-user: Implement RISC-V signal trampoline setup functions Date: Tue, 17 Sep 2024 01:51:16 +1000 Message-Id: <20240916155119.14610-15-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added functions for setting up the RISC-V signal trampoline and signal frame: 'set_sigtramp_args()': Configures the RISC-V CPU state with arguments for the signal handler. It sets up the registers with the signal number,pointers to the signal info and user context, the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 63 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 bsd-user/riscv/signal.c diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signal.c new file mode 100644 index 0000000000..2597fec2fd --- /dev/null +++ b/bsd-user/riscv/signal.c @@ -0,0 +1,63 @@ +/* + * RISC-V signal definitions + * + * Copyright (c) 2019 Mark Corbin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ +#include "qemu/osdep.h" + +#include "qemu.h" + +/* + * Compare with sendsig() in riscv/riscv/exec_machdep.c + * Assumes that target stack frame memory is locked. + */ +abi_long +set_sigtramp_args(CPURISCVState *regs, int sig, struct target_sigframe *frame, + abi_ulong frame_addr, struct target_sigaction *ka) +{ + /* + * Arguments to signal handler: + * a0 (10) = signal number + * a1 (11) = siginfo pointer + * a2 (12) = ucontext pointer + * pc = signal pointer handler + * sp (2) = sigframe pointer + * ra (1) = sigtramp at base of user stack + */ + + regs->gpr[xA0] = sig; + regs->gpr[xA1] = frame_addr + + offsetof(struct target_sigframe, sf_si); + regs->gpr[xA2] = frame_addr + + offsetof(struct target_sigframe, sf_uc); + regs->pc = ka->_sa_handler; + regs->gpr[xSP] = frame_addr; + regs->gpr[xRA] = TARGET_PS_STRINGS - TARGET_SZSIGCODE; + return 0; +} + +/* + * Compare to riscv/riscv/exec_machdep.c sendsig() + * Assumes that the memory is locked if frame points to user memory. + */ +abi_long setup_sigframe_arch(CPURISCVState *env, abi_ulong frame_addr, + struct target_sigframe *frame, int flags) +{ + target_mcontext_t *mcp = &frame->sf_uc.uc_mcontext; + + get_mcontext(env, mcp, flags); + return 0; +} From patchwork Mon Sep 16 15:51:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8978C3ABA2 for ; Mon, 16 Sep 2024 15:53:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sqE1o-0000qH-Kt; Mon, 16 Sep 2024 11:52:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sqE1h-0000BG-P3; Mon, 16 Sep 2024 11:52:36 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1sqE1f-0000Xc-Cx; Mon, 16 Sep 2024 11:52:33 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2068acc8b98so41074865ad.3; Mon, 16 Sep 2024 08:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726501949; x=1727106749; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gy74LlRTmtwc1XLq4kdnjaS7OlYM0YhDmnWN/nXgpX8=; b=l7Sdz9yewldxuG54C1sluF7w8G5hMDWw2du2u5NyLevGMcyMYEJKLtmEt1/6pyjZYb cao0ECjMwOHGzS9jFudjxpvV0cHwAubq7WstoLl6IoXK5H7Pl73rkCah9/gRDnbVivri jLhOmmo73JYMNbCou7Mtr0rDolfkyRpPu62qoWDw42xPuP7F4so4W9buEixgKLWSqF/O m3E5vWCgaiiF7cFgPVxXn6/Vnk2F5Enb0N5w9XDQ7JFgFWtfP7GuMhdXpUDyVYKwCTKk QqVZ23YG32+ql2fZS40nojrB+AQCt0arivnj04+MBdVYwtTD84aAX012fFWnGMKVCl8/ OCgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726501949; x=1727106749; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gy74LlRTmtwc1XLq4kdnjaS7OlYM0YhDmnWN/nXgpX8=; b=llXWfVdk3m+fM7Hp0S/kKAZ1iCMfKQhy05TNofKC9ip2vbsHUoUgK+sn+F//0InaVO NJELkf3nQ0/QK0YO5W3qZr8Wmf/LNwPi3UnHkxE7EOH7CciOPzfKHE0MccfJ4zEsnCfw MBtJBhOY1lwEqS6KeQ6+PQqBDwyszCeONL01HIE16nRFhbMRUpEeAc8xkwpd1clkmQwq Wj6mTGAy2+7cg135BNJ3UKDbr/IwQ0E2TYKAjZ2hL0sDkCQcCAL6WbV25Tv/ML08kjZ7 mQvod3hiWh0U53FEOpaneN7Cnxp86121XVcaW4/MOSAelxgFGmII3SiN7Gb1CCCrdc6G wrdA== X-Forwarded-Encrypted: i=1; AJvYcCWMIe9E2ik7lk0XantY2AbyPSkkB9BpLhByzwASB/WckNLRcKvP9birRAphWNx7OovwHAHm4x7bXR3d@nongnu.org X-Gm-Message-State: AOJu0Yw3Z4UGQHvJPRha042Vr+QIGRTkMBzJMS02WK2/sDTRk5bwR0lE hdEYmmEDB4o1EtXgrl3NflFq/X1KzhpclbKRwfdjNTOQG1gvUJYFZ0KigRYc X-Google-Smtp-Source: AGHT+IGgk6+966iMiNmvFsxvh5f1gxq8lekqd9CfDXwlcR5kBFWJGnOfck2PHGJtAGZUMDBLXOdPzw== X-Received: by 2002:a17:902:d4c1:b0:205:913b:d9ad with SMTP id d9443c01a7336-2076d6268ffmr214405795ad.0.1726501949300; Mon, 16 Sep 2024 08:52:29 -0700 (PDT) Received: from localhost.localdomain (27-32-110-191.tpgi.com.au. [27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:28 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Date: Tue, 17 Sep 2024 01:51:17 +1000 Message-Id: <20240916155119.14610-16-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added the 'get_mcontext' function to extract and populate the RISC-V machine context from the CPU state. This function is used to gather the current state of the general-purpose registers and store it in a 'target_mcontext_' structure. Signed-off-by: Mark Corbin Signed-off-by: Ajeet Singh Signed-off-by: Warner Losh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 53 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signal.c index 2597fec2fd..072ad821d2 100644 --- a/bsd-user/riscv/signal.c +++ b/bsd-user/riscv/signal.c @@ -61,3 +61,56 @@ abi_long setup_sigframe_arch(CPURISCVState *env, abi_ulong frame_addr, get_mcontext(env, mcp, flags); return 0; } + +/* + * Compare with get_mcontext() in riscv/riscv/machdep.c + * Assumes that the memory is locked if mcp points to user memory. + */ +abi_long get_mcontext(CPURISCVState *regs, target_mcontext_t *mcp, + int flags) +{ + + mcp->mc_gpregs.gp_t[0] = tswap64(regs->gpr[5]); + mcp->mc_gpregs.gp_t[1] = tswap64(regs->gpr[6]); + mcp->mc_gpregs.gp_t[2] = tswap64(regs->gpr[7]); + mcp->mc_gpregs.gp_t[3] = tswap64(regs->gpr[28]); + mcp->mc_gpregs.gp_t[4] = tswap64(regs->gpr[29]); + mcp->mc_gpregs.gp_t[5] = tswap64(regs->gpr[30]); + mcp->mc_gpregs.gp_t[6] = tswap64(regs->gpr[31]); + + mcp->mc_gpregs.gp_s[0] = tswap64(regs->gpr[8]); + mcp->mc_gpregs.gp_s[1] = tswap64(regs->gpr[9]); + mcp->mc_gpregs.gp_s[2] = tswap64(regs->gpr[18]); + mcp->mc_gpregs.gp_s[3] = tswap64(regs->gpr[19]); + mcp->mc_gpregs.gp_s[4] = tswap64(regs->gpr[20]); + mcp->mc_gpregs.gp_s[5] = tswap64(regs->gpr[21]); + mcp->mc_gpregs.gp_s[6] = tswap64(regs->gpr[22]); + mcp->mc_gpregs.gp_s[7] = tswap64(regs->gpr[23]); + mcp->mc_gpregs.gp_s[8] = tswap64(regs->gpr[24]); + mcp->mc_gpregs.gp_s[9] = tswap64(regs->gpr[25]); + mcp->mc_gpregs.gp_s[10] = tswap64(regs->gpr[26]); + mcp->mc_gpregs.gp_s[11] = tswap64(regs->gpr[27]); + + mcp->mc_gpregs.gp_a[0] = tswap64(regs->gpr[10]); + mcp->mc_gpregs.gp_a[1] = tswap64(regs->gpr[11]); + mcp->mc_gpregs.gp_a[2] = tswap64(regs->gpr[12]); + mcp->mc_gpregs.gp_a[3] = tswap64(regs->gpr[13]); + mcp->mc_gpregs.gp_a[4] = tswap64(regs->gpr[14]); + mcp->mc_gpregs.gp_a[5] = tswap64(regs->gpr[15]); + mcp->mc_gpregs.gp_a[6] = tswap64(regs->gpr[16]); + mcp->mc_gpregs.gp_a[7] = tswap64(regs->gpr[17]); + + if (flags & TARGET_MC_GET_CLEAR_RET) { + mcp->mc_gpregs.gp_a[0] = 0; /* a0 */ + mcp->mc_gpregs.gp_a[1] = 0; /* a1 */ + mcp->mc_gpregs.gp_t[0] = 0; /* clear syscall error */ + } + + mcp->mc_gpregs.gp_ra = tswap64(regs->gpr[1]); + mcp->mc_gpregs.gp_sp = tswap64(regs->gpr[2]); + mcp->mc_gpregs.gp_gp = tswap64(regs->gpr[3]); + mcp->mc_gpregs.gp_tp = tswap64(regs->gpr[4]); + mcp->mc_gpregs.gp_sepc = tswap64(regs->pc); + + return 0; +} From patchwork Mon Sep 16 15:51:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA7A9C3ABB2 for ; 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[27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:32 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Date: Tue, 17 Sep 2024 01:51:18 +1000 Message-Id: <20240916155119.14610-17-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Corbin Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Co-authored-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/riscv/signal.c | 54 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signal.c index 072ad821d2..10c940cd49 100644 --- a/bsd-user/riscv/signal.c +++ b/bsd-user/riscv/signal.c @@ -114,3 +114,57 @@ abi_long get_mcontext(CPURISCVState *regs, target_mcontext_t *mcp, return 0; } + +/* Compare with set_mcontext() in riscv/riscv/exec_machdep.c */ +abi_long set_mcontext(CPURISCVState *regs, target_mcontext_t *mcp, + int srflag) +{ + + regs->gpr[5] = tswap64(mcp->mc_gpregs.gp_t[0]); + regs->gpr[6] = tswap64(mcp->mc_gpregs.gp_t[1]); + regs->gpr[7] = tswap64(mcp->mc_gpregs.gp_t[2]); + regs->gpr[28] = tswap64(mcp->mc_gpregs.gp_t[3]); + regs->gpr[29] = tswap64(mcp->mc_gpregs.gp_t[4]); + regs->gpr[30] = tswap64(mcp->mc_gpregs.gp_t[5]); + regs->gpr[31] = tswap64(mcp->mc_gpregs.gp_t[6]); + + regs->gpr[8] = tswap64(mcp->mc_gpregs.gp_s[0]); + regs->gpr[9] = tswap64(mcp->mc_gpregs.gp_s[1]); + regs->gpr[18] = tswap64(mcp->mc_gpregs.gp_s[2]); + regs->gpr[19] = tswap64(mcp->mc_gpregs.gp_s[3]); + regs->gpr[20] = tswap64(mcp->mc_gpregs.gp_s[4]); + regs->gpr[21] = tswap64(mcp->mc_gpregs.gp_s[5]); + regs->gpr[22] = tswap64(mcp->mc_gpregs.gp_s[6]); + regs->gpr[23] = tswap64(mcp->mc_gpregs.gp_s[7]); + regs->gpr[24] = tswap64(mcp->mc_gpregs.gp_s[8]); + regs->gpr[25] = tswap64(mcp->mc_gpregs.gp_s[9]); + regs->gpr[26] = tswap64(mcp->mc_gpregs.gp_s[10]); + regs->gpr[27] = tswap64(mcp->mc_gpregs.gp_s[11]); + + regs->gpr[10] = tswap64(mcp->mc_gpregs.gp_a[0]); + regs->gpr[11] = tswap64(mcp->mc_gpregs.gp_a[1]); + regs->gpr[12] = tswap64(mcp->mc_gpregs.gp_a[2]); + regs->gpr[13] = tswap64(mcp->mc_gpregs.gp_a[3]); + regs->gpr[14] = tswap64(mcp->mc_gpregs.gp_a[4]); + regs->gpr[15] = tswap64(mcp->mc_gpregs.gp_a[5]); + regs->gpr[16] = tswap64(mcp->mc_gpregs.gp_a[6]); + regs->gpr[17] = tswap64(mcp->mc_gpregs.gp_a[7]); + + + regs->gpr[1] = tswap64(mcp->mc_gpregs.gp_ra); + regs->gpr[2] = tswap64(mcp->mc_gpregs.gp_sp); + regs->gpr[3] = tswap64(mcp->mc_gpregs.gp_gp); + regs->gpr[4] = tswap64(mcp->mc_gpregs.gp_tp); + regs->pc = tswap64(mcp->mc_gpregs.gp_sepc); + + return 0; +} + +/* Compare with sys_sigreturn() in riscv/riscv/machdep.c */ +abi_long get_ucontext_sigreturn(CPURISCVState *regs, + abi_ulong target_sf, abi_ulong *target_uc) +{ + + *target_uc = target_sf; + return 0; +} From patchwork Mon Sep 16 15:51:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajeet Singh X-Patchwork-Id: 13805604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7D6DC3ABB2 for ; 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[27.32.110.191]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-207946046cbsm37482545ad.105.2024.09.16.08.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2024 08:52:36 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Alistair Francis , Mark Corbin , qemu-riscv@nongnu.org, Warner Losh , Daniel Henrique Barboza , Ajeet Singh , Richard Henderson Subject: [PATCH v7 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Date: Tue, 17 Sep 2024 01:51:19 +1000 Message-Id: <20240916155119.14610-18-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240916155119.14610-1-itachis@FreeBSD.org> References: <20240916155119.14610-1-itachis@FreeBSD.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=itachis6234@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Warner Losh Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson --- configs/targets/riscv64-bsd-user.mak | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 configs/targets/riscv64-bsd-user.mak diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak new file mode 100644 index 0000000000..191c2c483f --- /dev/null +++ b/configs/targets/riscv64-bsd-user.mak @@ -0,0 +1,4 @@ +TARGET_ARCH=riscv64 +TARGET_BASE_ARCH=riscv +TARGET_ABI_DIR=riscv +TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml