From patchwork Tue Sep 17 09:26:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Garg, Nemesa" X-Patchwork-Id: 13806036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6503BC3ABD2 for ; Tue, 17 Sep 2024 09:26:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C550110E44C; Tue, 17 Sep 2024 09:26:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Js+OHdLd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id A0C7310E44A; Tue, 17 Sep 2024 09:26:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726565217; x=1758101217; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EHGmdOmf4sMgC7OTdRLNHeBTRsmBIPObEuaWU3d/lFU=; b=Js+OHdLdwZpQ/4hEzbOkoRQDW5eUa76BldzXk6YocPYsU4xZi+SOWH5K X5wvpqHlxWBl414XITvXH43/t2UQLNgpBdkZwphnHhST9mzWUu/nzfa6/ Ab72tTYTr24ovs+kSKnEZ2d9Qkxv4gZEPLr46IJcy/meBoWKEVbq70rLP w7JO51nQUA1hRBPo4fu+fQHoP4+RNzKsuZPF4iFXQR2e9LXWpqhBF0/hh R/wh9RcYR0ocU1+3Drl7uCPX13JrF5CZ9Iqhxd876gkPJlIu8MIEY0U4F 1ojZRbxs8ie5c3/CZBaozs7HJ2MxHpCqBYr2Q0ptT9AhtDwxMrTP7TGuv g==; X-CSE-ConnectionGUID: 0xtXZah7RLWyEBAVnMUHqw== X-CSE-MsgGUID: 7DVLD7nMQ5ScFNS3wg0ixA== X-IronPort-AV: E=McAfee;i="6700,10204,11197"; a="36789032" X-IronPort-AV: E=Sophos;i="6.10,235,1719903600"; d="scan'208";a="36789032" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2024 02:26:55 -0700 X-CSE-ConnectionGUID: PF0S+CvuQM2Vt3tmvR60pA== X-CSE-MsgGUID: Fng8SxpwTASRRJGJP7uCQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,235,1719903600"; d="scan'208";a="99815980" Received: from nemesa.iind.intel.com ([10.190.239.22]) by orviesa002.jf.intel.com with ESMTP; 17 Sep 2024 02:26:53 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH v2 1/5] drm: Introduce sharpness strength property Date: Tue, 17 Sep 2024 14:56:30 +0530 Message-Id: <20240917092634.1109572-2-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917092634.1109572-1-nemesa.garg@intel.com> References: <20240917092634.1109572-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Introduces the new crtc property "SHARPNESS_STRENGTH" that allows the user to set the intensity so as to get the sharpness effect. The value of this property can be set from 0-255. It is useful in scenario when the output is blurry and user want to sharpen the pixels. User can increase/decrease the sharpness level depending on the content displayed. v2: Rename crtc property variable [Arun] Add modeset detail in uapi doc[Uma] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/drm_atomic_uapi.c | 4 ++++ drivers/gpu/drm/drm_crtc.c | 35 +++++++++++++++++++++++++++++++ include/drm/drm_crtc.h | 17 +++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 7936c2023955..515ddc472f41 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -417,6 +417,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, set_out_fence_for_crtc(state->state, crtc, fence_ptr); } else if (property == crtc->scaling_filter_property) { state->scaling_filter = val; + } else if (property == crtc->sharpness_strength_property) { + state->sharpness_strength = val; } else if (crtc->funcs->atomic_set_property) { return crtc->funcs->atomic_set_property(crtc, state, property, val); } else { @@ -454,6 +456,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = 0; else if (property == crtc->scaling_filter_property) *val = state->scaling_filter; + else if (property == crtc->sharpness_strength_property) + *val = state->sharpness_strength; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else { diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 3488ff067c69..c4a267fa3402 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -229,6 +229,25 @@ struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc) * Driver's default scaling filter * Nearest Neighbor: * Nearest Neighbor scaling filter + * SHARPNESS_STRENGTH: + * Atomic property for setting the sharpness strength/intensity by userspace. + * + * The value of this property is set as an integer value ranging + * from 0 - 255 where: + * + * 0 means feature is disabled. + * + * 1 means minimum sharpness. + * + * 255 means maximum sharpness. + * + * User can gradually increase or decrease the sharpness level and can + * set the optimum value depending on content and this value will be + * passed to kernel through the Uapi. + * The setting of this property does not require modeset. + * The sharpness effect takes place post blending on the final composed output. + * If the feature is disabled, the content remains same without any sharpening effect + * and when this feature is applied, it enhances the clarity of the content. */ __printf(6, 0) @@ -939,3 +958,19 @@ int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, return 0; } EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property); + +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_property *prop = + drm_property_create_range(dev, 0, "SHARPNESS_STRENGTH", 0, 255); + + if (!prop) + return -ENOMEM; + + crtc->sharpness_strength_property = prop; + drm_object_attach_property(&crtc->base, prop, 0); + + return 0; +} +EXPORT_SYMBOL(drm_crtc_create_sharpness_strength_property); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 8b48a1974da3..37a879350b4e 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -317,6 +317,16 @@ struct drm_crtc_state { */ enum drm_scaling_filter scaling_filter; + /** + * @sharpness_strength + * + * Used by the user to set the sharpness intensity. + * The value ranges from 0-255. + * Any value greater than 0 means enabling the featuring + * along with setting the value for sharpness. + */ + u8 sharpness_strength; + /** * @event: * @@ -1088,6 +1098,12 @@ struct drm_crtc { */ struct drm_property *scaling_filter_property; + /** + * @sharpness_strength_prop: property to apply + * the intensity of the sharpness requested. + */ + struct drm_property *sharpness_strength_property; + /** * @state: * @@ -1324,4 +1340,5 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev, int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, unsigned int supported_filters); +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc); #endif /* __DRM_CRTC_H__ */ From patchwork Tue Sep 17 09:26:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Garg, Nemesa" X-Patchwork-Id: 13806037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D214EC36000 for ; Tue, 17 Sep 2024 09:27:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D92D10E44E; Tue, 17 Sep 2024 09:26:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ILyqUGrN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id C42F510E44C; Tue, 17 Sep 2024 09:26:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726565218; x=1758101218; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h44K62pB2weucxX5xc7OLq6Qiu/UYAXUNC70yt/j+7A=; b=ILyqUGrNdoHI0lDQdKGFVQYSiKWDEMJeedxUsOGk80/Zy6RToOQYL4IS DwgumwK7HC0Xn0XVKiqGmi2cm25iSqzzaoqH/7yd3zTsqP7tlK2B43MCe uy+pEoL67yC4XtV3D0zzmY1sb+FJ8uShkP7I+/l+ZDmBME8fNlQZ+LpCb E9uj4KkoKUxc9AbXCXT4FWBItJTWgmMLksWZ+ha9TJbSFIHeFXcXDU3vP Ei2oMsLR+JOrCdaG3Uzu1omp1+Pqybkhmw/+IVW4zGLAjcm75024S2j6b uGmDOrXMo2LogEfJ7uLJ7y0khhrqyiq1CeD3Ya7jc6pc/az8aCVscpLq0 w==; X-CSE-ConnectionGUID: MKuCLlNXThaluPzMXHWong== X-CSE-MsgGUID: zoyNt5v4Suy7eGP9c+MQKA== X-IronPort-AV: E=McAfee;i="6700,10204,11197"; a="36789037" X-IronPort-AV: E=Sophos;i="6.10,235,1719903600"; d="scan'208";a="36789037" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2024 02:26:58 -0700 X-CSE-ConnectionGUID: dpFWG49pTFqiZK15fthDlw== X-CSE-MsgGUID: AfOp+nAbSW65yrGI6+CqLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,235,1719903600"; d="scan'208";a="99815986" Received: from nemesa.iind.intel.com ([10.190.239.22]) by orviesa002.jf.intel.com with ESMTP; 17 Sep 2024 02:26:56 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH v3 2/5] drm/i915/display: Compute the scaler filter coefficients Date: Tue, 17 Sep 2024 14:56:31 +0530 Message-Id: <20240917092634.1109572-3-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917092634.1109572-1-nemesa.garg@intel.com> References: <20240917092634.1109572-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The sharpness property requires the use of one of the scaler so need to set the sharpness scaler coefficient values. These values are based on experiments and vary for different tap value/win size. These values are normalized by taking the sum of all values and then dividing each value with a sum. v2: Fix ifndef header naming issue reported by kernel test robot v3: Rename file name[Arun] Replace array size number with macro[Arun] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_display.c | 2 + .../drm/i915/display/intel_display_types.h | 2 + .../drm/i915/display/intel_sharpness_filter.c | 106 ++++++++++++++++++ .../drm/i915/display/intel_sharpness_filter.h | 38 +++++++ drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/xe/Makefile | 1 + 7 files changed, 152 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_sharpness_filter.c create mode 100644 drivers/gpu/drm/i915/display/intel_sharpness_filter.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index c63fa2133ccb..28e5f3b95371 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -280,6 +280,7 @@ i915-y += \ display/intel_pmdemand.o \ display/intel_psr.o \ display/intel_quirks.o \ + display/intel_sharpness_filter.o \ display/intel_sprite.o \ display/intel_sprite_uapi.o \ display/intel_tc.o \ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b4ef4d59da1a..e447a316ec38 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5917,6 +5917,8 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) if (ret) return ret; + intel_sharpness_scaler_compute_config(new_crtc_state); + /* * On some platforms the number of active planes affects * the planes' minimum cdclk calculation. Add such planes diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index f29e5dc3db91..5636f9b60d5d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -56,6 +56,7 @@ #include "intel_display_power.h" #include "intel_dpll_mgr.h" #include "intel_wm_types.h" +#include "intel_sharpness_filter.h" struct drm_printer; struct __intel_global_objs_state; @@ -1072,6 +1073,7 @@ struct intel_crtc_state { struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; struct drm_display_mode mode, pipe_mode, adjusted_mode; enum drm_scaling_filter scaling_filter; + struct intel_sharpness_filter casf_params; } hw; /* actual state of LUTs */ diff --git a/drivers/gpu/drm/i915/display/intel_sharpness_filter.c b/drivers/gpu/drm/i915/display/intel_sharpness_filter.c new file mode 100644 index 000000000000..e5fbffbe0428 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_sharpness_filter.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + * + */ + +#include "i915_reg.h" +#include "intel_de.h" +#include "intel_display_types.h" +#include "skl_scaler.h" + +#define MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER 7 +#define SCALER_FILTER_NUM_TAPS 7 +#define SCALER_FILTER_NUM_PHASES 17 +#define FILTER_COEFF_0_125 125 +#define FILTER_COEFF_0_25 250 +#define FILTER_COEFF_0_5 500 +#define FILTER_COEFF_1_0 1000 +#define FILTER_COEFF_0_0 0 + +const u16 filtercoeff_1[] = {FILTER_COEFF_0_0, FILTER_COEFF_0_0, +FILTER_COEFF_0_5, FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0, FILTER_COEFF_0_0}; + +const u16 filtercoeff_2[] = {FILTER_COEFF_0_0, FILTER_COEFF_0_25, +FILTER_COEFF_0_5, FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, FILTER_COEFF_0_0}; + +const u16 filtercoeff_3[] = {FILTER_COEFF_0_125, FILTER_COEFF_0_25, +FILTER_COEFF_0_5, FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, FILTER_COEFF_0_125}; + +void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + int id = crtc_state->scaler_state.scaler_id; + + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0), + PS_COEF_INDEX_AUTO_INC); + + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 1), + PS_COEF_INDEX_AUTO_INC); + + for (int index = 0; index < 60; index++) { + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0), + crtc_state->hw.casf_params.scaler_coefficient[index]); + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 1), + crtc_state->hw.casf_params. scaler_coefficient[index]); + } +} + +static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, + u16 coefficient) +{ + if (coefficient < 25) { + coeff->mantissa = (coefficient * 2048) / 100; + coeff->exp = 3; + } else if (coefficient < 50) { + coeff->mantissa = (coefficient * 1024) / 100; + coeff->exp = 2; + } else if (coefficient < 100) { + coeff->mantissa = (coefficient * 512) / 100; + coeff->exp = 1; + } else { + coeff->mantissa = (coefficient * 256) / 100; + coeff->exp = 0; + } +} + +static void intel_sharpness_filter_coeff(struct intel_crtc_state *crtc_state) +{ + const u16 *filtercoeff; + u16 filter_coeff[MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER]; + u16 sumcoeff = 0; + u8 i; + + if (crtc_state->hw.casf_params.win_size == 0) + filtercoeff = filtercoeff_1; + else if (crtc_state->hw.casf_params.win_size == 1) + filtercoeff = filtercoeff_2; + else + filtercoeff = filtercoeff_3; + + for (i = 0; i < MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER; i++) + sumcoeff += *(filtercoeff + i); + + for (i = 0; i < MAX_NUM_UNIQUE_COEF_FOR_SHARPNESS_FILTER; i++) { + filter_coeff[i] = (*(filtercoeff + i) * 100 / sumcoeff); + convert_sharpness_coef_binary(&crtc_state->hw.casf_params.coeff[i], + filter_coeff[i]); + } +} + +void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state) +{ + u16 phase, tapindex, phaseoffset; + u16 *coeff = (u16 *)crtc_state->hw.casf_params.scaler_coefficient; + + intel_sharpness_filter_coeff(crtc_state); + + for (phase = 0; phase < SCALER_FILTER_NUM_PHASES; phase++) { + phaseoffset = SCALER_FILTER_NUM_TAPS * phase; + for (tapindex = 0; tapindex < SCALER_FILTER_NUM_TAPS; tapindex++) { + coeff[phaseoffset + tapindex] = + SHARP_COEFF_TO_REG_FORMAT(crtc_state->hw.casf_params.coeff[tapindex]); + } + } +} diff --git a/drivers/gpu/drm/i915/display/intel_sharpness_filter.h b/drivers/gpu/drm/i915/display/intel_sharpness_filter.h new file mode 100644 index 000000000000..d1dc65e747fe --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_sharpness_filter.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_SHARPNESS_FILTER_H__ +#define __INTEL_SHARPNESS_FILTER_H__ + +#include + +#define SHARP_COEFF_TO_REG_FORMAT(coefficient) ((u16)(coefficient.sign << 15 | \ + coefficient.exp << 12 | coefficient.mantissa << 3)) + +struct intel_crtc; +struct intel_crtc_state; +struct intel_atomic_state; + +struct scaler_filter_coeff { + u16 sign; + u16 exp; + u16 mantissa; +}; + +struct intel_sharpness_filter { +#define SCALER_FILTER_NUM_TAPS 7 +#define SCLAER_FILTER_COEFF 119 + struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; + u32 scaler_coefficient[SCLAER_FILTER_COEFF]; + bool strength_changed; + u8 win_size; + bool need_scaler; + u8 strength; +}; + +void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state); +void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state); + +#endif /* __INTEL_SHARPEN_FILTER_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 41f4350a7c6c..84b05b57ad52 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2257,6 +2257,8 @@ #define PS_VERT_INT_INVERT_FIELD REG_BIT(20) #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */ #define PS_PWRUP_PROGRESS REG_BIT(17) +#define PS_BYPASS_ARMING REG_BIT(10) +#define PS_DB_STALL REG_BIT(9) #define PS_V_FILTER_BYPASS REG_BIT(8) #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */ #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */ diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 8f1c5c329f79..26b4b516c9ec 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -254,6 +254,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_psr.o \ i915-display/intel_qp_tables.o \ i915-display/intel_quirks.o \ + i915-display/intel_sharpness_filter.o \ i915-display/intel_snps_phy.o \ i915-display/intel_tc.o \ i915-display/intel_vblank.o \ From patchwork Tue Sep 17 09:26:32 2024 Content-Type: text/plain; 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d="scan'208";a="99815991" Received: from nemesa.iind.intel.com ([10.190.239.22]) by orviesa002.jf.intel.com with ESMTP; 17 Sep 2024 02:26:59 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH v3 3/5] drm/i915/display: Enable the second scaler for sharpness Date: Tue, 17 Sep 2024 14:56:32 +0530 Message-Id: <20240917092634.1109572-4-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917092634.1109572-1-nemesa.garg@intel.com> References: <20240917092634.1109572-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" As only second scaler can be used for sharpness check if it is available and also check if panel fitting is also not enabled, then set the sharpness. Panel fitting will have the preference over sharpness property. v2: Add the panel fitting check before enabling sharpness v3: Reframe commit message[Arun] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_display.c | 10 ++- .../drm/i915/display/intel_modeset_verify.c | 1 + drivers/gpu/drm/i915/display/intel_panel.c | 7 ++ .../drm/i915/display/intel_sharpness_filter.c | 10 +++ .../drm/i915/display/intel_sharpness_filter.h | 1 + drivers/gpu/drm/i915/display/skl_scaler.c | 78 ++++++++++++++++--- drivers/gpu/drm/i915/display/skl_scaler.h | 1 + 7 files changed, 95 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e447a316ec38..a6e33238dac8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2039,7 +2039,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); if (crtc_state->pch_pfit.enabled || - crtc_state->pch_pfit.force_thru) + crtc_state->pch_pfit.force_thru || crtc_state->hw.casf_params.need_scaler) set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); drm_for_each_encoder_mask(encoder, &dev_priv->drm, @@ -2295,7 +2295,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) * PF-ID we'll need to adjust the pixel_rate here. */ - if (!crtc_state->pch_pfit.enabled) + if (!crtc_state->pch_pfit.enabled || crtc_state->hw.casf_params.need_scaler) return pixel_rate; drm_rect_init(&src, 0, 0, @@ -4306,7 +4306,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) >= 9) { if (intel_crtc_needs_modeset(crtc_state) || - intel_crtc_needs_fastset(crtc_state)) { + intel_crtc_needs_fastset(crtc_state) || + crtc_state->hw.casf_params.need_scaler) { ret = skl_update_scaler_crtc(crtc_state); if (ret) return ret; @@ -5492,6 +5493,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(cmrr.enable); } + if (pipe_config->uapi.sharpness_strength > 0) + PIPE_CONF_CHECK_BOOL(hw.casf_params.need_scaler); + #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_LLI diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index 3491db5cad31..ed75934bed6b 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -177,6 +177,7 @@ verify_crtc_state(struct intel_atomic_state *state, crtc->base.name); hw_crtc_state->hw.enable = sw_crtc_state->hw.enable; + hw_crtc_state->hw.casf_params.need_scaler = sw_crtc_state->hw.casf_params.need_scaler; intel_crtc_get_pipe_config(hw_crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 71454ddef20f..6ed13245bdc8 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -389,6 +389,9 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); int pipe_src_h = drm_rect_height(&crtc_state->pipe_src); int x, y, width, height; @@ -399,6 +402,9 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) return 0; + if (old_crtc_state->hw.casf_params.need_scaler) + return -EINVAL; + switch (conn_state->scaling_mode) { case DRM_MODE_SCALE_CENTER: width = pipe_src_w; @@ -451,6 +457,7 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, drm_rect_init(&crtc_state->pch_pfit.dst, x, y, width, height); + crtc_state->pch_pfit.enabled = true; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_sharpness_filter.c b/drivers/gpu/drm/i915/display/intel_sharpness_filter.c index e5fbffbe0428..42073aa25edc 100644 --- a/drivers/gpu/drm/i915/display/intel_sharpness_filter.c +++ b/drivers/gpu/drm/i915/display/intel_sharpness_filter.c @@ -45,6 +45,16 @@ void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state) intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 1), crtc_state->hw.casf_params. scaler_coefficient[index]); } + + casf_scaler_enable(crtc_state); +} + +int intel_sharpness_filter_compute_config(struct intel_crtc_state *crtc_state) +{ + if (!crtc_state->pch_pfit.enabled) + crtc_state->hw.casf_params.need_scaler = true; + + return 0; } static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, diff --git a/drivers/gpu/drm/i915/display/intel_sharpness_filter.h b/drivers/gpu/drm/i915/display/intel_sharpness_filter.h index d1dc65e747fe..84f47d511cdc 100644 --- a/drivers/gpu/drm/i915/display/intel_sharpness_filter.h +++ b/drivers/gpu/drm/i915/display/intel_sharpness_filter.h @@ -34,5 +34,6 @@ struct intel_sharpness_filter { void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state); void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state); +int intel_sharpness_filter_compute_config(struct intel_crtc_state *crtc_state); #endif /* __INTEL_SHARPEN_FILTER_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index baa601d27815..af40288a6709 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -97,7 +97,12 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) #define MTL_MAX_DST_H 8192 #define SKL_MIN_YUV_420_SRC_W 16 #define SKL_MIN_YUV_420_SRC_H 16 - +#define SCALER_FILTER_SELECT \ + (PS_FILTER_PROGRAMMED | \ + PS_Y_VERT_FILTER_SELECT(1) | \ + PS_Y_HORZ_FILTER_SELECT(0) | \ + PS_UV_VERT_FILTER_SELECT(1) | \ + PS_UV_HORZ_FILTER_SELECT(0)) static int skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, unsigned int scaler_user, int *scaler_id, @@ -253,7 +258,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) drm_rect_width(&crtc_state->pipe_src), drm_rect_height(&crtc_state->pipe_src), width, height, NULL, 0, - crtc_state->pch_pfit.enabled); + crtc_state->pch_pfit.enabled || + crtc_state->hw.casf_params.need_scaler); } /** @@ -353,9 +359,10 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat int num_scalers_need, struct intel_crtc *intel_crtc, const char *name, int idx, struct intel_plane_state *plane_state, - int *scaler_id) + int *scaler_id, bool casf_scaler) { struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + struct intel_crtc_state *crtc_state = to_intel_crtc_state(intel_crtc->base.state); int j; u32 mode; @@ -365,6 +372,11 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat if (scaler_state->scalers[j].in_use) continue; + if (!strcmp(name, "CRTC")) { + if (casf_scaler && j != 1) + continue; + } + *scaler_id = j; scaler_state->scalers[*scaler_id].in_use = 1; break; @@ -375,6 +387,10 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat "Cannot find scaler for %s:%d\n", name, idx)) return -EINVAL; + if (crtc_state->hw.casf_params.need_scaler) { + mode = SKL_PS_SCALER_MODE_HQ; + } + /* set scaler mode */ if (plane_state && plane_state->hw.fb && plane_state->hw.fb->format->is_yuv && @@ -598,7 +614,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need, intel_crtc, name, idx, - plane_state, scaler_id); + plane_state, scaler_id, + crtc_state->hw.casf_params.need_scaler); if (ret < 0) return ret; } @@ -705,6 +722,44 @@ static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe } } +void casf_scaler_enable(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc); + struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + struct drm_rect src, dest; + int id, width, height; + int x, y; + enum pipe pipe = crtc->pipe; + u32 ps_ctrl; + + width = adjusted_mode->crtc_hdisplay; + height = adjusted_mode->crtc_vdisplay; + + x = y = 0; + drm_rect_init(&dest, x, y, width, height); + + width = drm_rect_width(&dest); + height = drm_rect_height(&dest); + id = scaler_state->scaler_id; + + drm_rect_init(&src, 0, 0, + drm_rect_width(&crtc_state->pipe_src) << 16, + drm_rect_height(&crtc_state->pipe_src) << 16); + + ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | + PS_BYPASS_ARMING | PS_DB_STALL | SCALER_FILTER_SELECT; + + intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); + intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id), + PS_WIN_XPOS(x) | PS_WIN_YPOS(y)); + intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id), + PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); +} + void skl_pfit_enable(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -875,16 +930,19 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) continue; id = i; - crtc_state->pch_pfit.enabled = true; + + if (!crtc_state->hw.casf_params.need_scaler) + crtc_state->pch_pfit.enabled = true; pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); - drm_rect_init(&crtc_state->pch_pfit.dst, - REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), - REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); + if (!crtc_state->hw.casf_params.need_scaler) + drm_rect_init(&crtc_state->pch_pfit.dst, + REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), + REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); scaler_state->scalers[i].in_use = true; break; diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h index 63f93ca03c89..444527e6a15b 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.h +++ b/drivers/gpu/drm/i915/display/skl_scaler.h @@ -33,5 +33,6 @@ void skl_detach_scalers(const struct intel_crtc_state *crtc_state); void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); void skl_scaler_get_config(struct intel_crtc_state *crtc_state); +void casf_scaler_enable(struct intel_crtc_state *crtc_state); #endif From patchwork Tue Sep 17 09:26:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Garg, Nemesa" X-Patchwork-Id: 13806039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABAEEC36002 for ; Tue, 17 Sep 2024 09:27:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2098910E44D; Tue, 17 Sep 2024 09:27:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="36789048" X-IronPort-AV: E=Sophos;i="6.10,235,1719903600"; d="scan'208";a="36789048" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2024 02:27:03 -0700 X-CSE-ConnectionGUID: 9g68xvxpRW+9cy5AFK9u4g== X-CSE-MsgGUID: yQR0wJYCTiiYnauxSZOtDg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,235,1719903600"; d="scan'208";a="99816001" Received: from nemesa.iind.intel.com ([10.190.239.22]) by orviesa002.jf.intel.com with ESMTP; 17 Sep 2024 02:27:02 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH v2 4/5] drm/i915/display: Add registers and compute the strength Date: Tue, 17 Sep 2024 14:56:33 +0530 Message-Id: <20240917092634.1109572-5-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917092634.1109572-1-nemesa.garg@intel.com> References: <20240917092634.1109572-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add new registers and related bits. Compute the strength value and tap value based on display mode. v2: Replace i915/dev_priv with display[Jani] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_display.c | 7 +- .../drm/i915/display/intel_sharpness_filter.c | 112 +++++++++++++++++- .../drm/i915/display/intel_sharpness_filter.h | 5 + drivers/gpu/drm/i915/i915_reg.h | 17 +++ 4 files changed, 139 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a6e33238dac8..6fe434708cd7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5921,7 +5921,12 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) if (ret) return ret; - intel_sharpness_scaler_compute_config(new_crtc_state); + if (sharp_compute(new_crtc_state)) { + intel_sharpness_scaler_compute_config(new_crtc_state); + ret = intel_sharpness_filter_compute_config(new_crtc_state); + if (ret) + return ret; + } /* * On some platforms the number of active planes affects diff --git a/drivers/gpu/drm/i915/display/intel_sharpness_filter.c b/drivers/gpu/drm/i915/display/intel_sharpness_filter.c index 42073aa25edc..28cd5c51e5b8 100644 --- a/drivers/gpu/drm/i915/display/intel_sharpness_filter.c +++ b/drivers/gpu/drm/i915/display/intel_sharpness_filter.c @@ -27,11 +27,88 @@ FILTER_COEFF_0_5, FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, FILTER_ const u16 filtercoeff_3[] = {FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5, FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, FILTER_COEFF_0_125}; -void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state) +/* Default LUT values to be loaded one time. */ +static const u16 lut_data[] = { + 4095, 2047, 1364, 1022, 816, 678, 579, + 504, 444, 397, 357, 323, 293, 268, 244, 224, + 204, 187, 170, 154, 139, 125, 111, 98, 85, + 73, 60, 48, 36, 24, 12, 0 +}; + +void intel_filter_lut_load(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + int i; + + intel_de_write(display, SHRPLUT_INDEX(crtc->pipe), INDEX_AUTO_INCR | INDEX_VALUE(0)); + + for (i = 0; i < ARRAY_SIZE(lut_data); i++) + intel_de_write(display, SHRPLUT_DATA(crtc->pipe), lut_data[i]); +} + +static void intel_sharpness_filter_size_compute(struct intel_crtc_state *crtc_state) +{ + const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode; + + if (mode->hdisplay <= 1920 && mode->vdisplay <= 1080) + crtc_state->hw.casf_params.win_size = 0; + else if (mode->hdisplay <= 3840 && mode->vdisplay <= 2160) + crtc_state->hw.casf_params.win_size = 1; + else + crtc_state->hw.casf_params.win_size = 2; +} + +bool intel_sharpness_strength_changed(struct intel_atomic_state *state) +{ + int i; + struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_crtc *crtc; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (new_crtc_state->uapi.sharpness_strength != + old_crtc_state->uapi.sharpness_strength) + return true; + } + + return false; +} + +void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state) +{ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); int id = crtc_state->scaler_state.scaler_id; + u32 sharpness_ctl; + u8 val; + + if (crtc_state->uapi.sharpness_strength == 0 || + crtc_state->pch_pfit.enabled) { + intel_sharpness_disable(crtc_state); + + return; + } + + /* + * HW takes a value in form (1.0 + strength) in 4.4 fixed format. + * Strength is from 0.0-14.9375 ie from 0-239. + * User can give value from 0-255 but is clamped to 239. + * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125. + * 6.3125 in 4.4 format is 01100101 which is equal to 101. + * Also 85 + 16 = 101. + */ + val = min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10; + + drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", val); + + sharpness_ctl = FILTER_EN | FILTER_STRENGTH(val) | + FILTER_SIZE(crtc_state->hw.casf_params.win_size); + + intel_de_write(display, SHARPNESS_CTL(crtc->pipe), + sharpness_ctl); intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0), PS_COEF_INDEX_AUTO_INC); @@ -51,9 +128,24 @@ void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state) int intel_sharpness_filter_compute_config(struct intel_crtc_state *crtc_state) { + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + + if (crtc_state->uapi.sharpness_strength == 0) { + crtc_state->hw.casf_params.need_scaler = false; + return 0; + } + + if (crtc_state->pch_pfit.enabled) + return -EINVAL; + if (!crtc_state->pch_pfit.enabled) crtc_state->hw.casf_params.need_scaler = true; + intel_sharpness_filter_size_compute(crtc_state); + drm_dbg(&dev_priv->drm, "Tap Size: %d\n", + crtc_state->hw.casf_params.win_size); + return 0; } @@ -114,3 +206,21 @@ void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state) } } } + +void intel_sharpness_disable(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + intel_de_write(display, SHARPNESS_CTL(crtc->pipe), 0); + drm_dbg(&dev_priv->drm, "Filter strength value: %d\n", 0); +} + +bool sharp_compute(struct intel_crtc_state *crtc_state) +{ + if (!(FILTER_EN & 1) && crtc_state->uapi.sharpness_strength != 0) + return true; + + return false; +} diff --git a/drivers/gpu/drm/i915/display/intel_sharpness_filter.h b/drivers/gpu/drm/i915/display/intel_sharpness_filter.h index 84f47d511cdc..85b2b8975383 100644 --- a/drivers/gpu/drm/i915/display/intel_sharpness_filter.h +++ b/drivers/gpu/drm/i915/display/intel_sharpness_filter.h @@ -35,5 +35,10 @@ struct intel_sharpness_filter { void intel_sharpness_filter_enable(struct intel_crtc_state *crtc_state); void intel_sharpness_scaler_compute_config(struct intel_crtc_state *crtc_state); int intel_sharpness_filter_compute_config(struct intel_crtc_state *crtc_state); +void intel_filter_lut_load(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state); +bool intel_sharpness_strength_changed(struct intel_atomic_state *state); +void intel_sharpness_disable(struct intel_crtc_state *crtc_state); +bool sharp_compute(struct intel_crtc_state *crtc_state); #endif /* __INTEL_SHARPEN_FILTER_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 84b05b57ad52..41c6c56d83d6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2396,6 +2396,23 @@ _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) +#define _SHARPNESS_CTL_A 0x682B0 +#define SHARPNESS_CTL(trans) _MMIO_PIPE2(dev_priv, trans, _SHARPNESS_CTL_A) +#define FILTER_EN REG_BIT(31) +#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8) +#define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x)) +#define FILTER_SIZE_MASK REG_GENMASK(1, 0) +#define FILTER_SIZE(x) REG_FIELD_PREP(FILTER_SIZE_MASK, (x)) + +#define _SHRPLUT_DATA_A 0x682B8 +#define SHRPLUT_DATA(trans) _MMIO_PIPE2(dev_priv, trans, _SHRPLUT_DATA_A) + +#define _SHRPLUT_INDEX_A 0x682B4 +#define SHRPLUT_INDEX(trans) _MMIO_PIPE2(dev_priv, trans, _SHRPLUT_INDEX_A) +#define INDEX_AUTO_INCR REG_BIT(10) +#define INDEX_VALUE_MASK REG_GENMASK(4, 0) +#define INDEX_VALUE(x) REG_FIELD_PREP(INDEX_VALUE_MASK, (x)) + /* Display Internal Timeout Register */ #define RM_TIMEOUT _MMIO(0x42060) #define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0) From patchwork Tue Sep 17 09:26:34 2024 Content-Type: text/plain; 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d="scan'208";a="99816011" Received: from nemesa.iind.intel.com ([10.190.239.22]) by orviesa002.jf.intel.com with ESMTP; 17 Sep 2024 02:27:04 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 5/5] drm/i915/display: Load the lut values and enable sharpness Date: Tue, 17 Sep 2024 14:56:34 +0530 Message-Id: <20240917092634.1109572-6-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240917092634.1109572-1-nemesa.garg@intel.com> References: <20240917092634.1109572-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Load the lut values during pipe enable. v2: Add the display version check Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++ drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++ drivers/gpu/drm/i915/display/skl_scaler.c | 13 ++++++++++++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 1b578cad2813..a8aaea0d2932 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -379,6 +379,9 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); + if (DISPLAY_VER(dev_priv) >= 20) + drm_crtc_create_sharpness_strength_property(&crtc->base); + return 0; fail: diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6fe434708cd7..f6f31f259262 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1782,6 +1782,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_crtc_wait_for_next_vblank(wa_crtc); } } + + if (new_crtc_state->hw.casf_params.strength_changed) + intel_filter_lut_load(crtc, new_crtc_state); } void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) @@ -6931,6 +6934,9 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_vrr_set_transcoder_timings(new_crtc_state); } + if (intel_sharpness_strength_changed(state)) + intel_sharpness_filter_enable(new_crtc_state); + intel_fbc_update(state, crtc); drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index af40288a6709..4bdec5c87945 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -923,7 +923,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) /* find scaler attached to this pipe */ for (i = 0; i < crtc->num_scalers; i++) { - u32 ctl, pos, size; + u32 ctl, pos, size, sharp; ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE)) @@ -931,6 +931,17 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) id = i; + if (DISPLAY_VER(dev_priv) >= 20) { + sharp = intel_de_read(dev_priv, SHARPNESS_CTL(crtc->pipe)); + if (sharp & FILTER_EN) { + crtc_state->hw.casf_params.strength = + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) - 16; + crtc_state->hw.casf_params.need_scaler = true; + crtc_state->hw.casf_params.win_size = + REG_FIELD_GET(FILTER_SIZE_MASK, sharp); + } + } + if (!crtc_state->hw.casf_params.need_scaler) crtc_state->pch_pfit.enabled = true;