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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini , "Bertrand Marquis" , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v2 1/4] xen/arm: mpu: Introduce choice between MMU and MPU Date: Wed, 18 Sep 2024 18:50:59 +0100 Message-ID: <20240918175102.223076-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240918175102.223076-1-ayan.kumar.halder@amd.com> References: <20240918175102.223076-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE8:EE_|LV2PR12MB5944:EE_ X-MS-Office365-Filtering-Correlation-Id: 64d39b26-64a7-41e1-6ef7-08dcd80a8eb4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: eOKLW/V/17YJC7jFVYRe2/2w1nLShFiWNu5z1QVYY9SFpQGmiXL7eg50/+CzVH5acQCvfWPEZ5ORVm4i0csKRtUoRh6z3AfnZS4tuvgD6Dsc/kZBbARnM1rtwVP9M1OrZlHMItaP6YopQi4f0STn1rE3DmdzJ9gEpnkO17NXrNZaF+BeIXR81gLpR/cc13GYHRCSV76gsBn8BXdzyMC2ZjyyiCf65BCbBf8SVRMVKLQT4QFgxeJf3b8p5lSVkmm9qvl2XFJmKTyFzNR+vohzGDOHLEf1BqA9Swz/ph+IwrGUvhy1LFN1TjJS9OR6fjE8RVs2ouOnm62dvJ/xn3V/jqnGfk/FJViKNpxLtIfqss3pdboGg3sxT8UjS78l+tX4hlDtJ9KfxzmQdlqYFKXkQNskLp7VFv4tp/2nieOaJgnJtUDfo3L5gPQSRYZ+0v9kmPnqgQQAvgISPaRl1kQHZ8Q0mpSGMF2j+SRWrPdkmyRP/FI6Mbwb9HIMq/ZD0F08R7lXauE7adh6VsiO40rxqJOvR0xwA53bb5joto5KTfLIXP4JWjT0lz4K17AfxLc5cOJYwtnCZ8rgWpJLW4g3tS5PmS/eEXaMY/9bAeraNZfzY5+IEgdSh8J5qGesPoejrDr/8BQwe67AjwDM+zQXgKlZ9z6yCF5/sx0Qst64/br73dg0D2Mr30qSqqwsyogxjl1+yrfXYy4m+irQA7cdQ/diDOKRYHesPbZCawqy6i4mfxD50aptwYfmMUCJOA2J3dQkKoQB7hXGaGKCRo3DFGIaT6ESdBfZu71UlOc9B91scF9Elrqg/Y/1624ozcDjGqR4WTxaOEU+LjR3V2mpBLvji7/zNBd861zDyUrWvLzPgZmwPlbc0MtVecNHkAQwC24xPilNgEU5P9GE8Inz7EbW07TLwmbY2HP+lwaA1fgxW0XcI/pZJlqMx2aEUkSqdh2tO1XCxGIRkhD6hTOJo/CEK1YmFEpX3kP/9OcBEaMbSIIfRbY0GKALD649UZ0gA231+luEgxeIeSDrlvyu+mwA+MhRu25FykI+P234o5vv2NS8JnW8LMyr0yPBSUnc/o4I3AXsAgDdYQqqgnkU8q250KQQJ6wQpWt5vHgwelgngXrWGFYvdGdiYpHKvK+YlOb+ax1SgbmVo4V/xQArkbWg+2UnBpcaAak1IpJSfge7UHO/qUpZU2Wm43t9y0e5bqZtSO/pf/lQy22/DniAXr7x0ozCOqT49L/Iw5ucJ3Zc/fUMeZCZkFkBIr9m09SlTUZmAf331WU0VaNWinOc8DzrDm6cBHBSZ7JAA82IeoI8w4sEi79izyKxBCmGF2opfhXhzKbzt8oJSJ/gfcxtKwMTe3bRCMhTRyu4SLnC+r6B+HnYEFajWPbK2KYydhyq0woonjJZBCEBJ8I/c0g4NzTaBhBSogJPBRQkqRsiaepKJNJo2zeELIh5J98VToH+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 17:51:43.3823 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64d39b26-64a7-41e1-6ef7-08dcd80a8eb4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5944 There are features in the forthcoming patches which are dependent on MPU. For eg fixed start address. Also, some of the Xen features (eg STATIC_MEMORY) will be selected by the MPU configuration. Thus, this patch introduces a choice between MMU and MPU for the type of memory management system. By default, MMU is selected. MPU is now gated by UNSUPPORTED. Updated SUPPORT.md to state that the support for MPU is experimental. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Reworded the help messages. 2. Updated Support.md. SUPPORT.md | 1 + xen/arch/arm/Kconfig | 16 +++++++++++++++- xen/arch/arm/platforms/Kconfig | 2 +- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/SUPPORT.md b/SUPPORT.md index 23dd7e6424..3f6d788a43 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -40,6 +40,7 @@ supported in this document. Status, Xen in AArch64 mode: Supported Status, Xen in AArch32 mode: Tech Preview + Status, Xen with MPU: Experimental Status, Cortex A57 r0p0-r1p1: Supported, not security supported Status, Cortex A77 r0p0-r1p0: Supported, not security supported diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 323c967361..e881f5ba57 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -58,10 +58,24 @@ config PADDR_BITS default 40 if ARM_PA_BITS_40 default 48 if ARM_64 +choice + prompt "Memory management system" + default MMU if ARM + help + User can choose between the different forms of memory management system. + config MMU - def_bool y + bool "MMU" select HAS_PMAP select HAS_VMAP + help + Select it if you plan to run Xen on A-profile Armv7+ + +config MPU + bool "MPU" if UNSUPPORTED + help + Memory protection unit is supported on some Armv8-R systems (UNSUPPORTED). +endchoice source "arch/Kconfig" diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfig index 76f7e76b1b..02322c259c 100644 --- a/xen/arch/arm/platforms/Kconfig +++ b/xen/arch/arm/platforms/Kconfig @@ -1,5 +1,5 @@ choice - prompt "Platform Support" + prompt "Platform Support" if MMU default ALL_PLAT help Choose which hardware platform to enable in Xen. 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pr=C From: Ayan Kumar Halder To: CC: Wei Chen , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , "Jiamei . Xie" , "Ayan Kumar Halder" Subject: [PATCH v2 2/4] xen/arm: mpu: Define Xen start address for MPU systems Date: Wed, 18 Sep 2024 18:51:00 +0100 Message-ID: <20240918175102.223076-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240918175102.223076-1-ayan.kumar.halder@amd.com> References: <20240918175102.223076-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|PH7PR12MB9127:EE_ X-MS-Office365-Filtering-Correlation-Id: dd77f411-24f5-4ea4-b93d-08dcd80aa454 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: 2h8Iij0Vvn9rT+dFVuVHmWrfQZe3NulGnBSfHHfbgBBr8mHrZzFg5ps67tBxTTnhCMQnDhiH0ApsFmHXyXw9htJ/zhs9aXLqFTKoW4g1av18s/jL/biB0K39CIyGRj2PWUj2/Xdfo639JtCM1uzVQLEQWOjJRfdoaTGsZnPm0KBUOhGHVySXoIHvV3fIRitTDcpURsEusEcQYSZon2jPm8/lgYzG2Dgug0C0u2HzW1pYXVlME5WR9iDNWFSbFli+1aWQW1k9334kt12a3g/kSSxQOQwLBPajfzoqYgaKFCANGhfxiqvI90b7WOGbXwSS6dzxvDXgmrtRVz3g6zrLqfYtXhhSGAcbQuZXqR5QgPFWa2Mkeq5kfrTA8TugVRujfKX6nKnLE9LuDCXjk8/mpWoA6QMKVfVVSsTCY0NHYqGkgZkswZc1n/88mTA2Xv4wfjoMBUNWVzXCRCXhEmIytSIP028l7IlI/9DuKdS6qcP9PCl5YWhpiqIYToxPFFRNGiEwf8m5jguUn8yzYZ63fUCswjGSI9Ud9vtxZGLHfiQMcFIKBfiDS9emitQ2MDW+JwGx0d3PUQlkyVdavFgV2mj3g8cyCh1ot6xy59kDg85IxnJ8r68wqBf6j847hEE8H2x9QiwF1MQpdARYB4jH+1Fbv4d5wtNhtDbqPgOhkGsyf4ZeFwH4TjrzP5ZgRhbcXyODgatlOJWHctnjp0vZb3w7CiKELHkO8aCTIqNOJDxQ/zlotcINBIFAl65DkdN9eDzRJjOwzyqpYIdEjgl9/U0PH9odsoLjAIGHOk3f0MRjmxPsT+qKYU9l6rVV9n7tbyEgu5uBebrgCJoCeDW6EdD4obXUKn1o/HQtVvUJIQkRmA0liDcOHx7fLgVAg9Yc1es0J54IQTha5sjLdNoX//9olGr9TdftGyoRrV2h0z9ydli/vy/1SkxHt/HV6vR5IKbG6T4BIDFRsoZPtNnJkSyHTVz96wN0RXbw0+QX5HLVoeqaqwEsXDo/Z7smYkNQ9QiXjF7XwOBWPXg70vHxSBb2E1K0sgGWYvqsXsQ+xCM95zw7kP/0Koewnv+rodn85AJxV+dW2lv39rVHywI7xlIpgFWYmYdPL0m4AzYXcJOlCL1dDek4PhH3vLOQk3gd+wLvyYleUPcKEoAuo49yWTbGd/9MS2D1z+DcEVLj5dQtT2bRCVHaexay/OQfzhEhimT8nXY1fzpW18pIqZ21xYQlfRX4i5MZ05NrLEyIgjROyuLhEgRLj3tAHnZP9AnjnCdPTnOH6VPwGfXjBAMElrANvZYKTfSPR1jQpt9WGCQ1jMmJ/lhbMcgjJA/guYuoE5rkghrA7treefr/jST1QUt/CuJt2U25S84MhU+DJ+2UGnwUr7EKANXc+17qAQWxQBKacjxCXFjVdo75iMuVaXbVM6mtggxSu4kixr+ZoxDFp3wZXF9RDYInxs90dcWm X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 17:52:19.7274 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd77f411-24f5-4ea4-b93d-08dcd80aa454 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9127 From: Wei Chen On Armv8-A, Xen has a fixed virtual start address (link address too) for all Armv8-A platforms. In an MMU based system, Xen can map its loaded address to this virtual start address. So, on Armv8-A platforms, the Xen start address does not need to be configurable. But on Armv8-R platforms, there is no MMU to map loaded address to a fixed virtual address and different platforms will have very different address space layout. So Xen cannot use a fixed physical address on MPU based system and need to have it configurable. So, we introduce a Kconfig option for users to set the start address. The start address needs to be aligned to 4KB. We have a check for this alignment. In case if the user forgets to set the start address, then 0xffffffff is used as default. This is to trigger the error (on alignment check) and thereby prompt user to set the start address. Also updated config.h so that it includes mpu/layout.h when CONFIG_MPU is defined. Signed-off-by: Wei Chen Signed-off-by: Jiamei.Xie Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Fixed some of the coding style issues. 2. Reworded the help message. 3. Updated the commit message. xen/arch/arm/Kconfig | 10 ++++++++++ xen/arch/arm/include/asm/config.h | 4 +++- xen/arch/arm/include/asm/mpu/layout.h | 27 +++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/include/asm/mpu/layout.h diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index e881f5ba57..ab3ef005a6 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -23,6 +23,16 @@ config ARCH_DEFCONFIG default "arch/arm/configs/arm32_defconfig" if ARM_32 default "arch/arm/configs/arm64_defconfig" if ARM_64 +config XEN_START_ADDRESS + hex "Xen start address: keep default to use platform defined address" + default 0xFFFFFFFF + depends on MPU + help + Used to set customized address at which which Xen will be linked on MPU + systems. Must be aligned to 4KB. + 0xFFFFFFFF is used as default value to indicate that user has not + customized this address. + menu "Architecture Features" choice diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/config.h index a2e22b659d..0a51142efd 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -69,8 +69,10 @@ #include #include -#ifdef CONFIG_MMU +#if defined(CONFIG_MMU) #include +#elif defined(CONFIG_MPU) +#include #else # error "Unknown memory management layout" #endif diff --git a/xen/arch/arm/include/asm/mpu/layout.h b/xen/arch/arm/include/asm/mpu/layout.h new file mode 100644 index 0000000000..f9a5be2d6b --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/layout.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MPU_LAYOUT_H__ +#define __ARM_MPU_LAYOUT_H__ + +#define XEN_START_ADDRESS CONFIG_XEN_START_ADDRESS + +/* + * All MPU platforms need to provide a XEN_START_ADDRESS for linker. This + * address indicates where Xen image will be loaded and run from. This + * address must be aligned to a PAGE_SIZE. + */ +#if (XEN_START_ADDRESS % PAGE_SIZE) != 0 +#error "XEN_START_ADDRESS must be aligned to PAGE_SIZE" +#endif + +#define XEN_VIRT_START _AT(paddr_t, XEN_START_ADDRESS) + +#endif /* __ARM_MPU_LAYOUT_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Wed Sep 18 17:51:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13807064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 918CBCDD550 for ; Wed, 18 Sep 2024 17:53:21 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.800388.1210318 (Exim 4.92) (envelope-from ) id 1sqyrQ-0000zn-AV; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 17:52:56.7094 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6687e436-7708-4dc7-4175-08dcd80aba69 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7525 Define enable_boot_cpu_mm() for the AArch64-V8R system. Like boot-time page table in MMU system, we need a boot-time MPU protection region configuration in MPU system so Xen can fetch code and data from normal memory. To do this, Xen maps the following sections of the binary as separate regions (with permissions) :- 1. Text (Read only at EL2, execution is permitted) 2. RO data (Read only at EL2) 3. RO after init data (Read/Write at EL2 as the data is RW during init) 4. RW data (Read/Write at EL2) 5. BSS (Read/Write at EL2) 6. Init Text (Read only at EL2, execution is permitted) 7. Init data (Read/Write at EL2) If the number of MPU regions created is greater than the count defined in MPUIR_EL2, then the boot fails. One can refer to ARM DDI 0600B.a ID062922 G1.3 "General System Control Registers", to get the definitions of PRBAR_EL2, PRLAR_EL2 and PRSELR_EL2 registers. Also, refer to G1.2 "Accessing MPU memory region registers", the following ``` The MPU provides two register interfaces to program the MPU regions: - Access to any of the MPU regions via PRSELR_ELx, PRBAR_ELx, and PRLAR_ELx. ``` We use the above mechanism to configure the MPU memory regions. MPU specific registers are defined in xen/arch/arm/include/asm/arm64/mpu/sysregs.h. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. Instead of mapping a (XEN_START_ADDRESS + 2MB) as a single MPU region, we have separate MPU regions for different parts of the Xen binary. The reason being different regions will nned different permissions (as mentioned in the linker script). 2. Introduced a label (__init_data_begin) to mark the beginning of the init data section. 3. Moved MPU specific register definitions to mpu/sysregs.h. 4. Fixed coding style issues. 5. Included page.h in mpu/head.S as page.h includes sysregs.h. I haven't seen sysregs.h included directly from head.S or mmu/head.S. (Outstanding comment not addressed). xen/arch/arm/Makefile | 1 + xen/arch/arm/arm64/mpu/Makefile | 1 + xen/arch/arm/arm64/mpu/head.S | 176 +++++++++++++++++++ xen/arch/arm/include/asm/arm64/mpu/sysregs.h | 27 +++ xen/arch/arm/include/asm/arm64/sysregs.h | 3 + xen/arch/arm/include/asm/mm.h | 2 + xen/arch/arm/include/asm/mpu/arm64/mm.h | 22 +++ xen/arch/arm/include/asm/mpu/mm.h | 20 +++ xen/arch/arm/xen.lds.S | 1 + 9 files changed, 253 insertions(+) create mode 100644 xen/arch/arm/arm64/mpu/Makefile create mode 100644 xen/arch/arm/arm64/mpu/head.S create mode 100644 xen/arch/arm/include/asm/arm64/mpu/sysregs.h create mode 100644 xen/arch/arm/include/asm/mpu/arm64/mm.h create mode 100644 xen/arch/arm/include/asm/mpu/mm.h diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 7792bff597..aebccec63a 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_ARM_32) += arm32/ obj-$(CONFIG_ARM_64) += arm64/ obj-$(CONFIG_MMU) += mmu/ +obj-$(CONFIG_MPU) += mpu/ obj-$(CONFIG_ACPI) += acpi/ obj-$(CONFIG_HAS_PCI) += pci/ ifneq ($(CONFIG_NO_PLAT),y) diff --git a/xen/arch/arm/arm64/mpu/Makefile b/xen/arch/arm/arm64/mpu/Makefile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm64/mpu/Makefile @@ -0,0 +1 @@ +obj-y += head.o diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S new file mode 100644 index 0000000000..ef55c8765c --- /dev/null +++ b/xen/arch/arm/arm64/mpu/head.S @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include + +#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ +#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ + +/* + * Macro to round up the section address to be PAGE_SIZE aligned + * Each section(e.g. .text, .data, etc) in xen.lds.S is page-aligned, + * which is usually guarded with ". = ALIGN(PAGE_SIZE)" in the head, + * or in the end + */ +.macro roundup_section, xb + add \xb, \xb, #(PAGE_SIZE-1) + and \xb, \xb, #PAGE_MASK +.endm + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * Inputs: + * sel: region selector + * base: reg storing base address (should be page-aligned) + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + * + * Clobber \tmp1, \tmp2 + * + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, tmp1, tmp2, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Prepare value for PRLAR_EL2 reg and preserve it in \prlar.*/ + /* Round up limit address to be PAGE_SIZE aligned */ + roundup_section \limit + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + msr PRSELR_EL2, \sel + isb + msr PRBAR_EL2, \prbar + msr PRLAR_EL2, \prlar + dsb + isb +.endm + +/* Load the physical address of a symbol into xb */ +.macro load_paddr xb, sym + ldr \xb, =\sym + add \xb, \xb, x20 /* x20 - Phys offset */ +.endm + +.section .text.header, "ax", %progbits + +/* + * Enable EL2 MPU and data cache + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch64 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers x0 + * + */ +FUNC_LOCAL(enable_mpu) + mrs x0, SCTLR_EL2 + orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + orr x0, x0, #SCTLR_Axx_ELx_WXN /* Enable WXN */ + dsb sy + msr SCTLR_EL2, x0 + isb + + ret +END(enable_mpu) + +/* + * Maps the various sections of Xen (described in xen.lds.S) as different MPU + * regions. Some of these regions will be marked read only while the others will + * be read write or execute. + * + * Inputs: + * lr : Address to return to. + * + * Clobbers x0 - x7 + * + */ +FUNC(enable_boot_cpu_mm) + mov x7, lr + + /* x0: region sel */ + mov x0, xzr + /* Xen text section. */ + load_paddr x1, _stext + load_paddr x2, _etext + prepare_xen_region x0, x1, x2, x3, x4, x5, x6, attr_prbar=REGION_TEXT_PRBAR + + add x0, x0, #1 + /* Xen read-only data section. */ + load_paddr x1, _srodata + load_paddr x2, _erodata + prepare_xen_region x0, x1, x2, x3, x4, x5, x6, attr_prbar=REGION_RO_PRBAR + + add x0, x0, #1 + /* Xen read-only after init data section. */ + load_paddr x1, __ro_after_init_start + load_paddr x2, __ro_after_init_end + prepare_xen_region x0, x1, x2, x3, x4, x5, x6 + + add x0, x0, #1 + /* Xen read-write data section. */ + load_paddr x1, __ro_after_init_end + load_paddr x2, __init_begin + prepare_xen_region x0, x1, x2, x3, x4, x5, x6 + + add x0, x0, #1 + /* Xen BSS section. */ + load_paddr x1, __bss_start + load_paddr x2, __bss_end + prepare_xen_region x0, x1, x2, x3, x4, x5, x6 + + add x0, x0, #1 + /* Xen init text section. */ + load_paddr x1, __init_begin + load_paddr x2, __init_data_begin + prepare_xen_region x0, x1, x2, x3, x4, x5, x6, attr_prbar=REGION_TEXT_PRBAR + + add x0, x0, #1 + /* Xen init data section. */ + load_paddr x1, __init_data_begin + load_paddr x2, __init_end + prepare_xen_region x0, x1, x2, x3, x4, x5, x6 + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + mrs x1, MPUIR_EL2 + cmp x0, x1 + bgt 1f + bl enable_mpu + + mov lr, x7 + ret + +1: + PRINT("- Number of MPU regions set in MPUIR_EL2 is too less -\r\n") + wfe + b 1b +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm64/mpu/sysregs.h b/xen/arch/arm/include/asm/arm64/mpu/sysregs.h new file mode 100644 index 0000000000..b0c31a58ec --- /dev/null +++ b/xen/arch/arm/include/asm/arm64/mpu/sysregs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_ARM_ARM64_MPU_SYSREGS_H +#define __ASM_ARM_ARM64_MPU_SYSREGS_H + +/* Number of EL2 MPU regions */ +#define MPUIR_EL2 S3_4_C0_C0_4 + +/* EL2 MPU Protection Region Base Address Register encode */ +#define PRBAR_EL2 S3_4_C6_C8_0 + +/* EL2 MPU Protection Region Limit Address Register encode */ +#define PRLAR_EL2 S3_4_C6_C8_1 + +/* MPU Protection Region Selection Register encode */ +#define PRSELR_EL2 S3_4_C6_C2_1 + +#endif /* __ASM_ARM_ARM64_MPU_SYSREGS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index b593e4028b..8b6b373ce9 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -2,6 +2,9 @@ #define __ASM_ARM_ARM64_SYSREGS_H #include +#if defined(CONFIG_MPU) +#include +#endif /* * GIC System register assembly aliases picked from kernel diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 5abd4b0d1c..7e61f37612 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -16,6 +16,8 @@ #if defined(CONFIG_MMU) # include +#elif defined(CONFIG_MPU) +# include #else # error "Unknown memory management layout" #endif diff --git a/xen/arch/arm/include/asm/mpu/arm64/mm.h b/xen/arch/arm/include/asm/mpu/arm64/mm.h new file mode 100644 index 0000000000..c2640b50df --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/arm64/mm.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * mm.h: Arm Memory Protection Unit definitions. + */ + +#ifndef __ARM64_MPU_MM_H__ +#define __ARM64_MPU_MM_H__ + +#define MPU_REGION_SHIFT 6 +#define MPU_REGION_ALIGN (_AC(1, UL) << MPU_REGION_SHIFT) +#define MPU_REGION_MASK (~(MPU_REGION_ALIGN - 1)) + +#endif /* __ARM64_MPU_MM_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h new file mode 100644 index 0000000000..92599a1d75 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/mm.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MPU_MM__ +#define __ARM_MPU_MM__ + +#if defined(CONFIG_ARM_64) +# include +#else +# error "unknown ARM variant" +#endif + +#endif /* __ARM_MPU_MM__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S index bd884664ad..0b8956ac3c 100644 --- a/xen/arch/arm/xen.lds.S +++ b/xen/arch/arm/xen.lds.S @@ -157,6 +157,7 @@ SECTIONS *(.altinstr_replacement) } :text . = ALIGN(PAGE_SIZE); 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini , "Bertrand Marquis" , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v2 4/4] xen/arm: mpu: Implement a dummy enable_secondary_cpu_mm Date: Wed, 18 Sep 2024 18:51:02 +0100 Message-ID: <20240918175102.223076-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240918175102.223076-1-ayan.kumar.halder@amd.com> References: <20240918175102.223076-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE4:EE_|LV2PR12MB5846:EE_ X-MS-Office365-Filtering-Correlation-Id: d9983e89-6efe-45c3-1737-08dcd80abea3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: +vwDf1+RV2vA+lyD7QmsTXsF2uDGYiS5fmB6MvbcPeLHPkGujCixq08oRH5pkJ8IiKX57ClddHUt1dfoUm6Q7L1+ofuYTZE4Me6XKReOVJb7FcGUUb/Mv4dUFuJztJOYa/cNf+C4WcF2MmMaLYaFA3HWR0P9YOmmrkoyKfCz4a42/s2xR2rZKq7J+0Veig/QAdbP51R0MA2dDFYbnYGudGg08BYLmsmChh3vrOq1XR0BfivhGr9tn8B/3LjEcq9qlTCl1z21HKigOWUN1Hnx55X3uH4Mwv9zfxErJ1QQ02Gy9xgUh665ek/OtMOJ8Z9OE3gnQJYBEERKDO4mZdi22H/DnmS+KgA2QprYygkXqpjIK598gHjDmvGpojX1M5PtEf9ZEPz98rqlmCuKdjAFqUoGZaZ4cNCxP6F/zkiF/JZ4q+0qFC4Ctrl2datAJxxgNVjc9ZdmkvL2CRBMyLuS73fnuGl+/Yo5rxyFglNiPTBaq3FrBexYMSs4lKigNbCFGpDTNoLYXL4N2TUcmuoMqa8IoeJ6pEoxvKNRPOMVL2zLtLUp1F9hGRP8BOZTLWaEYNiuvJA9AqTLUT7vAIbynZWUoezFpxg8REMh2AlRX/YwBGQcKEGy5JO7bZKboQWyZyjpKJ3ELoiuVnMa4DqDAOe5tAIe3WjosG+0fPjMlUGvWd1jd0EkpaX3PBnjvrVYp5EMbDZxey8GerDntpK8FJItB38qgHiUUfWz6ks92oQyEA+ksZQWxLAaOneAx+PLN0FwUobX19GBUI07u7O/xNpzio8/Fjyj+NV+YwcFo8cJ+TMSI5rMgDbxEB3sHmD5lMwjKp2v+fe02fw6hojsZ+gCdkSpnAurewIP0xW+sGktX/Z+1k47tcaH6zM3HMP5q/nOeIflhJ1nxNyw3S1dLWiwkc1bAu0ndHzlJ8/RUhkoq/uom85rToNRJDoJlzmJgStTZdbVXqAsE4Fa8i489yLtq/qVGenQhRA4qkZUhry4J1lhE1WIE97eBUTTjBvD4lwqckecCYQRjZMtYKDgEkSGMsMr1iEfQt6kBmdN8Uz3yXcnaAMKIkF9MUbtzXYsCN7Hslcy0D2fWrCBBiBCKlgWYSuj2oYeF5EWFt4Fn9xNwaO5rQf/8S7gbXI/d+oVhCo/RygrW3sZ/U2flIywPrrmM7iFd+hpMIT38jkVjoUyOEkJQZmRtYZ5SSzUeevo5xshGac37if/9U23HN9IUzQl8WKXYjtaN3nk3e7S/cefHXS/qcp/krMBXpOscna6bcMQwAf/XfH4XgiNykaApvm7c2TfhElyLIy3WW6y5PSw1T2e97H1VZ86oRE9c0E35UgLRedjc3+CpyZglwJb/04E5Qu11rsdhO0KtDMJzCacindNCESRyjmPZalWlbcbZ0eMAIevO17EiXJaNo18u+2T4Txzb+RewXazfwFe5MpV11o4rtnqcliDk1spNEAL X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 17:53:03.7993 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9983e89-6efe-45c3-1737-08dcd80abea3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5846 Secondary cpus initialization is not yet supported. Thus, we print an appropriate message and put the secondary cpus in WFE state. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1 - 1. NR_CPUS is defined as 1 for MPU 2. Added a message in enable_secondary_cpu_mm() xen/arch/Kconfig | 1 + xen/arch/arm/arm64/mpu/head.S | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 308ce129a8..8640b7ec8b 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -11,6 +11,7 @@ config NR_CPUS default "8" if ARM && RCAR3 default "4" if ARM && QEMU default "4" if ARM && MPSOC + default "1" if ARM && MPU default "128" if ARM help Controls the build-time size of various arrays and bitmaps diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index ef55c8765c..3dfbbf8879 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -168,6 +168,16 @@ FUNC(enable_boot_cpu_mm) b 1b END(enable_boot_cpu_mm) +/* + * Secondary cpu has not yet been supported on MPU systems. We will block the + * secondary cpu bringup at this stage. + */ +ENTRY(enable_secondary_cpu_mm) +1: PRINT("- SMP not enabled yet -\r\n") + wfe + b 1b +ENDPROC(enable_secondary_cpu_mm) + /* * Local variables: * mode: ASM