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Wed, 18 Sep 2024 14:59:54 -0700 From: Besar Wicaksono To: , , , , CC: , , , , , , , , "Besar Wicaksono" Subject: [PATCH 1/3] perf: arm_cspmu: nvidia: remove unsupported SCF events Date: Wed, 18 Sep 2024 21:58:44 +0000 Message-ID: <20240918215846.1424282-2-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240918215846.1424282-1-bwicaksono@nvidia.com> References: <20240918215846.1424282-1-bwicaksono@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|CY8PR12MB7491:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b24cc76-4e7d-4b35-a1be-08dcd82d4178 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 9D4y8FoQMzU1zcDWJxFm513J5e4P2txySD9R6QFSCoHi9G1XFS+g49tKgLBd/IJ0gqS/TMMcWVx6bx4fpSuRg+6CDapmmSVpKqug6vXfX2PGdv/TovcXciHNVguVhq7ZbBu/3g5EA4hAqAvrs0m6P+IMJCTeqcxSM3zWrGw3E6oqWxEJWYgujAVXLJ3LK+m9rIdlQtXlRGGavaR5Jq1f6G508rowwxq9OCBI7UP1CrjlO7WWVFI17lYjrzFNLbyhMBEMpJx2nKG9cUGt8S82ia7h6F5l+LxWzy5Wl361ueR63ta90D4Km7zBWDuepA8SrBz+QblqRa5EhI/VVH07VHrhredtfHm+2mp4PSVBJWrP3SbHEEABaJ9xvuoZHtTx8zdOpoDSinOqwppSxmYiNcDV4LruXgW+I9dbCvyzESlKRktiWo0EPnQMNf5lUiFehVYPAJzChnCMWV2qCMCV0BXHn6IXoyjLPMYuxtfsUNENftJ9G91ihUrWaOw7wiWAgQCTIqGfJ6CqJ4fgb5k4g8gQHETo+KUF9lgjS8IoE89KCjiGpNCr3g4r1QTAFSmHd5vjcnOMkExfWxXHgcPcuCL9CdJYDRK7GDfL5ryQ7L11xGwIk+8KjQrZdvKQoRGIUogDGH/tqNCB+2wdutlbGjxfmZkvFyCMdnmrR+yN09dlaedAD0x99r2hNM4ZpOy2QnmMRvH3NEHRESrd+el1uyrRHI6OHXrq0B36LfuctF8EgqQmTo59w73X+q+zHjBRMtJJ/BVbcJaLvhPCZLDbLicPRVfWm2UEhEdNxxwPBZtdbgMmpLZUXdZ5PNIg1rshW0pHwELHjT2BTodobvXFWVFZ7oqRrDVmWqvRN2ylTpZ9HWtuwFOQCBi2fk6XM5WKtcPwWSdiS9QMV9YDKrLjeNGC8+P3lBC0/lBFqagcqhREGqcgZITGafIQXCxRJnzkBf88VHF3u+mBgdqMTHQr6U3vNC7ncYgePC1Ey+JdDqkUei1PXM7aFwUHtl2uenrEX93yauJfzyETewgmenVtOEFR7E/I4VfN2jFHgvgU0KAbTd/TLUWjgltwwLzX7MPcUDpyxFTDi+M4xoUe60HkwJyXY1f4Jgkdb25kdjGmUmLska/YD+UOINGL9mOv5UCyMhhzCWI/1tCaA+K3ET8V8wou6G7gpDAsHLGNgBmjgVWEhp0co6Tc/fUExF7ijMq51uxvPX1zwia0/XBXh0ci0SVvi7MhJ182Y7Q1g7VfJ/2mtwZ2w4cyBK4m1SmS0lPImD3B8H5gvu8RIxjTv8lmasqIV+ADwicaRg33ha5ODroNaLXO8mwOicgFYOSz4Ho+RCxtxk5G91RdpgWlKLe59fExBFvZvp6RBtlFXWiIxT3QN3cyNFGbLiSOy8aWCkWB X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Remove unsupported events under SCF PMU. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/nvidia_cspmu.c | 64 --------------------------- 1 file changed, 64 deletions(-) diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu/nvidia_cspmu.c index d0ef611240aa..ea2d44adfa7c 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -54,65 +54,24 @@ static struct attribute *scf_pmu_event_attrs[] = { ARM_CSPMU_EVENT_ATTR(scf_cache_wb, 0xF3), NV_CSPMU_EVENT_ATTR_4(socket, rd_data, 0x101), - NV_CSPMU_EVENT_ATTR_4(socket, dl_rsp, 0x105), NV_CSPMU_EVENT_ATTR_4(socket, wb_data, 0x109), - NV_CSPMU_EVENT_ATTR_4(socket, ev_rsp, 0x10d), - NV_CSPMU_EVENT_ATTR_4(socket, prb_data, 0x111), NV_CSPMU_EVENT_ATTR_4(socket, rd_outstanding, 0x115), - NV_CSPMU_EVENT_ATTR_4(socket, dl_outstanding, 0x119), - NV_CSPMU_EVENT_ATTR_4(socket, wb_outstanding, 0x11d), - NV_CSPMU_EVENT_ATTR_4(socket, wr_outstanding, 0x121), - NV_CSPMU_EVENT_ATTR_4(socket, ev_outstanding, 0x125), - NV_CSPMU_EVENT_ATTR_4(socket, prb_outstanding, 0x129), NV_CSPMU_EVENT_ATTR_4(socket, rd_access, 0x12d), - NV_CSPMU_EVENT_ATTR_4(socket, dl_access, 0x131), NV_CSPMU_EVENT_ATTR_4(socket, wb_access, 0x135), NV_CSPMU_EVENT_ATTR_4(socket, wr_access, 0x139), - NV_CSPMU_EVENT_ATTR_4(socket, ev_access, 0x13d), - NV_CSPMU_EVENT_ATTR_4(socket, prb_access, 0x141), - - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_rd_data, 0x145), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_rd_access, 0x149), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wb_access, 0x14d), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_rd_outstanding, 0x151), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wr_outstanding, 0x155), - - NV_CSPMU_EVENT_ATTR_4(ocu, rem_rd_data, 0x159), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_rd_access, 0x15d), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wb_access, 0x161), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_rd_outstanding, 0x165), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wr_outstanding, 0x169), ARM_CSPMU_EVENT_ATTR(gmem_rd_data, 0x16d), ARM_CSPMU_EVENT_ATTR(gmem_rd_access, 0x16e), ARM_CSPMU_EVENT_ATTR(gmem_rd_outstanding, 0x16f), - ARM_CSPMU_EVENT_ATTR(gmem_dl_rsp, 0x170), - ARM_CSPMU_EVENT_ATTR(gmem_dl_access, 0x171), - ARM_CSPMU_EVENT_ATTR(gmem_dl_outstanding, 0x172), ARM_CSPMU_EVENT_ATTR(gmem_wb_data, 0x173), ARM_CSPMU_EVENT_ATTR(gmem_wb_access, 0x174), - ARM_CSPMU_EVENT_ATTR(gmem_wb_outstanding, 0x175), - ARM_CSPMU_EVENT_ATTR(gmem_ev_rsp, 0x176), - ARM_CSPMU_EVENT_ATTR(gmem_ev_access, 0x177), - ARM_CSPMU_EVENT_ATTR(gmem_ev_outstanding, 0x178), ARM_CSPMU_EVENT_ATTR(gmem_wr_data, 0x179), - ARM_CSPMU_EVENT_ATTR(gmem_wr_outstanding, 0x17a), ARM_CSPMU_EVENT_ATTR(gmem_wr_access, 0x17b), NV_CSPMU_EVENT_ATTR_4(socket, wr_data, 0x17c), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wr_data, 0x180), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wb_data, 0x184), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wr_access, 0x188), - NV_CSPMU_EVENT_ATTR_4(ocu, gmem_wb_outstanding, 0x18c), - - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wr_data, 0x190), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wb_data, 0x194), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wr_access, 0x198), - NV_CSPMU_EVENT_ATTR_4(ocu, rem_wb_outstanding, 0x19c), - ARM_CSPMU_EVENT_ATTR(gmem_wr_total_bytes, 0x1a0), ARM_CSPMU_EVENT_ATTR(remote_socket_wr_total_bytes, 0x1a1), ARM_CSPMU_EVENT_ATTR(remote_socket_rd_data, 0x1a2), @@ -122,35 +81,12 @@ static struct attribute *scf_pmu_event_attrs[] = { ARM_CSPMU_EVENT_ATTR(cmem_rd_data, 0x1a5), ARM_CSPMU_EVENT_ATTR(cmem_rd_access, 0x1a6), ARM_CSPMU_EVENT_ATTR(cmem_rd_outstanding, 0x1a7), - ARM_CSPMU_EVENT_ATTR(cmem_dl_rsp, 0x1a8), - ARM_CSPMU_EVENT_ATTR(cmem_dl_access, 0x1a9), - ARM_CSPMU_EVENT_ATTR(cmem_dl_outstanding, 0x1aa), ARM_CSPMU_EVENT_ATTR(cmem_wb_data, 0x1ab), ARM_CSPMU_EVENT_ATTR(cmem_wb_access, 0x1ac), - ARM_CSPMU_EVENT_ATTR(cmem_wb_outstanding, 0x1ad), - ARM_CSPMU_EVENT_ATTR(cmem_ev_rsp, 0x1ae), - ARM_CSPMU_EVENT_ATTR(cmem_ev_access, 0x1af), - ARM_CSPMU_EVENT_ATTR(cmem_ev_outstanding, 0x1b0), ARM_CSPMU_EVENT_ATTR(cmem_wr_data, 0x1b1), - ARM_CSPMU_EVENT_ATTR(cmem_wr_outstanding, 0x1b2), - - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_rd_data, 0x1b3), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_rd_access, 0x1b7), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wb_access, 0x1bb), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_rd_outstanding, 0x1bf), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wr_outstanding, 0x1c3), - - ARM_CSPMU_EVENT_ATTR(ocu_prb_access, 0x1c7), - ARM_CSPMU_EVENT_ATTR(ocu_prb_data, 0x1c8), - ARM_CSPMU_EVENT_ATTR(ocu_prb_outstanding, 0x1c9), ARM_CSPMU_EVENT_ATTR(cmem_wr_access, 0x1ca), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wr_access, 0x1cb), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wb_data, 0x1cf), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wr_data, 0x1d3), - NV_CSPMU_EVENT_ATTR_4(ocu, cmem_wb_outstanding, 0x1d7), - ARM_CSPMU_EVENT_ATTR(cmem_wr_total_bytes, 0x1db), ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT), From patchwork Wed Sep 18 21:58:45 2024 Content-Type: text/plain; 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Wed, 18 Sep 2024 14:59:58 -0700 From: Besar Wicaksono To: , , , , CC: , , , , , , , , "Besar Wicaksono" Subject: [PATCH 2/3] perf: arm_cspmu: nvidia: update CNVLINK PMU events Date: Wed, 18 Sep 2024 21:58:45 +0000 Message-ID: <20240918215846.1424282-3-bwicaksono@nvidia.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240918215846.1424282-1-bwicaksono@nvidia.com> References: <20240918215846.1424282-1-bwicaksono@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A1:EE_|CYXPR12MB9425:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ca640ca-c2e9-44c2-9da3-08dcd82d44de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: ZImBW+U2My4fOkcmzfnvxwvd5UfpIVUkn+eOlHx6QhGzewDJ9ce8xYIhONGeNq/tLeUpemYenvafyhYdLqY0J/iTI/zjh5RGoWp1rOyCyXAs0x+uJ9G4fvJZzHGLa25bz61B8IL9sVjI/8c+QL/jFW8A9PhHl0ZWAY4dnicsLFh5pzx6rbfLBeJojJqWU0c71K1JCv0lvilBaIZTv6BrlbEUuWaSXIufptmLX2SNqPVCY0LU1ICODMQ/Kbnew1OE+mvxk+sIFx6jtaoFycMWhef64YJlBKGV+8cB1QygpzcUF6QcpUOOsprjhezfSjpNnod122KWoeI5XTfyCz1M3r9E82hEV5gwfO6YMTNMvofXZH+lBzhIT2cM4DxZ8hy8VqmwFhpiL+F6CwyfMeBqxpAVOgJP4hKBhN7vPydwei2aesDaQzO6BksO/5neLjpWKt1F80kLa4JIgmAIGg8AZ9MzqBsSe1j6CqylAdc8svSsb/1humzOdqmROB60kX+FjUIMQMV3CoQBAO5qwsA9Z7gSDxaBqT+v9Qe+/IffIcfO8ovBvFGUnGWGORlH5cDRs29+LXf9mypQDhGUVYULNVGouYBVCwtzE/sBmb4wUP7VQSlG+EJarlAyNiMpewQUYd2ALgU1rJ9ZKEkSgUpg3+2mwwMPBQq29Ly+YrlZiymWFCvK3riEh+p8hYhES7v+aPc0GNZjiy4FTGKOwMzmz5LRAIpe+7aMV2sqbNlee5pftUQ8xUcBV3+6EpXxqKKksjmBf0J7YUcsQd6dqfNPZ72t0iQA1Xhg2xEynFeaaHXYSLOVfzKG5p7Th16Jv417kgoRg1ElKPZ1FTN0xVjLvnquJqWRxJCbMrHIxWz5l4EX72+iGbkSPzpxl1dqlhfyvoBkw9ejnq7mfhmhV6N+HQuYnnTkwRkxwAnZJ+XLdSXgxMjV574TFofBipCSMyonGGE9y0Yip3EDG94f+J6T6E/ST5MbuY+fq1AQXCGh9AGIlsiQyUarxqsDUr/uSfRDRwRzUmYSKWjXW2iUjObb8ZpUCObVJqh09H1ISlhleEW5VlCnzQiJ4oKdw8n/BXnvnAT31hrBTdHP85+UjLJQziKC/PsF9TMXl6VnBOF9c/92zBHvJmybsofEtuwKFG5erIY+tjZPOiUNOvoAmIvocdTfZz/ITl6MuO33U86Af9Jc1T/a8jkw/ylFGUC/d4g2NYrnB08VFP7AR+N4YuqLoFaBIbe2gk9fmyEmb8JKtWMQzMAdaBVSd3kp57YAT6binAZexwQOD6W+pmeMre5+ZOsrIvtwP3E/tixS7w+LHEH223R2LXh7vnNfDrISzKPvcOW69PHY6fnmZ6fGystBI1hhIobcOag/kDrqz4inq9DLbitrkjYaCEgZAHztvOZGrAAtZn72oiTxmCS3jl6rA2hC05WsFFMcexUvSfKMuAM6SrGFlD75A5YSi1D+09q8 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 22:00:11.8304 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3ca640ca-c2e9-44c2-9da3-08dcd82d44de X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9425 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240918_150019_175610_C4384551 X-CRM114-Status: GOOD ( 10.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Rename loc* and rem* events in CNVLINK PMU to cmem* and gmem* events. Signed-off-by: Besar Wicaksono --- drivers/perf/arm_cspmu/nvidia_cspmu.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu/nvidia_cspmu.c index ea2d44adfa7c..d1cd9975e71a 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -112,6 +112,25 @@ static struct attribute *mcf_pmu_event_attrs[] = { NULL, }; +static struct attribute *mcf_cnvlink_pmu_event_attrs[] = { + ARM_CSPMU_EVENT_ATTR(rd_bytes_cmem, 0x0), + ARM_CSPMU_EVENT_ATTR(rd_bytes_gmem, 0x1), + ARM_CSPMU_EVENT_ATTR(wr_bytes_cmem, 0x2), + ARM_CSPMU_EVENT_ATTR(wr_bytes_gmem, 0x3), + ARM_CSPMU_EVENT_ATTR(total_bytes_cmem, 0x4), + ARM_CSPMU_EVENT_ATTR(total_bytes_gmem, 0x5), + ARM_CSPMU_EVENT_ATTR(rd_req_cmem, 0x6), + ARM_CSPMU_EVENT_ATTR(rd_req_gmem, 0x7), + ARM_CSPMU_EVENT_ATTR(wr_req_cmem, 0x8), + ARM_CSPMU_EVENT_ATTR(wr_req_gmem, 0x9), + ARM_CSPMU_EVENT_ATTR(total_req_cmem, 0xa), + ARM_CSPMU_EVENT_ATTR(total_req_gmem, 0xb), + ARM_CSPMU_EVENT_ATTR(rd_cum_outs_cmem, 0xc), + ARM_CSPMU_EVENT_ATTR(rd_cum_outs_gmem, 0xd), + ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT), + NULL, +}; + static struct attribute *generic_pmu_event_attrs[] = { ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT), NULL, @@ -234,7 +253,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] = { .filter_default_val = NV_CNVL_FILTER_ID_MASK, .name_pattern = "nvidia_cnvlink_pmu_%u", .name_fmt = NAME_FMT_SOCKET, - .event_attr = mcf_pmu_event_attrs, + .event_attr = mcf_cnvlink_pmu_event_attrs, .format_attr = cnvlink_pmu_format_attrs }, { From patchwork Wed Sep 18 21:58:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Besar Wicaksono X-Patchwork-Id: 13807234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C69CCDD55D for ; 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Signed-off-by: Besar Wicaksono --- Documentation/admin-guide/perf/nvidia-pmu.rst | 32 +++++++++++++++++++ drivers/perf/arm_cspmu/nvidia_cspmu.c | 7 ++-- 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/Documentation/admin-guide/perf/nvidia-pmu.rst b/Documentation/admin-guide/perf/nvidia-pmu.rst index 2e0d47cfe7ea..6d1d3206b4ad 100644 --- a/Documentation/admin-guide/perf/nvidia-pmu.rst +++ b/Documentation/admin-guide/perf/nvidia-pmu.rst @@ -86,6 +86,22 @@ Example usage: perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/ +The NVLink-C2C has two ports that can be connected to one GPU (occupying both +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port number, +e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The +PMU will monitor both ports by default if not specified. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1:: + + perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/ + NVLink-C2C1 PMU ------------------- @@ -116,6 +132,22 @@ Example usage: perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/ +The NVLink-C2C has two ports that can be connected to one GPU (occupying both +ports) or to two GPUs (one GPU per port). The user can use "port" bitmap +parameter to select the port(s) to monitor. Each bit represents the port number, +e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The +PMU will monitor both ports by default if not specified. + +Example for port filtering: + +* Count event id 0x0 from the GPU connected with socket 0 on port 0:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/ + +* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1:: + + perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/ + CNVLink PMU --------------- diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu/nvidia_cspmu.c index d1cd9975e71a..cd51177347e5 100644 --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c @@ -149,6 +149,7 @@ static struct attribute *pcie_pmu_format_attrs[] = { static struct attribute *nvlink_c2c_pmu_format_attrs[] = { ARM_CSPMU_FORMAT_EVENT_ATTR, + ARM_CSPMU_FORMAT_ATTR(port, "config1:0-1"), NULL, }; @@ -193,7 +194,7 @@ static u32 nv_cspmu_event_filter(const struct perf_event *event) const struct nv_cspmu_ctx *ctx = to_nv_cspmu_ctx(to_arm_cspmu(event->pmu)); - if (ctx->filter_mask == 0) + if (ctx->filter_mask == 0 || event->attr.config1 == 0) return ctx->filter_default_val; return event->attr.config1 & ctx->filter_mask; @@ -229,7 +230,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] = { { .prodid = 0x104, .prodid_mask = NV_PRODID_MASK, - .filter_mask = 0x0, + .filter_mask = NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK, .name_pattern = "nvidia_nvlink_c2c1_pmu_%u", .name_fmt = NAME_FMT_SOCKET, @@ -239,7 +240,7 @@ static const struct nv_cspmu_match nv_cspmu_match[] = { { .prodid = 0x105, .prodid_mask = NV_PRODID_MASK, - .filter_mask = 0x0, + .filter_mask = NV_NVL_C2C_FILTER_ID_MASK, .filter_default_val = NV_NVL_C2C_FILTER_ID_MASK, .name_pattern = "nvidia_nvlink_c2c0_pmu_%u", .name_fmt = NAME_FMT_SOCKET,