From patchwork Thu Sep 19 09:09:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13807538 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB6B5CE8D62 for ; Thu, 19 Sep 2024 09:11:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ry5vKpJjRJgs56F8ircdRvQtPhhedYLh7XmItKi3+nM=; b=npttD9Y7LSRSE1 4nHGCorkdgSQy1tosQvNon0R8CVM/3h74nCBqSQiHt7aoN7JD9X2Th055hpQByq5myxEGEXldMkMy oE0q+IXjdpM/hjoa4oQZJ69hNdkD7F0XSNpHvhgGuR8Q/N5+qCHJbHacOCeIe7pBLkHBBwQRdtxSs sN7rw9bJM9Dgj/V6q6VNrOHf0btPs1y/miEzvzyyO8oE8A/2/8XlGM1XvsJhnd9VIh80R8Wxj7Lix L9ZUXtoi19AXldhpK4WNEP2/AJ50GxPDVgOnUJ2yAfon3MO7OCY7+2kOzB46NSWUKDMIMZbNG5B9u Ckeon2VovWcDJ8jl8x3A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1srDCc-00000009sZP-1i0U; Thu, 19 Sep 2024 09:11:54 +0000 Received: from bali.collaboradmins.com ([148.251.105.195]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1srDCX-00000009sWj-1b5H for linux-rockchip@lists.infradead.org; Thu, 19 Sep 2024 09:11:51 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1726737107; bh=rITSry2xLNISMJCkk+Pk0SePa7cy3UVe1V/XbJQtXgg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kdnz/tjQ5byJTA+DvSctoa3Vz01fgPgCX0G8MqA7HRCbTzRo4NWpA8IxF4X+CJMU1 JnEmsoH4G9XzXgQCTljjekl5c8cLuL2vzpCTHtXqguySVQX1X1Og//OwHN0gGCggNg eMxMongx/Lki+CnfS3WxL5CpT0FbGVfenk8V3SxrILzWmKcGNYGrqhwO2KmPQR7b9R 0QmYvidbVmAUJSpLaaF6WsLdLXmRFiD0zqr84vcAxOiqDh4WxWT3XIYbxZWXImLQiP bCnDRxAU4aYOgXV6wD4NcjHYZWc4a+/CxeBZeagGGaQD/S7UowchzbLpGr9WHwwHmC ifucprR8DMb4w== Received: from jupiter.universe (dyndsl-091-248-208-160.ewe-ip-backbone.de [91.248.208.160]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 6BC3D17E1067; Thu, 19 Sep 2024 11:11:47 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 20FB6480083; Thu, 19 Sep 2024 11:11:47 +0200 (CEST) From: Sebastian Reichel To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Cc: Elaine Zhang , Kever Yang , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , huangtao@rock-chips.com, andy.yan@rock-chips.com, Michal Tomek , Ilya K , Chad LeClair , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v11 1/5] clk: rockchip: support clocks registered late Date: Thu, 19 Sep 2024 11:09:44 +0200 Message-ID: <20240919091129.83500-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091129.83500-1-sebastian.reichel@collabora.com> References: <20240919091129.83500-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240919_021149_637075_23B1FFE2 X-CRM114-Status: GOOD ( 17.36 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org When some clocks are registered late and some clocks are registered early we need to make sure the late registered clocks report probe defer until the final registration has happened. But we do not want to keep reporting probe defer after the late registration has happened. Also not all Rockchip SoCs have late registered clocks and may not need to report probe defer at all. This restructures code a bit, so that there is a new function rockchip_clk_init_early(), which should be used for initializing the CRU structure on SoCs making use of late initialization in addition to the early init. These platforms should call rockchip_clk_finalize() once all clocks have been registered. Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/clk.c | 35 +++++++++++++++++++++++++++++++---- drivers/clk/rockchip/clk.h | 3 +++ 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 2fa7253c73b2..0d80729c18d6 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -359,14 +359,17 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name, return hw->clk; } -struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, - void __iomem *base, - unsigned long nr_clks) +static struct rockchip_clk_provider *rockchip_clk_init_base( + struct device_node *np, void __iomem *base, + unsigned long nr_clks, bool has_late_clocks) { struct rockchip_clk_provider *ctx; struct clk **clk_table; + struct clk *default_clk_val; int i; + default_clk_val = ERR_PTR(has_late_clocks ? -EPROBE_DEFER : -ENOENT); + ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); if (!ctx) return ERR_PTR(-ENOMEM); @@ -376,7 +379,7 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, goto err_free; for (i = 0; i < nr_clks; ++i) - clk_table[i] = ERR_PTR(-ENOENT); + clk_table[i] = default_clk_val; ctx->reg_base = base; ctx->clk_data.clks = clk_table; @@ -393,8 +396,32 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, kfree(ctx); return ERR_PTR(-ENOMEM); } + +struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, + void __iomem *base, + unsigned long nr_clks) +{ + return rockchip_clk_init_base(np, base, nr_clks, false); +} EXPORT_SYMBOL_GPL(rockchip_clk_init); +struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np, + void __iomem *base, + unsigned long nr_clks) +{ + return rockchip_clk_init_base(np, base, nr_clks, true); +} +EXPORT_SYMBOL_GPL(rockchip_clk_init_early); + +void rockchip_clk_finalize(struct rockchip_clk_provider *ctx) +{ + int i; + + for (i = 0; i < ctx->clk_data.clk_num; ++i) + if (ctx->clk_data.clks[i] == ERR_PTR(-EPROBE_DEFER)) + ctx->clk_data.clks[i] = ERR_PTR(-ENOENT); +} + void rockchip_clk_of_add_provider(struct device_node *np, struct rockchip_clk_provider *ctx) { diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index fd3b476dedda..e90d04fcd0ee 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -971,6 +971,9 @@ struct rockchip_clk_branch { struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks); +struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np, + void __iomem *base, unsigned long nr_clks); +void rockchip_clk_finalize(struct rockchip_clk_provider *ctx); void rockchip_clk_of_add_provider(struct device_node *np, struct rockchip_clk_provider *ctx); unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, From patchwork Thu Sep 19 09:09:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13807540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A328CE8D5F for ; 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Thu, 19 Sep 2024 11:11:47 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 230D8480084; Thu, 19 Sep 2024 11:11:47 +0200 (CEST) From: Sebastian Reichel To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Cc: Elaine Zhang , Kever Yang , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , huangtao@rock-chips.com, andy.yan@rock-chips.com, Michal Tomek , Ilya K , Chad LeClair , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v11 2/5] clk: rockchip: rk3588: register GATE_LINK later Date: Thu, 19 Sep 2024 11:09:45 +0200 Message-ID: <20240919091129.83500-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091129.83500-1-sebastian.reichel@collabora.com> References: <20240919091129.83500-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240919_021149_708504_E95AAF14 X-CRM114-Status: GOOD ( 20.83 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The proper GATE_LINK implementation will use runtime PM to handle the linked gate clocks, which requires device context. Currently all clocks are registered early via CLK_OF_DECLARE, which is before the kernel knows about devices. Moving the full clocks registration to the probe routine does not work, since the clocks needed for timers must be registered early. To work around this issue, most of the clock tree is registered early, but GATE_LINK clocks are handled in the probe routine. Since the resets are not needed early either, they have also been moved to the probe routine. Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/clk-rk3588.c | 66 +++++++++++++++++++++++++++---- 1 file changed, 58 insertions(+), 8 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 74051277ecea..b707105573d2 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -266,6 +266,8 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { }, \ } +static struct rockchip_clk_provider *early_ctx; + static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = { RK3588_CPUB01CLK_RATE(2496000000, 1), RK3588_CPUB01CLK_RATE(2400000000, 1), @@ -694,7 +696,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = { RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates), }; -static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { +static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { /* * CRU Clock-Architecture */ @@ -2428,7 +2430,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { RK3588_CLKGATE_CON(68), 5, GFLAGS), GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0, RK3588_CLKGATE_CON(68), 2, GFLAGS), +}; +static struct rockchip_clk_branch rk3588_clk_branches[] = { GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), @@ -2453,26 +2457,31 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), }; -static void __init rk3588_clk_init(struct device_node *np) +static void __init rk3588_clk_early_init(struct device_node *np) { struct rockchip_clk_provider *ctx; - unsigned long clk_nr_clks; + unsigned long clk_nr_clks, max_clk_id1, max_clk_id2; void __iomem *reg_base; - clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches, - ARRAY_SIZE(rk3588_clk_branches)) + 1; + max_clk_id1 = rockchip_clk_find_max_clk_id(rk3588_clk_branches, + ARRAY_SIZE(rk3588_clk_branches)); + max_clk_id2 = rockchip_clk_find_max_clk_id(rk3588_early_clk_branches, + ARRAY_SIZE(rk3588_early_clk_branches)); + clk_nr_clks = max(max_clk_id1, max_clk_id2) + 1; + reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: could not map cru region\n", __func__); return; } - ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); + ctx = rockchip_clk_init_early(np, reg_base, clk_nr_clks); if (IS_ERR(ctx)) { pr_err("%s: rockchip clk init failed\n", __func__); iounmap(reg_base); return; } + early_ctx = ctx; rockchip_clk_register_plls(ctx, rk3588_pll_clks, ARRAY_SIZE(rk3588_pll_clks), @@ -2491,14 +2500,55 @@ static void __init rk3588_clk_init(struct device_node *np) &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, ARRAY_SIZE(rk3588_cpub1clk_rates)); + rockchip_clk_register_branches(ctx, rk3588_early_clk_branches, + ARRAY_SIZE(rk3588_early_clk_branches)); + + rockchip_clk_of_add_provider(np, ctx); +} +CLK_OF_DECLARE_DRIVER(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_early_init); + +static int clk_rk3588_probe(struct platform_device *pdev) +{ + struct rockchip_clk_provider *ctx = early_ctx; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + rockchip_clk_register_branches(ctx, rk3588_clk_branches, ARRAY_SIZE(rk3588_clk_branches)); - rk3588_rst_init(np, reg_base); + rockchip_clk_finalize(ctx); + rk3588_rst_init(np, ctx->reg_base); rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL); + /* + * Re-add clock provider, so that the newly added clocks are also + * re-parented and get their defaults configured. + */ + of_clk_del_provider(np); rockchip_clk_of_add_provider(np, ctx); + + return 0; } -CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init); +static const struct of_device_id clk_rk3588_match_table[] = { + { + .compatible = "rockchip,rk3588-cru", + }, + { } +}; + +static struct platform_driver clk_rk3588_driver = { + .probe = clk_rk3588_probe, + .driver = { + .name = "clk-rk3588", + .of_match_table = clk_rk3588_match_table, + .suppress_bind_attrs = true, + }, +}; + +static int __init rockchip_clk_rk3588_drv_register(void) +{ + return platform_driver_register(&clk_rk3588_driver); +} +core_initcall(rockchip_clk_rk3588_drv_register); From patchwork Thu Sep 19 09:09:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13807539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12BAECE8D63 for ; Thu, 19 Sep 2024 09:11:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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These might also have to do a lookup, so rename the function to rockchip_clk_set_lookup and add a matching rockchip_clk_get_lookup. Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/clk.c | 14 ++++---------- drivers/clk/rockchip/clk.h | 12 ++++++++++++ 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 0d80729c18d6..b87ca1e8c540 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -197,12 +197,6 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n); } -static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx, - struct clk *clk, unsigned int id) -{ - ctx->clk_data.clks[id] = clk; -} - static struct clk *rockchip_clk_register_frac_branch( struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, @@ -292,7 +286,7 @@ static struct clk *rockchip_clk_register_frac_branch( return mux_clk; } - rockchip_clk_add_lookup(ctx, mux_clk, child->id); + rockchip_clk_set_lookup(ctx, mux_clk, child->id); /* notifier on the fraction divider to catch rate changes */ if (frac->mux_frac_idx >= 0) { @@ -451,7 +445,7 @@ void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, continue; } - rockchip_clk_add_lookup(ctx, clk, list->id); + rockchip_clk_set_lookup(ctx, clk, list->id); } } EXPORT_SYMBOL_GPL(rockchip_clk_register_plls); @@ -613,7 +607,7 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, continue; } - rockchip_clk_add_lookup(ctx, clk, list->id); + rockchip_clk_set_lookup(ctx, clk, list->id); } } EXPORT_SYMBOL_GPL(rockchip_clk_register_branches); @@ -637,7 +631,7 @@ void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, return; } - rockchip_clk_add_lookup(ctx, clk, lookup_id); + rockchip_clk_set_lookup(ctx, clk, lookup_id); } EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index e90d04fcd0ee..3dc5fb9bac4f 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -969,6 +969,18 @@ struct rockchip_clk_branch { #define SGRF_GATE(_id, cname, pname) \ FACTOR(_id, cname, pname, 0, 1, 1) +static inline struct clk *rockchip_clk_get_lookup(struct rockchip_clk_provider *ctx, + unsigned int id) +{ + return ctx->clk_data.clks[id]; +} + +static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx, + struct clk *clk, unsigned int id) +{ + ctx->clk_data.clks[id] = clk; +} + struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks); struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np, From patchwork Thu Sep 19 09:09:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13807537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5EF8CE8D61 for ; Thu, 19 Sep 2024 09:11:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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Thu, 19 Sep 2024 11:11:47 +0200 (CEST) From: Sebastian Reichel To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Cc: Elaine Zhang , Kever Yang , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , huangtao@rock-chips.com, andy.yan@rock-chips.com, Michal Tomek , Ilya K , Chad LeClair , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v11 4/5] clk: rockchip: implement linked gate clock support Date: Thu, 19 Sep 2024 11:09:47 +0200 Message-ID: <20240919091129.83500-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091129.83500-1-sebastian.reichel@collabora.com> References: <20240919091129.83500-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240919_021149_666237_9BD3550F X-CRM114-Status: GOOD ( 33.38 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Recent Rockchip SoCs have a new hardware block called Native Interface Unit (NIU), which gates clocks to devices behind them. These clock gates will only have a running output clock when all of the following conditions are met: 1. the parent clock is enabled 2. the enable bit is set correctly 3. the linked clock is enabled To handle them this code registers them as a normal gate type clock, which takes care of condition 1 + 2. The linked clock is handled by using runtime PM clocks. Handling it via runtime PM requires setting up a struct device for each of these clocks with a driver attached to use the correct runtime PM operations. Thus the complete handling of these clocks has been moved into its own driver. Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3588.c | 23 +-------- drivers/clk/rockchip/clk.c | 52 +++++++++++++++++++ drivers/clk/rockchip/clk.h | 25 +++++++++ drivers/clk/rockchip/gate-link.c | 85 +++++++++++++++++++++++++++++++ 5 files changed, 165 insertions(+), 21 deletions(-) create mode 100644 drivers/clk/rockchip/gate-link.c diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 36894f6a7022..179be95c6ffb 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -13,6 +13,7 @@ clk-rockchip-y += clk-inverter.o clk-rockchip-y += clk-mmc-phase.o clk-rockchip-y += clk-muxgrf.o clk-rockchip-y += clk-ddr.o +clk-rockchip-y += gate-link.o clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o obj-$(CONFIG_CLK_PX30) += clk-px30.o diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index b707105573d2..4d85ae615e15 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -12,25 +12,6 @@ #include #include "clk.h" -/* - * Recent Rockchip SoCs have a new hardware block called Native Interface - * Unit (NIU), which gates clocks to devices behind them. These effectively - * need two parent clocks. - * - * Downstream enables the linked clock via runtime PM whenever the gate is - * enabled. This implementation uses separate clock nodes for each of the - * linked gate clocks, which leaks parts of the clock tree into DT. - * - * The GATE_LINK macro instead takes the second parent via 'linkname', but - * ignores the information. Once the clock framework is ready to handle it, the - * information should be passed on here. But since these clocks are required to - * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked - * clocks critical until a better solution is available. This will waste some - * power, but avoids leaking implementation details into DT or hanging the - * system. - */ -#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ - GATE(_id, cname, pname, f, o, b, gf) #define RK3588_LINKED_CLK CLK_IS_CRITICAL @@ -2513,8 +2494,8 @@ static int clk_rk3588_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; - rockchip_clk_register_branches(ctx, rk3588_clk_branches, - ARRAY_SIZE(rk3588_clk_branches)); + rockchip_clk_register_late_branches(dev, ctx, rk3588_clk_branches, + ARRAY_SIZE(rk3588_clk_branches)); rockchip_clk_finalize(ctx); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index b87ca1e8c540..f0d76d62382c 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -467,6 +468,29 @@ unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, } EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id); +static struct platform_device *rockchip_clk_register_gate_link( + struct device *parent_dev, + struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *clkbr) +{ + struct rockchip_gate_link_platdata gate_link_pdata = { + .ctx = ctx, + .clkbr = clkbr, + }; + + struct platform_device_info pdevinfo = { + .parent = parent_dev, + .name = "rockchip-gate-link-clk", + .id = clkbr->id, + .fwnode = dev_fwnode(parent_dev), + .of_node_reused = true, + .data = &gate_link_pdata, + .size_data = sizeof(gate_link_pdata), + }; + + return platform_device_register_full(&pdevinfo); +} + void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, struct rockchip_clk_branch *list, unsigned int nr_clk) @@ -592,6 +616,9 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, list->div_width, list->div_flags, ctx->reg_base, &ctx->lock); break; + case branch_linked_gate: + /* must be registered late, fall-through for error message */ + break; } /* none of the cases above matched */ @@ -612,6 +639,31 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, } EXPORT_SYMBOL_GPL(rockchip_clk_register_branches); +void rockchip_clk_register_late_branches(struct device *dev, + struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + unsigned int nr_clk) +{ + unsigned int idx; + + for (idx = 0; idx < nr_clk; idx++, list++) { + struct platform_device *pdev = NULL; + + switch (list->branch_type) { + case branch_linked_gate: + pdev = rockchip_clk_register_gate_link(dev, ctx, list); + break; + default: + dev_err(dev, "unknown clock type %d\n", list->branch_type); + break; + } + + if (!pdev) + dev_err(dev, "failed to register device for clock %s\n", list->name); + } +} +EXPORT_SYMBOL_GPL(rockchip_clk_register_late_branches); + void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, unsigned int lookup_id, const char *name, const char *const *parent_names, diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 3dc5fb9bac4f..3fb620f8dd57 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -517,6 +517,7 @@ enum rockchip_clk_branch_type { branch_divider, branch_fraction_divider, branch_gate, + branch_linked_gate, branch_mmc, branch_inverter, branch_factor, @@ -544,6 +545,7 @@ struct rockchip_clk_branch { int gate_offset; u8 gate_shift; u8 gate_flags; + unsigned int linked_clk_id; struct rockchip_clk_branch *child; }; @@ -842,6 +844,20 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \ + { \ + .id = _id, \ + .branch_type = branch_linked_gate, \ + .name = cname, \ + .parent_names = (const char *[]){ pname }, \ + .linked_clk_id = linkedclk, \ + .num_parents = 1, \ + .flags = f, \ + .gate_offset = o, \ + .gate_shift = b, \ + .gate_flags = gf, \ + } + #define MMC(_id, cname, pname, offset, shift) \ { \ .id = _id, \ @@ -981,6 +997,11 @@ static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx, ctx->clk_data.clks[id] = clk; } +struct rockchip_gate_link_platdata { + struct rockchip_clk_provider *ctx; + struct rockchip_clk_branch *clkbr; +}; + struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np, void __iomem *base, unsigned long nr_clks); struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np, @@ -993,6 +1014,10 @@ unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list, void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, struct rockchip_clk_branch *list, unsigned int nr_clk); +void rockchip_clk_register_late_branches(struct device *dev, + struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *list, + unsigned int nr_clk); void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, struct rockchip_pll_clock *pll_list, unsigned int nr_pll, int grf_lock_offset); diff --git a/drivers/clk/rockchip/gate-link.c b/drivers/clk/rockchip/gate-link.c new file mode 100644 index 000000000000..cd0f7a2d30ab --- /dev/null +++ b/drivers/clk/rockchip/gate-link.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024 Collabora Ltd. + * Author: Sebastian Reichel + */ + +#include +#include +#include +#include +#include +#include "clk.h" + +static int rk_clk_gate_link_register(struct device *dev, + struct rockchip_clk_provider *ctx, + struct rockchip_clk_branch *clkbr) +{ + unsigned long flags = clkbr->flags | CLK_SET_RATE_PARENT; + struct clk *clk; + + clk = clk_register_gate(dev, clkbr->name, clkbr->parent_names[0], + flags, ctx->reg_base + clkbr->gate_offset, + clkbr->gate_shift, clkbr->gate_flags, + &ctx->lock); + + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rockchip_clk_set_lookup(ctx, clk, clkbr->id); + return 0; +} + +static int rk_clk_gate_link_probe(struct platform_device *pdev) +{ + struct rockchip_gate_link_platdata *pdata; + struct device *dev = &pdev->dev; + struct clk *linked_clk; + int ret; + + pdata = dev_get_platdata(dev); + if (!pdata) + return dev_err_probe(dev, -ENODEV, "missing platform data"); + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret = devm_pm_clk_create(dev); + if (ret) + return ret; + + linked_clk = rockchip_clk_get_lookup(pdata->ctx, pdata->clkbr->linked_clk_id); + ret = pm_clk_add_clk(dev, linked_clk); + if (ret) + return ret; + + ret = rk_clk_gate_link_register(dev, pdata->ctx, pdata->clkbr); + if (ret) + goto err; + + return 0; + +err: + pm_clk_remove_clk(dev, linked_clk); + return ret; +} + +static const struct dev_pm_ops rk_clk_gate_link_pm_ops = { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static struct platform_driver rk_clk_gate_link_driver = { + .probe = rk_clk_gate_link_probe, + .driver = { + .name = "rockchip-gate-link-clk", + .pm = &rk_clk_gate_link_pm_ops, + .suppress_bind_attrs = true, + }, +}; + +static int __init rk_clk_gate_link_drv_register(void) +{ + return platform_driver_register(&rk_clk_gate_link_driver); +} +core_initcall(rk_clk_gate_link_drv_register); From patchwork Thu Sep 19 09:09:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13807542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63B81CE8D62 for ; Thu, 19 Sep 2024 09:12:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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b=C3sqEKNLbU4V94mIG2aa/Med8YT/FxsWuslthNZ5turWW38G/dz4GudPZAQ9GrFNk bOB3qqrOchGjcZdk6OIFC/yYU1hQnCB3+VfFBEH7RlcMvj/dwUEWwpMakHQ0UpZh41 9Q+xCHjmhw+2lFgfFUXsMVdSFSIb0gnzii/tXWqbaaepzfovCtAPxoJ8u/TM9QqKcf IAZ7QSpyRz9FvH20cgUu7PaKMVQgjATvMmfP7WzL70lQPqv9GscYV0IQpCYti1FkIM D6RoN5tbCzhkMzmAqJKpUeYkKIFFnkebPSsMcrWt8NppDzTPnaYfN0YwFt7tpO4XgP LveUojnLguJnA== Received: from jupiter.universe (dyndsl-091-248-208-160.ewe-ip-backbone.de [91.248.208.160]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id A96E417E1097; Thu, 19 Sep 2024 11:11:47 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id 28E34480088; Thu, 19 Sep 2024 11:11:47 +0200 (CEST) From: Sebastian Reichel To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org Cc: Elaine Zhang , Kever Yang , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , huangtao@rock-chips.com, andy.yan@rock-chips.com, Michal Tomek , Ilya K , Chad LeClair , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v11 5/5] clk: rockchip: rk3588: drop RK3588_LINKED_CLK Date: Thu, 19 Sep 2024 11:09:48 +0200 Message-ID: <20240919091129.83500-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240919091129.83500-1-sebastian.reichel@collabora.com> References: <20240919091129.83500-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240919_021153_059435_AC9BF2B7 X-CRM114-Status: GOOD ( 12.75 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org With the proper GATE_LINK support, we no longer need to keep the linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL flag for them. Signed-off-by: Sebastian Reichel --- drivers/clk/rockchip/clk-rk3588.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 4d85ae615e15..70d0873a761f 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -12,9 +12,6 @@ #include #include "clk.h" -#define RK3588_LINKED_CLK CLK_IS_CRITICAL - - #define RK3588_GRF_SOC_STATUS0 0x600 #define RK3588_PHYREF_ALT_GATE 0xc38 @@ -1439,7 +1436,7 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, RK3588_CLKGATE_CON(31), 0, GFLAGS), - COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(31), 1, GFLAGS), GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, @@ -1668,13 +1665,13 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { RK3588_CLKGATE_CON(42), 9, GFLAGS), /* vdpu */ - COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(44), 0, GFLAGS), COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, RK3588_CLKGATE_CON(44), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, RK3588_CLKGATE_CON(44), 2, GFLAGS), COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, @@ -1725,9 +1722,9 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, RK3588_CLKGATE_CON(47), 1, GFLAGS), - GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK, + GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, RK3588_CLKGATE_CON(47), 4, GFLAGS), - GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK, + GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, RK3588_CLKGATE_CON(47), 5, GFLAGS), COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, @@ -1737,10 +1734,10 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { RK3588_CLKGATE_CON(48), 6, GFLAGS), /* vi */ - COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK, + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(49), 0, GFLAGS), - COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, RK3588_CLKGATE_CON(49), 1, GFLAGS), COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, @@ -1910,10 +1907,10 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(52), 0, GFLAGS), - COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, RK3588_CLKGATE_CON(52), 1, GFLAGS), - COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, RK3588_CLKGATE_CON(52), 2, GFLAGS), COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, @@ -2416,7 +2413,7 @@ static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = { static struct rockchip_clk_branch rk3588_clk_branches[] = { GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), - GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), + GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), @@ -2428,9 +2425,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] = { GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), - GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), - GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),