From patchwork Thu Sep 19 21:01:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Alvaro (Al-vuh-roe) Reyes" X-Patchwork-Id: 13807988 X-Patchwork-Delegate: kuba@kernel.org Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F50743AA1 for ; Thu, 19 Sep 2024 21:01:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726779706; cv=none; b=pA8Y2wWLi4TcoH78SrjYF6KRVQdnt7tHm0WfhPmfBGLLeCYn8XUPYINvU3fyKEH3akNwmDSzsrnTbTLb6iDYWFvBgBQ2McGvL8/Vf+12OwocBgHF3ZtQ7+xXIrmgbiFR7XlI80cXBNw1xExTRMsiR6MOItYdX1kZfwWO+zHq48I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726779706; c=relaxed/simple; bh=IgOLremkTluc+1bSUyBYBWgKXFJo2qRE+So66OXoPno=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZJ2/maxy3nr1azZFOFI+4x7FQkJlCjgF55wsAPpMN6ZByh2OtF++0of1HWsRa8IAoL5fj75kKmI4vIRr8ZRGXDEM1LQarSlSMRW5VQt+pANsfDw7oSpiCFipD7Uz2WTOPtwJtIyAa4fpOQS288pWMzm4GYdR2zPP1ohE3RYe7eg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Fqbwaw6p; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Fqbwaw6p" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48JL1RYX000574; Thu, 19 Sep 2024 16:01:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1726779687; bh=TrC7QeET0mtJuUfj3JjOJwoOOv+aq3YydRXmnQ4tVpY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Fqbwaw6pgvhzomvYolRrlWjoJy50alCHheZMG5pBTxypUeGihYrbzts1AlGfghX/I hqo1jSF9uCghclOaVs+24dDQEJhuv8ViAejgxhIXMwAb56IMavHjHIgU3T+dhtHTX3 UOooA9/5gtcW1Lfoq149nEaIzRfge3unNJKJCUQQ= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48JL1RFe064365 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 19 Sep 2024 16:01:27 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 19 Sep 2024 16:01:26 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 19 Sep 2024 16:01:26 -0500 Received: from Linux-002.dhcp.ti.com (linux-002.dhcp.ti.com [10.188.34.182]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48JL1OC5098001; Thu, 19 Sep 2024 16:01:26 -0500 From: "Alvaro (Al-vuh-roe) Reyes" To: CC: , , , , , , , , , , , "Alvaro (Al-vuh-roe) Reyes" Subject: [PATCH 1/5] net: phy: dp83tg720: Changed Macro names Date: Thu, 19 Sep 2024 14:01:15 -0700 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-Patchwork-Delegate: kuba@kernel.org Previous macro referes to DP83TG720S, where this driver works for both DP83TG720R & DP83TG720S. Macro changed to DP83TG720 to be more generic. Data sheets: https://www.ti.com/lit/ds/symlink/dp83tg720s-q1.pdf https://www.ti.com/lit/ds/symlink/dp83tg720r-q1.pdf Signed-off-by: Alvaro (Al-vuh-roe) Reyes --- drivers/net/phy/dp83tg720.c | 116 ++++++++++++++++++------------------ 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c index 0ef4d7dba065..7e81800cfc5b 100644 --- a/drivers/net/phy/dp83tg720.c +++ b/drivers/net/phy/dp83tg720.c @@ -10,62 +10,62 @@ #include "open_alliance_helpers.h" -#define DP83TG720S_PHY_ID 0x2000a284 +#define DP83TG720_PHY_ID 0x2000a284 /* MDIO_MMD_VEND2 registers */ -#define DP83TG720S_MII_REG_10 0x10 -#define DP83TG720S_STS_MII_INT BIT(7) -#define DP83TG720S_LINK_STATUS BIT(0) +#define DP83TG720_MII_REG_10 0x10 +#define DP83TG720_STS_MII_INT BIT(7) +#define DP83TG720_LINK_STATUS BIT(0) /* TDR Configuration Register (0x1E) */ -#define DP83TG720S_TDR_CFG 0x1e +#define DP83TG720_TDR_CFG 0x1e /* 1b = TDR start, 0b = No TDR */ -#define DP83TG720S_TDR_START BIT(15) +#define DP83TG720_TDR_START BIT(15) /* 1b = TDR auto on link down, 0b = Manual TDR start */ -#define DP83TG720S_CFG_TDR_AUTO_RUN BIT(14) +#define DP83TG720_CFG_TDR_AUTO_RUN BIT(14) /* 1b = TDR done, 0b = TDR in progress */ -#define DP83TG720S_TDR_DONE BIT(1) +#define DP83TG720_TDR_DONE BIT(1) /* 1b = TDR fail, 0b = TDR success */ -#define DP83TG720S_TDR_FAIL BIT(0) +#define DP83TG720_TDR_FAIL BIT(0) -#define DP83TG720S_PHY_RESET 0x1f -#define DP83TG720S_HW_RESET BIT(15) +#define DP83TG720_PHY_RESET 0x1f +#define DP83TG720_HW_RESET BIT(15) -#define DP83TG720S_LPS_CFG3 0x18c +#define DP83TG720_LPS_CFG3 0x18c /* Power modes are documented as bit fields but used as values */ /* Power Mode 0 is Normal mode */ -#define DP83TG720S_LPS_CFG3_PWR_MODE_0 BIT(0) +#define DP83TG720_LPS_CFG3_PWR_MODE_0 BIT(0) /* Open Aliance 1000BaseT1 compatible HDD.TDR Fault Status Register */ -#define DP83TG720S_TDR_FAULT_STATUS 0x30f +#define DP83TG720_TDR_FAULT_STATUS 0x30f /* Register 0x0301: TDR Configuration 2 */ -#define DP83TG720S_TDR_CFG2 0x301 +#define DP83TG720_TDR_CFG2 0x301 /* Register 0x0303: TDR Configuration 3 */ -#define DP83TG720S_TDR_CFG3 0x303 +#define DP83TG720_TDR_CFG3 0x303 /* Register 0x0304: TDR Configuration 4 */ -#define DP83TG720S_TDR_CFG4 0x304 +#define DP83TG720_TDR_CFG4 0x304 /* Register 0x0405: Unknown Register */ -#define DP83TG720S_UNKNOWN_0405 0x405 +#define DP83TG720_UNKNOWN_0405 0x405 /* Register 0x0576: TDR Master Link Down Control */ -#define DP83TG720S_TDR_MASTER_LINK_DOWN 0x576 +#define DP83TG720_TDR_MASTER_LINK_DOWN 0x576 -#define DP83TG720S_RGMII_DELAY_CTRL 0x602 +#define DP83TG720_RGMII_DELAY_CTRL 0x602 /* In RGMII mode, Enable or disable the internal delay for RXD */ -#define DP83TG720S_RGMII_RX_CLK_SEL BIT(1) +#define DP83TG720_RGMII_RX_CLK_SEL BIT(1) /* In RGMII mode, Enable or disable the internal delay for TXD */ -#define DP83TG720S_RGMII_TX_CLK_SEL BIT(0) +#define DP83TG720_RGMII_TX_CLK_SEL BIT(0) /* Register 0x083F: Unknown Register */ -#define DP83TG720S_UNKNOWN_083F 0x83f +#define DP83TG720_UNKNOWN_083F 0x83f -#define DP83TG720S_SQI_REG_1 0x871 -#define DP83TG720S_SQI_OUT_WORST GENMASK(7, 5) -#define DP83TG720S_SQI_OUT GENMASK(3, 1) +#define DP83TG720_SQI_REG_1 0x871 +#define DP83TG720_SQI_OUT_WORST GENMASK(7, 5) +#define DP83TG720_SQI_OUT GENMASK(3, 1) #define DP83TG720_SQI_MAX 7 @@ -82,7 +82,7 @@ static int dp83tg720_cable_test_start(struct phy_device *phydev) int ret; /* Initialize the PHY to run the TDR test as described in the - * "DP83TG720S-Q1: Configuring for Open Alliance Specification + * "DP83TG720-Q1: Configuring for Open Alliance Specification * Compliance (Rev. B)" application note. * Most of the registers are not documented. Some of register names * are guessed by comparing the register offsets with the DP83TD510E. @@ -90,38 +90,38 @@ static int dp83tg720_cable_test_start(struct phy_device *phydev) /* Force master link down */ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, - DP83TG720S_TDR_MASTER_LINK_DOWN, 0x0400); + DP83TG720_TDR_MASTER_LINK_DOWN, 0x0400); if (ret) return ret; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2, + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG2, 0xa008); if (ret) return ret; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3, + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG3, 0x0928); if (ret) return ret; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG4, + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG4, 0x0004); if (ret) return ret; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_0405, + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_UNKNOWN_0405, 0x6400); if (ret) return ret; - ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_083F, + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_UNKNOWN_083F, 0x3003); if (ret) return ret; /* Start the TDR */ - ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG, - DP83TG720S_TDR_START); + ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG, + DP83TG720_TDR_START); if (ret) return ret; @@ -146,21 +146,21 @@ static int dp83tg720_cable_test_get_status(struct phy_device *phydev, *finished = false; /* Read the TDR status */ - ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG); + ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG); if (ret < 0) return ret; /* Check if the TDR test is done */ - if (!(ret & DP83TG720S_TDR_DONE)) + if (!(ret & DP83TG720_TDR_DONE)) return 0; /* Check for TDR test failure */ - if (!(ret & DP83TG720S_TDR_FAIL)) { + if (!(ret & DP83TG720_TDR_FAIL)) { int location; /* Read fault status */ ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, - DP83TG720S_TDR_FAULT_STATUS); + DP83TG720_TDR_FAULT_STATUS); if (ret < 0) return ret; @@ -214,8 +214,8 @@ static int dp83tg720_read_status(struct phy_device *phydev) /* Most of Clause 45 registers are not present, so we can't use * genphy_c45_read_status() here. */ - phy_sts = phy_read(phydev, DP83TG720S_MII_REG_10); - phydev->link = !!(phy_sts & DP83TG720S_LINK_STATUS); + phy_sts = phy_read(phydev, DP83TG720_MII_REG_10); + phydev->link = !!(phy_sts & DP83TG720_LINK_STATUS); if (!phydev->link) { /* According to the "DP83TC81x, DP83TG72x Software * Implementation Guide", the PHY needs to be reset after a @@ -261,11 +261,11 @@ static int dp83tg720_get_sqi(struct phy_device *phydev) if (!phydev->link) return 0; - ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_SQI_REG_1); + ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_SQI_REG_1); if (ret < 0) return ret; - return FIELD_GET(DP83TG720S_SQI_OUT, ret); + return FIELD_GET(DP83TG720_SQI_OUT, ret); } static int dp83tg720_get_sqi_max(struct phy_device *phydev) @@ -283,24 +283,24 @@ static int dp83tg720_config_rgmii_delay(struct phy_device *phydev) rgmii_delay = 0; break; case PHY_INTERFACE_MODE_RGMII_ID: - rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL | - DP83TG720S_RGMII_TX_CLK_SEL; + rgmii_delay = DP83TG720_RGMII_RX_CLK_SEL | + DP83TG720_RGMII_TX_CLK_SEL; break; case PHY_INTERFACE_MODE_RGMII_RXID: - rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL; + rgmii_delay = DP83TG720_RGMII_RX_CLK_SEL; break; case PHY_INTERFACE_MODE_RGMII_TXID: - rgmii_delay = DP83TG720S_RGMII_TX_CLK_SEL; + rgmii_delay = DP83TG720_RGMII_TX_CLK_SEL; break; default: return 0; } - rgmii_delay_mask = DP83TG720S_RGMII_RX_CLK_SEL | - DP83TG720S_RGMII_TX_CLK_SEL; + rgmii_delay_mask = DP83TG720_RGMII_RX_CLK_SEL | + DP83TG720_RGMII_TX_CLK_SEL; return phy_modify_mmd(phydev, MDIO_MMD_VEND2, - DP83TG720S_RGMII_DELAY_CTRL, rgmii_delay_mask, + DP83TG720_RGMII_DELAY_CTRL, rgmii_delay_mask, rgmii_delay); } @@ -311,12 +311,12 @@ static int dp83tg720_config_init(struct phy_device *phydev) /* Software Restart is not enough to recover from a link failure. * Using Hardware Reset instead. */ - ret = phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET); + ret = phy_write(phydev, DP83TG720_PHY_RESET, DP83TG720_HW_RESET); if (ret) return ret; /* Wait until MDC can be used again. - * The wait value of one 1ms is documented in "DP83TG720S-Q1 1000BASE-T1 + * The wait value of one 1ms is documented in "DP83TG720-Q1 1000BASE-T1 * Automotive Ethernet PHY with SGMII and RGMII" datasheet. */ usleep_range(1000, 2000); @@ -330,8 +330,8 @@ static int dp83tg720_config_init(struct phy_device *phydev) /* In case the PHY is bootstrapped in managed mode, we need to * wake it. */ - ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LPS_CFG3, - DP83TG720S_LPS_CFG3_PWR_MODE_0); + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_LPS_CFG3, + DP83TG720_LPS_CFG3_PWR_MODE_0); if (ret) return ret; @@ -343,8 +343,8 @@ static int dp83tg720_config_init(struct phy_device *phydev) static struct phy_driver dp83tg720_driver[] = { { - PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID), - .name = "TI DP83TG720S", + PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID), + .name = "TI DP83TG720", .flags = PHY_POLL_CABLE_TEST, .config_aneg = dp83tg720_config_aneg, @@ -362,11 +362,11 @@ static struct phy_driver dp83tg720_driver[] = { module_phy_driver(dp83tg720_driver); static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = { - { PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID) }, + { PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID) }, { } }; MODULE_DEVICE_TABLE(mdio, dp83tg720_tbl); -MODULE_DESCRIPTION("Texas Instruments DP83TG720S PHY driver"); +MODULE_DESCRIPTION("Texas Instruments DP83TG720 PHY driver"); MODULE_AUTHOR("Oleksij Rempel "); MODULE_LICENSE("GPL"); From patchwork Thu Sep 19 21:01:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Alvaro (Al-vuh-roe) Reyes" X-Patchwork-Id: 13807989 X-Patchwork-Delegate: kuba@kernel.org Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8BA32B9B8 for ; Thu, 19 Sep 2024 21:01:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; 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Thu, 19 Sep 2024 16:01:31 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 19 Sep 2024 16:01:30 -0500 Received: from Linux-002.dhcp.ti.com (linux-002.dhcp.ti.com [10.188.34.182]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48JL1OC6098001; Thu, 19 Sep 2024 16:01:30 -0500 From: "Alvaro (Al-vuh-roe) Reyes" To: CC: , , , , , , , , , , , "Alvaro (Al-vuh-roe) Reyes" Subject: [PATCH 2/5] net: phy: dp83tg720: Added SGMII Support Date: Thu, 19 Sep 2024 14:01:16 -0700 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-Patchwork-Delegate: kuba@kernel.org Adding SGMII Support to driver by checking if SGMII is enabled and writing to the SGMII registers to ensure PHY is configured correctly. Signed-off-by: Alvaro (Al-vuh-roe) Reyes --- drivers/net/phy/dp83tg720.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c index 7e81800cfc5b..a6f90293aa61 100644 --- a/drivers/net/phy/dp83tg720.c +++ b/drivers/net/phy/dp83tg720.c @@ -12,6 +12,9 @@ #define DP83TG720_PHY_ID 0x2000a284 +#define MMD1F 0x1f +#define MMD1 0x1 + /* MDIO_MMD_VEND2 registers */ #define DP83TG720_MII_REG_10 0x10 #define DP83TG720_STS_MII_INT BIT(7) @@ -69,6 +72,13 @@ #define DP83TG720_SQI_MAX 7 +/* SGMII CTRL Registers/bits */ +#define DP83TG720_SGMII_CTRL 0x0608 +#define SGMII_CONFIG_VAL 0x027B +#define DP83TG720_SGMII_AUTO_NEG_EN BIT(0) +#define DP83TG720_SGMII_EN BIT(9) + + /** * dp83tg720_cable_test_start - Start the cable test for the DP83TG720 PHY. * @phydev: Pointer to the phy_device structure. @@ -306,7 +316,7 @@ static int dp83tg720_config_rgmii_delay(struct phy_device *phydev) static int dp83tg720_config_init(struct phy_device *phydev) { - int ret; + int value, ret; /* Software Restart is not enough to recover from a link failure. * Using Hardware Reset instead. @@ -327,6 +337,19 @@ static int dp83tg720_config_init(struct phy_device *phydev) return ret; } + value = phy_read_mmd(phydev, MMD1F, DP83TG720_SGMII_CTRL); + if (value < 0) + return value; + + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) + value |= DP83TG720_SGMII_EN; + else + value &= ~DP83TG720_SGMII_EN; + + ret = phy_write_mmd(phydev, MMD1F, DP83TG720_SGMII_CTRL, value); + if (ret < 0) + return ret; + /* In case the PHY is bootstrapped in managed mode, we need to * wake it. */ From patchwork Thu Sep 19 21:01:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Alvaro (Al-vuh-roe) Reyes" X-Patchwork-Id: 13807992 X-Patchwork-Delegate: kuba@kernel.org Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72132143736 for ; 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Thu, 19 Sep 2024 16:01:32 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 19 Sep 2024 16:01:32 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 19 Sep 2024 16:01:32 -0500 Received: from Linux-002.dhcp.ti.com (linux-002.dhcp.ti.com [10.188.34.182]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48JL1OC7098001; Thu, 19 Sep 2024 16:01:31 -0500 From: "Alvaro (Al-vuh-roe) Reyes" To: CC: , , , , , , , , , , , "Alvaro (Al-vuh-roe) Reyes" Subject: [PATCH 3/5] net: phy: dp83tg720: Extending support to DP83TG721 PHY Date: Thu, 19 Sep 2024 14:01:17 -0700 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-Patchwork-Delegate: kuba@kernel.org The DP83TG721 is the next revision of the DP83TG720 and will share the same driver. Added PHY_ID and probe funtion to check which version is being loaded. Signed-off-by: Alvaro (Al-vuh-roe) Reyes --- drivers/net/phy/dp83tg720.c | 183 ++++++++++++++++++++++++++++-------- 1 file changed, 146 insertions(+), 37 deletions(-) diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c index a6f90293aa61..b70802818f3c 100644 --- a/drivers/net/phy/dp83tg720.c +++ b/drivers/net/phy/dp83tg720.c @@ -10,8 +10,8 @@ #include "open_alliance_helpers.h" -#define DP83TG720_PHY_ID 0x2000a284 - +#define DP83TG720_CS_1_1_PHY_ID 0x2000a284 +#define DP83TG721_CS_1_0_PHY_ID 0x2000a290 #define MMD1F 0x1f #define MMD1 0x1 @@ -21,41 +21,41 @@ #define DP83TG720_LINK_STATUS BIT(0) /* TDR Configuration Register (0x1E) */ -#define DP83TG720_TDR_CFG 0x1e +#define DP83TG720_TDR_CFG 0x1e /* 1b = TDR start, 0b = No TDR */ -#define DP83TG720_TDR_START BIT(15) +#define DP83TG720_TDR_START BIT(15) /* 1b = TDR auto on link down, 0b = Manual TDR start */ #define DP83TG720_CFG_TDR_AUTO_RUN BIT(14) /* 1b = TDR done, 0b = TDR in progress */ -#define DP83TG720_TDR_DONE BIT(1) +#define DP83TG720_TDR_DONE BIT(1) /* 1b = TDR fail, 0b = TDR success */ -#define DP83TG720_TDR_FAIL BIT(0) +#define DP83TG720_TDR_FAIL BIT(0) -#define DP83TG720_PHY_RESET 0x1f -#define DP83TG720_HW_RESET BIT(15) +#define DP83TG720_PHY_RESET 0x1f +#define DP83TG720_HW_RESET BIT(15) -#define DP83TG720_LPS_CFG3 0x18c +#define DP83TG720_LPS_CFG3 0x18c /* Power modes are documented as bit fields but used as values */ /* Power Mode 0 is Normal mode */ -#define DP83TG720_LPS_CFG3_PWR_MODE_0 BIT(0) +#define DP83TG720_LPS_CFG3_PWR_MODE_0 BIT(0) /* Open Aliance 1000BaseT1 compatible HDD.TDR Fault Status Register */ #define DP83TG720_TDR_FAULT_STATUS 0x30f /* Register 0x0301: TDR Configuration 2 */ -#define DP83TG720_TDR_CFG2 0x301 +#define DP83TG720_TDR_CFG2 0x301 /* Register 0x0303: TDR Configuration 3 */ -#define DP83TG720_TDR_CFG3 0x303 +#define DP83TG720_TDR_CFG3 0x303 /* Register 0x0304: TDR Configuration 4 */ -#define DP83TG720_TDR_CFG4 0x304 +#define DP83TG720_TDR_CFG4 0x304 /* Register 0x0405: Unknown Register */ #define DP83TG720_UNKNOWN_0405 0x405 /* Register 0x0576: TDR Master Link Down Control */ -#define DP83TG720_TDR_MASTER_LINK_DOWN 0x576 +#define DP83TG720_TDR_MASTER_LINK_DOWN 0x576 #define DP83TG720_RGMII_DELAY_CTRL 0x602 /* In RGMII mode, Enable or disable the internal delay for RXD */ @@ -66,11 +66,11 @@ /* Register 0x083F: Unknown Register */ #define DP83TG720_UNKNOWN_083F 0x83f -#define DP83TG720_SQI_REG_1 0x871 -#define DP83TG720_SQI_OUT_WORST GENMASK(7, 5) -#define DP83TG720_SQI_OUT GENMASK(3, 1) +#define DP83TG720_SQI_REG_1 0x871 +#define DP83TG720_SQI_OUT_WORST GENMASK(7, 5) +#define DP83TG720_SQI_OUT GENMASK(3, 1) -#define DP83TG720_SQI_MAX 7 +#define DP83TG720_SQI_MAX 7 /* SGMII CTRL Registers/bits */ #define DP83TG720_SGMII_CTRL 0x0608 @@ -78,6 +78,54 @@ #define DP83TG720_SGMII_AUTO_NEG_EN BIT(0) #define DP83TG720_SGMII_EN BIT(9) +/* Strap Register/bits */ +#define DP83TG720_STRAP 0x045d +#define DP83TG720_MASTER_MODE BIT(5) +#define DP83TG720_RGMII_IS_EN BIT(12) +#define DP83TG720_SGMII_IS_EN BIT(13) +#define DP83TG720_RX_SHIFT_EN BIT(14) +#define DP83TG720_TX_SHIFT_EN BIT(15) + +enum DP83TG720_chip_type { + DP83TG720_CS1_1, + DP83TG721_CS1, +}; + +struct DP83TG720_private { + int chip; + bool is_master; + bool is_rgmii; + bool is_sgmii; + bool rx_shift; + bool tx_shift; +}; + +static int dp83tg720_read_straps(struct phy_device *phydev) +{ + struct DP83TG720_private *DP83TG720 = phydev->priv; + int strap; + + strap = phy_read_mmd(phydev, MMD1F, DP83TG720_STRAP); + if (strap < 0) + return strap; + + if (strap & DP83TG720_MASTER_MODE) + DP83TG720->is_master = true; + + if (strap & DP83TG720_RGMII_IS_EN) + DP83TG720->is_rgmii = true; + + if (strap & DP83TG720_SGMII_IS_EN) + DP83TG720->is_sgmii = true; + + if (strap & DP83TG720_RX_SHIFT_EN) + DP83TG720->rx_shift = true; + + if (strap & DP83TG720_TX_SHIFT_EN) + DP83TG720->tx_shift = true; + + return 0; +}; /** * dp83tg720_cable_test_start - Start the cable test for the DP83TG720 PHY. @@ -364,32 +412,93 @@ static int dp83tg720_config_init(struct phy_device *phydev) return genphy_c45_pma_baset1_read_master_slave(phydev); } -static struct phy_driver dp83tg720_driver[] = { +static int dp83tg720_probe(struct phy_device *phydev) { - PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID), - .name = "TI DP83TG720", - - .flags = PHY_POLL_CABLE_TEST, - .config_aneg = dp83tg720_config_aneg, - .read_status = dp83tg720_read_status, - .get_features = genphy_c45_pma_read_ext_abilities, - .config_init = dp83tg720_config_init, - .get_sqi = dp83tg720_get_sqi, - .get_sqi_max = dp83tg720_get_sqi_max, - .cable_test_start = dp83tg720_cable_test_start, - .cable_test_get_status = dp83tg720_cable_test_get_status, - - .suspend = genphy_suspend, - .resume = genphy_resume, -} }; + struct DP83TG720_private *DP83TG720; + int ret; + + DP83TG720 = devm_kzalloc(&phydev->mdio.dev, sizeof(*DP83TG720), + GFP_KERNEL); + if (!DP83TG720) + return -ENOMEM; + + phydev->priv = DP83TG720; + + ret = dp83tg720_read_straps(phydev); + if (ret) + return ret; + + switch (phydev->phy_id) { + case DP83TG720_CS_1_1_PHY_ID: + DP83TG720->chip = DP83TG720_CS1_1; + break; + case DP83TG721_CS_1_0_PHY_ID: + DP83TG720->chip = DP83TG721_CS1; + break; + default: + return -EINVAL; + }; + + return dp83tg720_config_init(phydev); +} + +#define DP83TG720_PHY_DRIVER(_id, _name) \ +{ \ + PHY_ID_MATCH_EXACT(_id), \ + .name = (_name), \ + .probe = dp83tg720_probe, \ + .flags = PHY_POLL_CABLE_TEST, \ + .config_aneg = dp83tg720_config_aneg, \ + .read_status = dp83tg720_read_status, \ + .get_features = genphy_c45_pma_read_ext_abilities, \ + .config_init = dp83tg720_config_init, \ + .get_sqi = dp83tg720_get_sqi, \ + .get_sqi_max = dp83tg720_get_sqi_max, \ + .cable_test_start = dp83tg720_cable_test_start, \ + .cable_test_get_status = dp83tg720_cable_test_get_status, \ + .suspend = genphy_suspend, \ + .resume = genphy_resume, \ +} + +static struct phy_driver dp83tg720_driver[] = { + DP83TG720_PHY_DRIVER(DP83TG720_CS_1_1_PHY_ID, "TI DP83TG720CS1.1"), + DP83TG720_PHY_DRIVER(DP83TG721_CS_1_0_PHY_ID, "TI DP83TG721CS1.0"), +}; module_phy_driver(dp83tg720_driver); static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = { - { PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID) }, - { } + { PHY_ID_MATCH_EXACT(DP83TG720_CS_1_1_PHY_ID) }, + { PHY_ID_MATCH_EXACT(DP83TG721_CS_1_0_PHY_ID) }, + { }, }; MODULE_DEVICE_TABLE(mdio, dp83tg720_tbl); +// static struct phy_driver dp83tg720_driver[] = { +// { +// PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID), +// .name = "TI DP83TG720", + +// .flags = PHY_POLL_CABLE_TEST, +// .config_aneg = dp83tg720_config_aneg, +// .read_status = dp83tg720_read_status, +// .get_features = genphy_c45_pma_read_ext_abilities, +// .config_init = dp83tg720_config_init, +// .get_sqi = dp83tg720_get_sqi, +// .get_sqi_max = dp83tg720_get_sqi_max, +// .cable_test_start = dp83tg720_cable_test_start, +// .cable_test_get_status = dp83tg720_cable_test_get_status, + +// .suspend = genphy_suspend, +// .resume = genphy_resume, +// } }; +// module_phy_driver(dp83tg720_driver); + +// static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = { +// { PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID) }, +// { } +// }; +// MODULE_DEVICE_TABLE(mdio, dp83tg720_tbl); + MODULE_DESCRIPTION("Texas Instruments DP83TG720 PHY driver"); MODULE_AUTHOR("Oleksij Rempel "); MODULE_LICENSE("GPL"); From patchwork Thu Sep 19 21:01:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Alvaro (Al-vuh-roe) Reyes" X-Patchwork-Id: 13807991 X-Patchwork-Delegate: kuba@kernel.org Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 940451428FA for ; Thu, 19 Sep 2024 21:01:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726779706; cv=none; b=qoFS3JlKCTUfs6fncMOPikZMpDntNoN5qSyqfL8/+CgLHGdjyjBoqvnkQzqrncb9j+fFUxv4dKpzc0REaOQ3OAoe2Ak8ZQ9pG4GcElu1BFQiiKA/6s8SgJlasvp7Ptemq+AF24rpsuRBxnBKfz1ffvVHX0Nr3iKg2JVLKsw29i8= ARC-Message-Signature: i=1; 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Thu, 19 Sep 2024 16:01:34 -0500 Received: from Linux-002.dhcp.ti.com (linux-002.dhcp.ti.com [10.188.34.182]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48JL1OC8098001; Thu, 19 Sep 2024 16:01:33 -0500 From: "Alvaro (Al-vuh-roe) Reyes" To: CC: , , , , , , , , , , , "Alvaro (Al-vuh-roe) Reyes" Subject: [PATCH 4/5] net: phy: dp83tg720: Added OA script Date: Thu, 19 Sep 2024 14:01:18 -0700 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-Patchwork-Delegate: kuba@kernel.org For the DP83TG720 & DP83TG721 to function properly, both need an initialization script to be run at boot up. The init script and a chip_init function have been added to handle this condition. Signed-off-by: Alvaro (Al-vuh-roe) Reyes --- drivers/net/phy/dp83tg720.c | 355 ++++++++++++++++++++++++++++++++---- 1 file changed, 324 insertions(+), 31 deletions(-) diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c index b70802818f3c..4df6713c51e3 100644 --- a/drivers/net/phy/dp83tg720.c +++ b/drivers/net/phy/dp83tg720.c @@ -31,8 +31,9 @@ /* 1b = TDR fail, 0b = TDR success */ #define DP83TG720_TDR_FAIL BIT(0) -#define DP83TG720_PHY_RESET 0x1f -#define DP83TG720_HW_RESET BIT(15) +#define DP83TG720_PHY_RESET_CTRL 0x1f +#define DP83TG720_HW_RESET BIT(15) +#define DP83TG720_SW_RESET BIT(14) #define DP83TG720_LPS_CFG3 0x18c /* Power modes are documented as bit fields but used as values */ @@ -100,6 +101,221 @@ struct DP83TG720_private { bool tx_shift; }; +struct DP83TG720_init_reg { + int MMD; + int reg; + int val; +}; + +/*Refer to SNLA371 for more information*/ +static const struct DP83TG720_init_reg DP83TG720_cs1_1_master_init[] = { + {0x1F, 0x001F, 0X8000}, + {0x1F, 0x0573, 0x0101}, + {0x1, 0x0834, 0xC001}, + {0x1F, 0x0405, 0x5800}, + {0x1F, 0x08AD, 0x3C51}, + {0x1F, 0x0894, 0x5DF7}, + {0x1F, 0x08A0, 0x09E7}, + {0x1F, 0x08C0, 0x4000}, + {0x1F, 0x0814, 0x4800}, + {0x1F, 0x080D, 0x2EBF}, + {0x1F, 0x08C1, 0x0B00}, + {0x1F, 0x087D, 0x0001}, + {0x1F, 0x082E, 0x0000}, + {0x1F, 0x0837, 0x00F4}, + {0x1F, 0x08BE, 0x0200}, + {0x1F, 0x08C5, 0x4000}, + {0x1F, 0x08C7, 0x2000}, + {0x1F, 0x08B3, 0x005A}, + {0x1F, 0x08B4, 0x005A}, + {0x1F, 0x08B0, 0x0202}, + {0x1F, 0x08B5, 0x00EA}, + {0x1F, 0x08BA, 0x2828}, + {0x1F, 0x08BB, 0x6828}, + {0x1F, 0x08BC, 0x0028}, + {0x1F, 0x08BF, 0x0000}, + {0x1F, 0x08B1, 0x0014}, + {0x1F, 0x08B2, 0x0008}, + {0x1F, 0x08EC, 0x0000}, + {0x1F, 0x08C8, 0x0003}, + {0x1F, 0x08BE, 0x0201}, + {0x1F, 0x018C, 0x0001}, + {0x1F, 0x001F, 0x4000}, + {0x1F, 0x0573, 0x0001}, + {0x1F, 0x056A, 0x5F41}, +}; + +/*Refer to SNLA371 for more information*/ +static const struct DP83TG720_init_reg DP83TG720_cs1_1_slave_init[] = { + {0x1F, 0x001F, 0x8000}, + {0x1F, 0x0573, 0x0101}, + {0x1, 0x0834, 0x8001}, + {0x1F, 0x0894, 0x5DF7}, + {0x1F, 0x056a, 0x5F40}, + {0x1F, 0x0405, 0x5800}, + {0x1F, 0x08AD, 0x3C51}, + {0x1F, 0x0894, 0x5DF7}, + {0x1F, 0x08A0, 0x09E7}, + {0x1F, 0x08C0, 0x4000}, + {0x1F, 0x0814, 0x4800}, + {0x1F, 0x080D, 0x2EBF}, + {0x1F, 0x08C1, 0x0B00}, + {0x1F, 0x087d, 0x0001}, + {0x1F, 0x082E, 0x0000}, + {0x1F, 0x0837, 0x00f4}, + {0x1F, 0x08BE, 0x0200}, + {0x1F, 0x08C5, 0x4000}, + {0x1F, 0x08C7, 0x2000}, + {0x1F, 0x08B3, 0x005A}, + {0x1F, 0x08B4, 0x005A}, + {0x1F, 0x08B0, 0x0202}, + {0x1F, 0x08B5, 0x00EA}, + {0x1F, 0x08BA, 0x2828}, + {0x1F, 0x08BB, 0x6828}, + {0x1F, 0x08BC, 0x0028}, + {0x1F, 0x08BF, 0x0000}, + {0x1F, 0x08B1, 0x0014}, + {0x1F, 0x08B2, 0x0008}, + {0x1F, 0x08EC, 0x0000}, + {0x1F, 0x08C8, 0x0003}, + {0x1F, 0x08BE, 0x0201}, + {0x1F, 0x056A, 0x5F40}, + {0x1F, 0x018C, 0x0001}, + {0x1F, 0x001F, 0x4000}, + {0x1F, 0x0573, 0x0001}, + {0x1F, 0x056A, 0X5F41}, +}; + +/*Refer to SNLA371 for more information*/ +static const struct DP83TG720_init_reg DP83TG721_cs1_master_init[] = { + {0x1F, 0x001F, 0x8000}, + {0x1F, 0x0573, 0x0801}, + {0x1, 0x0834, 0xC001}, + {0x1F, 0x0405, 0x6C00}, + {0x1F, 0x08AD, 0x3C51}, + {0x1F, 0x0894, 0x5DF7}, + {0x1F, 0x08A0, 0x09E7}, + {0x1F, 0x08C0, 0x4000}, + {0x1F, 0x0814, 0x4800}, + {0x1F, 0x080D, 0x2EBF}, + {0x1F, 0x08C1, 0x0B00}, + {0x1F, 0x087D, 0x0001}, + {0x1F, 0x082E, 0x0000}, + {0x1F, 0x0837, 0x00F8}, + {0x1F, 0x08BE, 0x0200}, + {0x1F, 0x08C5, 0x4000}, + {0x1F, 0x08C7, 0x2000}, + {0x1F, 0x08B3, 0x005A}, + {0x1F, 0x08B4, 0x005A}, + {0x1F, 0x08B0, 0x0202}, + {0x1F, 0x08B5, 0x00EA}, + {0x1F, 0x08BA, 0x2828}, + {0x1F, 0x08BB, 0x6828}, + {0x1F, 0x08BC, 0x0028}, + {0x1F, 0x08BF, 0x0000}, + {0x1F, 0x08B1, 0x0014}, + {0x1F, 0x08B2, 0x0008}, + {0x1F, 0x08EC, 0x0000}, + {0x1F, 0x08FC, 0x0091}, + {0x1F, 0x08BE, 0x0201}, + {0x1F, 0x0335, 0x0010}, + {0x1F, 0x0336, 0x0009}, + {0x1F, 0x0337, 0x0208}, + {0x1F, 0x0338, 0x0208}, + {0x1F, 0x0339, 0x02CB}, + {0x1F, 0x033A, 0x0208}, + {0x1F, 0x033B, 0x0109}, + {0x1F, 0x0418, 0x0380}, + {0x1F, 0x0420, 0xFF10}, + {0x1F, 0x0421, 0x4033}, + {0x1F, 0x0422, 0x0800}, + {0x1F, 0x0423, 0x0002}, + {0x1F, 0x0484, 0x0003}, + {0x1F, 0x055D, 0x0008}, + {0x1F, 0x042B, 0x0018}, + {0x1F, 0x087C, 0x0080}, + {0x1F, 0x08C1, 0x0900}, + {0x1F, 0x08fc, 0x4091}, + {0x1F, 0x0881, 0x5146}, + {0x1F, 0x08be, 0x02a1}, + {0x1F, 0x0867, 0x9999}, + {0x1F, 0x0869, 0x9666}, + {0x1F, 0x086a, 0x0009}, + {0x1F, 0x0822, 0x11e1}, + {0x1F, 0x08f9, 0x1f11}, + {0x1F, 0x08a3, 0x24e8}, + {0x1F, 0x018C, 0x0001}, + {0x1F, 0x001F, 0x4000}, + {0x1F, 0x0573, 0x0001}, + {0x1F, 0x056A, 0x5F41}, +}; + +/*Refer to SNLA371 for more information*/ +static const struct DP83TG720_init_reg DP83TG721_cs1_slave_init[] = { + {0x1F, 0x001F, 0x8000}, + {0x1F, 0x0573, 0x0801}, + {0x1, 0x0834, 0x8001}, + {0x1F, 0x0405, 0X6C00}, + {0x1F, 0x08AD, 0x3C51}, + {0x1F, 0x0894, 0x5DF7}, + {0x1F, 0x08A0, 0x09E7}, + {0x1F, 0x08C0, 0x4000}, + {0x1F, 0x0814, 0x4800}, + {0x1F, 0x080D, 0x2EBF}, + {0x1F, 0x08C1, 0x0B00}, + {0x1F, 0x087D, 0x0001}, + {0x1F, 0x082E, 0x0000}, + {0x1F, 0x0837, 0x00F8}, + {0x1F, 0x08BE, 0x0200}, + {0x1F, 0x08C5, 0x4000}, + {0x1F, 0x08C7, 0x2000}, + {0x1F, 0x08B3, 0x005A}, + {0x1F, 0x08B4, 0x005A}, + {0x1F, 0x08B0, 0x0202}, + {0x1F, 0x08B5, 0x00EA}, + {0x1F, 0x08BA, 0x2828}, + {0x1F, 0x08BB, 0x6828}, + {0x1F, 0x08BC, 0x0028}, + {0x1F, 0x08BF, 0x0000}, + {0x1F, 0x08B1, 0x0014}, + {0x1F, 0x08B2, 0x0008}, + {0x1F, 0x08EC, 0x0000}, + {0x1F, 0x08FC, 0x0091}, + {0x1F, 0x08BE, 0x0201}, + {0x1F, 0x0456, 0x0160}, + {0x1F, 0x0335, 0x0010}, + {0x1F, 0x0336, 0x0009}, + {0x1F, 0x0337, 0x0208}, + {0x1F, 0x0338, 0x0208}, + {0x1F, 0x0339, 0x02CB}, + {0x1F, 0x033A, 0x0208}, + {0x1F, 0x033B, 0x0109}, + {0x1F, 0x0418, 0x0380}, + {0x1F, 0x0420, 0xFF10}, + {0x1F, 0x0421, 0x4033}, + {0x1F, 0x0422, 0x0800}, + {0x1F, 0x0423, 0x0002}, + {0x1F, 0x0484, 0x0003}, + {0x1F, 0x055D, 0x0008}, + {0x1F, 0x042B, 0x0018}, + {0x1F, 0x082D, 0x120F}, + {0x1F, 0x0888, 0x0438}, + {0x1F, 0x0824, 0x09E0}, + {0x1F, 0x0883, 0x5146}, + {0x1F, 0x08BE, 0x02A1}, + {0x1F, 0x0822, 0x11E1}, + {0x1F, 0x056A, 0x5F40}, + {0x1F, 0x08C1, 0x0900}, + {0x1F, 0x08FC, 0x4091}, + {0x1F, 0x08F9, 0x1F11}, + {0x1F, 0x084F, 0x290C}, + {0x1F, 0x0850, 0x3D33}, + {0x1F, 0x018C, 0x0001}, + {0x1F, 0x001F, 0x4000}, + {0x1F, 0x0573, 0x0001}, + {0x1F, 0x056A, 0x5F41}, +}; + static int dp83tg720_read_straps(struct phy_device *phydev) { struct DP83TG720_private *DP83TG720 = phydev->priv; @@ -127,6 +343,55 @@ static int dp83tg720_read_straps(struct phy_device *phydev) return 0; }; +static int dp83tg720_reset(struct phy_device *phydev, bool hw_reset) +{ + int ret; + + if (hw_reset) + ret = phy_write_mmd(phydev, MMD1F, DP83TG720_PHY_RESET_CTRL, + DP83TG720_HW_RESET); + else + ret = phy_write_mmd(phydev, MMD1F, DP83TG720_PHY_RESET_CTRL, + DP83TG720_SW_RESET); + if (ret) + return ret; + + mdelay(100); + + return 0; +} + +static int dp83tg720_phy_reset(struct phy_device *phydev) +{ + int ret; + + ret = dp83tg720_reset(phydev, false); + if (ret) + return ret; + + ret = dp83tg720_read_straps(phydev); + if (ret) + return ret; + + return 0; +} + +static int DP83TG720_write_seq(struct phy_device *phydev, + const struct DP83TG720_init_reg *init_data, int size) +{ + int ret; + int i; + + for (i = 0; i < size; i++) { + ret = phy_write_mmd(phydev, init_data[i].MMD, init_data[i].reg, + init_data[i].val); + if (ret) + return ret; + } + + return 0; +} + /** * dp83tg720_cable_test_start - Start the cable test for the DP83TG720 PHY. * @phydev: Pointer to the phy_device structure. @@ -362,6 +627,61 @@ static int dp83tg720_config_rgmii_delay(struct phy_device *phydev) rgmii_delay); } +static int dp83tg720_chip_init(struct phy_device *phydev) +{ + struct DP83TG720_private *DP83TG720 = phydev->priv; + int ret; + + ret = dp83tg720_reset(phydev, true); + if (ret) + return ret; + + phydev->autoneg = AUTONEG_DISABLE; + phydev->speed = SPEED_1000; + phydev->duplex = DUPLEX_FULL; + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported); + + switch (DP83TG720->chip) { + case DP83TG720_CS1_1: + if (DP83TG720->is_master) + ret = DP83TG720_write_seq(phydev, DP83TG720_cs1_1_master_init, + ARRAY_SIZE(DP83TG720_cs1_1_master_init)); + else + ret = DP83TG720_write_seq(phydev, DP83TG720_cs1_1_slave_init, + ARRAY_SIZE(DP83TG720_cs1_1_slave_init)); + + ret = dp83tg720_reset(phydev, false); + + return 1; + case DP83TG721_CS1: + if (DP83TG720->is_master) + ret = DP83TG720_write_seq(phydev, DP83TG721_cs1_master_init, + ARRAY_SIZE(DP83TG721_cs1_master_init)); + else + ret = DP83TG720_write_seq(phydev, DP83TG721_cs1_slave_init, + ARRAY_SIZE(DP83TG721_cs1_slave_init)); + + ret = dp83tg720_reset(phydev, false); + + return 1; + default: + return -EINVAL; + }; + + if (ret) + return ret; + + /* Enable the PHY */ + ret = phy_write_mmd(phydev, MMD1F, DP83TG720_LPS_CFG3, DP83TG720_LPS_CFG3_PWR_MODE_0); + if (ret) + return ret; + + mdelay(10); + + /* Do a software reset to restart the PHY with the updated values */ + return dp83tg720_reset(phydev, false); +} + static int dp83tg720_config_init(struct phy_device *phydev) { int value, ret; @@ -369,9 +689,7 @@ static int dp83tg720_config_init(struct phy_device *phydev) /* Software Restart is not enough to recover from a link failure. * Using Hardware Reset instead. */ - ret = phy_write(phydev, DP83TG720_PHY_RESET, DP83TG720_HW_RESET); - if (ret) - return ret; + ret = dp83tg720_chip_init(phydev); /* Wait until MDC can be used again. * The wait value of one 1ms is documented in "DP83TG720-Q1 1000BASE-T1 @@ -447,6 +765,7 @@ static int dp83tg720_probe(struct phy_device *phydev) PHY_ID_MATCH_EXACT(_id), \ .name = (_name), \ .probe = dp83tg720_probe, \ + .soft_reset = dp83tg720_phy_reset, \ .flags = PHY_POLL_CABLE_TEST, \ .config_aneg = dp83tg720_config_aneg, \ .read_status = dp83tg720_read_status, \ @@ -473,32 +792,6 @@ static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = { }; MODULE_DEVICE_TABLE(mdio, dp83tg720_tbl); -// static struct phy_driver dp83tg720_driver[] = { -// { -// PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID), -// .name = "TI DP83TG720", - -// .flags = PHY_POLL_CABLE_TEST, -// .config_aneg = dp83tg720_config_aneg, -// .read_status = dp83tg720_read_status, -// .get_features = genphy_c45_pma_read_ext_abilities, -// .config_init = dp83tg720_config_init, -// .get_sqi = dp83tg720_get_sqi, -// .get_sqi_max = dp83tg720_get_sqi_max, -// .cable_test_start = dp83tg720_cable_test_start, -// .cable_test_get_status = dp83tg720_cable_test_get_status, - -// .suspend = genphy_suspend, -// .resume = genphy_resume, -// } }; -// module_phy_driver(dp83tg720_driver); - -// static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = { -// { PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID) }, -// { } -// }; -// MODULE_DEVICE_TABLE(mdio, dp83tg720_tbl); - MODULE_DESCRIPTION("Texas Instruments DP83TG720 PHY driver"); MODULE_AUTHOR("Oleksij Rempel "); MODULE_LICENSE("GPL"); From patchwork Thu Sep 19 21:01:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Alvaro (Al-vuh-roe) Reyes" X-Patchwork-Id: 13807993 X-Patchwork-Delegate: kuba@kernel.org Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E676315099B for ; Thu, 19 Sep 2024 21:01:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 19 Sep 2024 16:01:36 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 19 Sep 2024 16:01:35 -0500 Received: from Linux-002.dhcp.ti.com (linux-002.dhcp.ti.com [10.188.34.182]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48JL1OC9098001; Thu, 19 Sep 2024 16:01:35 -0500 From: "Alvaro (Al-vuh-roe) Reyes" To: CC: , , , , , , , , , , , "Alvaro (Al-vuh-roe) Reyes" Subject: [PATCH 5/5] net: phy: dp83tg720: fixed Linux coding standards issues Date: Thu, 19 Sep 2024 14:01:19 -0700 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-Patchwork-Delegate: kuba@kernel.org Driver patches was checked against the linux coding standards using scripts/checkpatch.pl. This patch meets the standards checked by the script. Signed-off-by: Alvaro (Al-vuh-roe) Reyes --- drivers/net/phy/dp83tg720.c | 71 +++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 35 deletions(-) diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c index 4df6713c51e3..1135dcf5efe6 100644 --- a/drivers/net/phy/dp83tg720.c +++ b/drivers/net/phy/dp83tg720.c @@ -10,7 +10,7 @@ #include "open_alliance_helpers.h" -#define DP83TG720_CS_1_1_PHY_ID 0x2000a284 +#define DP83TG720_CS_1_1_PHY_ID 0x2000a284 #define DP83TG721_CS_1_0_PHY_ID 0x2000a290 #define MMD1F 0x1f #define MMD1 0x1 @@ -349,10 +349,10 @@ static int dp83tg720_reset(struct phy_device *phydev, bool hw_reset) if (hw_reset) ret = phy_write_mmd(phydev, MMD1F, DP83TG720_PHY_RESET_CTRL, - DP83TG720_HW_RESET); + DP83TG720_HW_RESET); else ret = phy_write_mmd(phydev, MMD1F, DP83TG720_PHY_RESET_CTRL, - DP83TG720_SW_RESET); + DP83TG720_SW_RESET); if (ret) return ret; @@ -377,16 +377,17 @@ static int dp83tg720_phy_reset(struct phy_device *phydev) } static int DP83TG720_write_seq(struct phy_device *phydev, - const struct DP83TG720_init_reg *init_data, int size) + const struct DP83TG720_init_reg *init_data, + int size) { int ret; int i; for (i = 0; i < size; i++) { - ret = phy_write_mmd(phydev, init_data[i].MMD, init_data[i].reg, - init_data[i].val); - if (ret) - return ret; + ret = phy_write_mmd(phydev, init_data[i].MMD, init_data[i].reg, + init_data[i].val); + if (ret) + return ret; } return 0; @@ -635,20 +636,20 @@ static int dp83tg720_chip_init(struct phy_device *phydev) ret = dp83tg720_reset(phydev, true); if (ret) return ret; - + phydev->autoneg = AUTONEG_DISABLE; - phydev->speed = SPEED_1000; + phydev->speed = SPEED_1000; phydev->duplex = DUPLEX_FULL; - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported); switch (DP83TG720->chip) { case DP83TG720_CS1_1: if (DP83TG720->is_master) ret = DP83TG720_write_seq(phydev, DP83TG720_cs1_1_master_init, - ARRAY_SIZE(DP83TG720_cs1_1_master_init)); + ARRAY_SIZE(DP83TG720_cs1_1_master_init)); else ret = DP83TG720_write_seq(phydev, DP83TG720_cs1_1_slave_init, - ARRAY_SIZE(DP83TG720_cs1_1_slave_init)); + ARRAY_SIZE(DP83TG720_cs1_1_slave_init)); ret = dp83tg720_reset(phydev, false); @@ -656,10 +657,10 @@ static int dp83tg720_chip_init(struct phy_device *phydev) case DP83TG721_CS1: if (DP83TG720->is_master) ret = DP83TG720_write_seq(phydev, DP83TG721_cs1_master_init, - ARRAY_SIZE(DP83TG721_cs1_master_init)); + ARRAY_SIZE(DP83TG721_cs1_master_init)); else ret = DP83TG720_write_seq(phydev, DP83TG721_cs1_slave_init, - ARRAY_SIZE(DP83TG721_cs1_slave_init)); + ARRAY_SIZE(DP83TG721_cs1_slave_init)); ret = dp83tg720_reset(phydev, false); @@ -736,7 +737,7 @@ static int dp83tg720_probe(struct phy_device *phydev) int ret; DP83TG720 = devm_kzalloc(&phydev->mdio.dev, sizeof(*DP83TG720), - GFP_KERNEL); + GFP_KERNEL); if (!DP83TG720) return -ENOMEM; @@ -760,33 +761,33 @@ static int dp83tg720_probe(struct phy_device *phydev) return dp83tg720_config_init(phydev); } -#define DP83TG720_PHY_DRIVER(_id, _name) \ -{ \ - PHY_ID_MATCH_EXACT(_id), \ - .name = (_name), \ - .probe = dp83tg720_probe, \ - .soft_reset = dp83tg720_phy_reset, \ - .flags = PHY_POLL_CABLE_TEST, \ - .config_aneg = dp83tg720_config_aneg, \ - .read_status = dp83tg720_read_status, \ - .get_features = genphy_c45_pma_read_ext_abilities, \ - .config_init = dp83tg720_config_init, \ - .get_sqi = dp83tg720_get_sqi, \ - .get_sqi_max = dp83tg720_get_sqi_max, \ - .cable_test_start = dp83tg720_cable_test_start, \ - .cable_test_get_status = dp83tg720_cable_test_get_status, \ - .suspend = genphy_suspend, \ - .resume = genphy_resume, \ +#define DP83TG720_PHY_DRIVER(_id, _name) \ +{ \ + PHY_ID_MATCH_EXACT(_id), \ + .name = (_name), \ + .probe = dp83tg720_probe, \ + .soft_reset = dp83tg720_phy_reset, \ + .flags = PHY_POLL_CABLE_TEST, \ + .config_aneg = dp83tg720_config_aneg, \ + .read_status = dp83tg720_read_status, \ + .get_features = genphy_c45_pma_read_ext_abilities, \ + .config_init = dp83tg720_config_init, \ + .get_sqi = dp83tg720_get_sqi, \ + .get_sqi_max = dp83tg720_get_sqi_max, \ + .cable_test_start = dp83tg720_cable_test_start, \ + .cable_test_get_status = dp83tg720_cable_test_get_status, \ + .suspend = genphy_suspend, \ + .resume = genphy_resume, \ } static struct phy_driver dp83tg720_driver[] = { - DP83TG720_PHY_DRIVER(DP83TG720_CS_1_1_PHY_ID, "TI DP83TG720CS1.1"), + DP83TG720_PHY_DRIVER(DP83TG720_CS_1_1_PHY_ID, "TI DP83TG720CS1.1"), DP83TG720_PHY_DRIVER(DP83TG721_CS_1_0_PHY_ID, "TI DP83TG721CS1.0"), }; module_phy_driver(dp83tg720_driver); static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = { - { PHY_ID_MATCH_EXACT(DP83TG720_CS_1_1_PHY_ID) }, + { PHY_ID_MATCH_EXACT(DP83TG720_CS_1_1_PHY_ID) }, { PHY_ID_MATCH_EXACT(DP83TG721_CS_1_0_PHY_ID) }, { }, };