From patchwork Fri Sep 20 13:41:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Sun X-Patchwork-Id: 13808524 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E33FC17B506; Fri, 20 Sep 2024 13:42:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726839747; cv=none; b=HxPd8wPuNOcpgltF3ECyt6AxCX+m6tC736bg6bvv+fpsdIoFZTdMD5rkJey35GZwnjJgd+/4ZQbutFTKy6NWx2n7p1y9cjLmn21gW/0ZzMb4iESsW/oDcFP6VjmI6fPZRjMpyzFfUijukkhaK3fM7ebC1VKkRMXBYzxWYuFN/pY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726839747; c=relaxed/simple; bh=48kR4307+f0xawXLPR/6nuOZKLDb6FFxmzd1qOUv3VY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Rngd+eSYMLK56+NVf4i9xXMzXOMIlfQvNIrr1ZKg2Lxapdc+oh5RHxP7vLjze7Z1zTaJ4Orei5r/hbQZSc+1mbtmGXWWkoMiYXdMovpSfXsY5+4pvhM23wu0vr1Ya5Df1eIE4T5H44q2VQkH3kaAPSiJeolFySiuC/2HKp7AVw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=SQeeA4li; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SQeeA4li" X-UUID: 2909d714775611ef8b96093e013ec31c-20240920 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6fNkpx8yInEDktvhahzTbJz3OXq0KQfG32J2/mZQM2U=; b=SQeeA4liJEFPxXrGjGQc87dicEfVsM0gjxEP+7afgrSFIhK6XfuIvnPn/6DSZmFoFE/LoON31ovP0xXjEdO/5ynycyYnuTmkpX72hVAaLwTKh//PqUXoqcfM+LIMDhr/obOcdt/069gF9n2qFhcjxCCuw8nFPBz/XycJVphKWlc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:107b5ac6-773a-4119-9fc0-c632b102dedb,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:8a6bff17-b42d-49a6-94d2-a75fa0df01d2,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 2909d714775611ef8b96093e013ec31c-20240920 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2084515162; Fri, 20 Sep 2024 21:42:21 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 20 Sep 2024 21:42:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 20 Sep 2024 21:42:19 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , "Srinivas Kandagatla" CC: , , , , , Pablo Sun Subject: [PATCH 1/5] arm64: dts: mediatek: mt8188: Fix wrong clock provider in MFG1 power domain Date: Fri, 20 Sep 2024 21:41:07 +0800 Message-ID: <20240920134111.19744-2-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240920134111.19744-1-pablo.sun@mediatek.com> References: <20240920134111.19744-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.516100-8.000000 X-TMASE-MatchedRID: +rnZyzwxyNIPRVepDWIjx/fLKp/JCt7hXW2lZgTs6mzfUZT83lbkEPBY Ro06eVj3qeTGwaWK7dyAMuqetGVetnyef22ep6XYxlblqLlYqXLetNGkEDQrI+B5LykgR4DXTWc vApzCWVLvAbW4qQmY4Gn7CIB1iw88YT7jkPs65/Si0djfdRK1jzeJDevMXv/zyuuRMrTTzW+Oh+ wyNBrFXDJiNuKohDcKzKSG3JdyKAPqtV2AGMNPaiHWPYzouJUy X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.516100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: D98EB045355BC250620669345B381D34A8C31BFC89CAAB7290297AD83953F32E2000:8 X-MTK: N The clock index "CLK_APMIXED_MFGPLL" belongs to the "apmixedsys" provider, so fix the index. In addition, add a "mfg1" label so following commits could set domain-supply for MFG1 power domain. Fixes: b8369604050b ("UPSTREAM: arm64: dts: mediatek: mt8188: Add support for SoC power domains") Signed-off-by: Pablo Sun --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index cd27966d2e3c..02a5bb4dbd1f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -956,9 +956,9 @@ mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { #size-cells = <0>; #power-domain-cells = <1>; - power-domain@MT8188_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 { reg = ; - clocks = <&topckgen CLK_APMIXED_MFGPLL>, + clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, <&topckgen CLK_TOP_MFG_CORE_TMP>; clock-names = "mfg", "alt"; mediatek,infracfg = <&infracfg_ao>; From patchwork Fri Sep 20 13:41:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Sun X-Patchwork-Id: 13808526 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B19C817BEC5; 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Fri, 20 Sep 2024 21:42:23 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 20 Sep 2024 21:42:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 20 Sep 2024 21:42:21 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , "Srinivas Kandagatla" CC: , , , , , Pablo Sun Subject: [PATCH 2/5] clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmp Date: Fri, 20 Sep 2024 21:41:08 +0800 Message-ID: <20240920134111.19744-3-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240920134111.19744-1-pablo.sun@mediatek.com> References: <20240920134111.19744-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.220100-8.000000 X-TMASE-MatchedRID: 6mUaupESUicX/DgtOsKbJEKcYi5Qw/RVYU4M4UEhdYoOUs4CTUgKy6dy K1rXVA/F9tuSNsrGP8feAMGbXnKiN7UN8Yzp1vtfA9lly13c/gHt/okBLaEo+IWXGHd13QwAo8W MkQWv6iXBcIE78YqRWo6HM5rqDwqt4XgtCAUmrqUKYfTzGGy8aC9j0U24TSafOrFVoj5IqtJ8dr /u/DLEnwHOhuuQEdvLcdzPe3Qcn3bSiULcJKjUyoEDzLGQCF4vwZBgUyJVEbl6Fw8/PpTMRaVvm iAyeA2kc5MSfkiJFI5QBJtcKcOYfpRMZUCEHkRt X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.220100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: E9E4C39A28787342393ECA9258E7290EA1B256B30B3614CD06F8F7BD2D4C723A2000:8 X-MTK: N Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when setting mfgpll clock rate. If we keep the univpll parents from mfg_core_tmp, when setting GPU frequency to 390000000, the common clock framework would switch the parent to univpll, instead of setting mfgpll to 390000000: mfgpll 0 0 0 949999756 univpll 2 2 0 2340000000 univpll_d6 1 1 0 390000000 top_mfg_core_tmp 1 1 0 390000000 mfg_ck_fast_ref 1 1 0 390000000 mfgcfg_bg3d 1 1 0 390000000 This results in failures when subsequent devfreq operations need to switch to other frequencies. So remove univpll from the parent list. This solution is taken from commit 72d38ed720e9 ("clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents") Signed-off-by: Pablo Sun --- drivers/clk/mediatek/clk-mt8188-topckgen.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c index 2ccc8a1c98f9..74ee692ac613 100644 --- a/drivers/clk/mediatek/clk-mt8188-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c @@ -342,11 +342,14 @@ static const char * const dsp7_parents[] = { "univpll_d3" }; +/* + * MFG can be also parented to "univpll_d6" and "univpll_d7": + * these have been removed from the parents list to let us + * achieve GPU DVFS without any special clock handlers. + */ static const char * const mfg_core_tmp_parents[] = { "clk26m", "mainpll_d5_d2", - "univpll_d6", - "univpll_d7" }; static const char * const camtg_parents[] = { From patchwork Fri Sep 20 13:41:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Sun X-Patchwork-Id: 13808525 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1CDB17BB0F; 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Fri, 20 Sep 2024 21:42:23 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 20 Sep 2024 06:42:22 -0700 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 20 Sep 2024 21:42:22 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Srinivas Kandagatla CC: , , , , , Pablo Sun Subject: [PATCH 3/5] nvmem: mtk-efuse: Enable postprocess for mt8188 GPU speed binning Date: Fri, 20 Sep 2024 21:41:09 +0800 Message-ID: <20240920134111.19744-4-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240920134111.19744-1-pablo.sun@mediatek.com> References: <20240920134111.19744-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Similar to mt8186, the efuse data for mt8188's GPU speed binning requires post-process to convert the bit field format expected by the OPP table. Since mt8188 efuse is not compatible to mt8186, add a new compatible entry for mt8188 and enable postprocess. Signed-off-by: Pablo Sun --- drivers/nvmem/mtk-efuse.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/nvmem/mtk-efuse.c b/drivers/nvmem/mtk-efuse.c index 9caf04667341..4984145025bb 100644 --- a/drivers/nvmem/mtk-efuse.c +++ b/drivers/nvmem/mtk-efuse.c @@ -105,6 +105,10 @@ static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = { .uses_post_processing = true, }; +static const struct mtk_efuse_pdata mtk_mt8188_efuse_pdata = { + .uses_post_processing = true, +}; + static const struct mtk_efuse_pdata mtk_efuse_pdata = { .uses_post_processing = false, }; @@ -112,6 +116,7 @@ static const struct mtk_efuse_pdata mtk_efuse_pdata = { static const struct of_device_id mtk_efuse_of_match[] = { { .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata }, { .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata }, + { .compatible = "mediatek,mt8188-efuse", .data = &mtk_mt8188_efuse_pdata }, { .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata }, {/* sentinel */}, }; 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Fri, 20 Sep 2024 06:42:23 -0700 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 20 Sep 2024 21:42:23 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , Srinivas Kandagatla CC: , , , , , Pablo Sun Subject: [PATCH 4/5] arm64: dts: mediatek: mt8188: Add efuse for GPU speed binning Date: Fri, 20 Sep 2024 21:41:10 +0800 Message-ID: <20240920134111.19744-5-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240920134111.19744-1-pablo.sun@mediatek.com> References: <20240920134111.19744-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N The OPP table of mt8188 GPU contains duplicated frequencies for different speed bins. In order to support OPP table, we need to provide the speed bin info in the efuse data so the GPU driver could properly set the supported hardware speed bin. Signed-off-by: Pablo Sun --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 02a5bb4dbd1f..129edaf33704 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1752,6 +1752,11 @@ efuse: efuse@11f20000 { lvts_efuse_data1: lvts1-calib@1ac { reg = <0x1ac 0x40>; }; + + gpu_speedbin: gpu-speedbin@580 { + reg = <0x581 0x1>; + bits = <0 3>; + }; }; gpu: gpu@13000000 { @@ -1763,6 +1768,8 @@ gpu: gpu@13000000 { , ; interrupt-names = "job", "mmu", "gpu"; + nvmem-cells = <&gpu_speedbin>; + nvmem-cell-names = "speed-bin"; operating-points-v2 = <&gpu_opp_table>; power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, <&spm MT8188_POWER_DOMAIN_MFG3>, From patchwork Fri Sep 20 13:41:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pablo Sun X-Patchwork-Id: 13808528 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A41AE17BB0F; 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Fri, 20 Sep 2024 21:42:28 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 20 Sep 2024 21:42:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 20 Sep 2024 21:42:26 +0800 From: Pablo Sun To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd , "Srinivas Kandagatla" CC: , , , , , Pablo Sun Subject: [PATCH 5/5] arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU Date: Fri, 20 Sep 2024 21:41:11 +0800 Message-ID: <20240920134111.19744-6-pablo.sun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240920134111.19744-1-pablo.sun@mediatek.com> References: <20240920134111.19744-1-pablo.sun@mediatek.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.132500-8.000000 X-TMASE-MatchedRID: yKCfkewtMJNcgzmua3ALxodlc1JaOB1TIfZjRfGTydjCJQ8asLA2FymF OYJJbPqpf146W0iUu2vednYgFc6jdmoOvZKQqN7ksyw+ZJnFumR9LQinZ4QefCP/VFuTOXUTKYO cjnHaFYKOhzOa6g8KrUNZLx701ylLZNlabEp+beNgV30RsrzFkpsG9tZP2PDMCxXIK6ID3jMoKN LuxkrzxPJboJY9QimDkaMcawjb1snfsU0wOw8Q+MGQYFMiVRG5ehcPPz6UzEWlb5ogMngNpHOTE n5IiRSOady5RJQR05c= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.132500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 1205DADD2A2EEDD3CF06167194CE62D4F6C98BED4D4CE9704DCD6AE8E579CEAD2000:8 X-MTK: N Configure GPU regulator supplies and enable GPU for GENIO 700 EVK. The GPU in MT8390 & MT8188 has two power inputs: "DVDD_GPU" and "DVDD_SRAM_GPU". In Genio 700 EVK, DVDD_GPU is supplied by mt6359_vproc2_buck_reg, and DVDD_SRAM_GPU is supplied by mt6359_vsram_others_ldo_reg. According to section 5.2 "Recommended Operating Conditions" in MT8390 IoT Application Processor Datasheet v1.9, The recommended operating voltage ranges are: - DVDD_GPU: min 0.55V, max 0.86V, typical 0.75V - DVDD_SRAM_GPU: min 0.71V, max 0.92V, typical 0.85V In this commit, we set DVDD_SRAM_GPU to typical 0.85V. It is possbile to couple it to the DVDD_GPU in future patches. Signed-off-by: Pablo Sun --- .../dts/mediatek/mt8390-genio-700-evk.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts index 1474bef7e754..a1d6f4cd4e5f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -190,6 +190,11 @@ usb_p2_vbus: regulator-10 { }; }; +&gpu { + mali-supply = <&mt6359_vproc2_buck_reg>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -253,6 +258,14 @@ &i2c6 { status = "okay"; }; +&mfg0 { + domain-supply = <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + &mmc0 { status = "okay"; pinctrl-names = "default", "state_uhs"; @@ -314,6 +327,11 @@ &mt6359_vpa_buck_reg { regulator-max-microvolt = <3100000>; }; +&mt6359_vproc2_buck_reg { + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <860000>; +}; + &mt6359_vpu_buck_reg { regulator-always-on; }; @@ -326,6 +344,12 @@ &mt6359_vsim1_ldo_reg { regulator-enable-ramp-delay = <480>; }; +/* for GPU SRAM */ +&mt6359_vsram_others_ldo_reg { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; +}; + &mt6359_vufs_ldo_reg { regulator-always-on; };