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Fri, 20 Sep 2024 15:34:51 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC 01/13] cxl: allow a type-2 device not to have memory device registers Date: Fri, 20 Sep 2024 15:34:34 -0700 Message-ID: <20240920223446.1908673-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920223446.1908673-1-zhiw@nvidia.com> References: <20240920223446.1908673-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|DM6PR12MB4138:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ea9ad7c-e11e-48ce-84d3-08dcd9c47a4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: 3XUeIwtZp6c8mDklwZSH8NSgId07HnE86ZMlV10zXgtEdFv92LqHT2w6JE4KWVD/efZ4Puk9zqgV2FdGlatxsWH57Wrygo0xeMYXnILaAyFIfPCJRLhGv36ud9eu8NEXV3CC+ClR0V80kW+pDcjcN6LJn1nNU5iV39aGnvhVDA2Fw9kpBy3YpLLtZ8QXwf/H7bXdQr1KrgU34X5I6a0E4SGU26JhPWCeouXXui19CXifVLN3FDJz3kweumIFiorIQ/DMZhW2MJrYBn9aIn9uUzitR5ED0U8kLz8xfr8YQDn5qCJPFWXZVDT0kOwO5S0avcsnb7eE7SzTUKIsYwCpInd8ZdKkjMTwMCIkShrfjUX/Y3NEXVry7xqryr/ZG46Sz8YVy8sDq2E4BF/x6kXBhAlAuuVYnCkDWl719QqQOSQFpo/UxP3E1fYilOGcWL3ga8BoHnwCS3oRhh6FsHH92g5mL8qo/NMTNq9crBS6CqVmuctlgXjmTW2pRaWyvO0x+WI7zd29+6q9YYt0PKLE0kxFk+Tqj6piXfpKcG6srmjcjHA7FYoep9jW6ByC+AadVtdX/wKJiVOrglOJR48pY8tx7dL+ZQnGNM4BnealeY+IKM8F+JMkuPjbbZCFsKRzTXoXq/FsXzw/T6QUbXYFqAKV+Olj+uRAegn4eRg197KQOeHZYs4/DXwuBLv1QSiRi3sqz4KHYR1Fo55you1YOW2T99+zeX2fbnpfF9Qmpu95BLYsMQ6SqRNQnlfh7f3JQljQ3Fn+74dt6CIiSqf+Zs7Y+YjnaQfy/8JU0YlnTLMlKGPmANQkqFZ2vRg/4FA5lk8ZTZXAI3HjiAbxEh4eloAcWi/ZSAeDVNCX07EVcPVkPmEmRkY6wi+BeLPmmX2+C4oP7hVYdbAxKcroTVl46oQ2y8h83vK8PHHg9xOq2iNvLK3DzVNRA1HJ02Zuvr4KJ2z3Ah6hjV6SaWuDh3+6+4VpxuOY8Ke1uryWPnZi/WbJSk4aKZfuNZQxePYcfiCAUlq2poBAGD+2mFnU0vW13HO3929AYHPTHqElKWaCJMQMz7PrRXT8N87A/nDVS3b3GhoCUpCcq37RqUYEZFmvzypccdYIeMN5cY/A55W1DRd8cw9XlGJDfvcSvLJIQeYpiN5XtlVkyWWvWeD/tfUTKu8Mdk/Ul8t1K2mr/1aiGTPRHo6S6jqe88XyRB6RDVb1wdPhGzsIhRE2p7/S/qrjNz12IfUpI+tJEQiet/085/KpqQ6Mf2TlqLjJLL7FIu8c7wgd/fmk6huEi+uQvtV0pTf03s7OZmHR9PQHANoMfjVv+T3auFgggIO+UHJHUACIUi1hHiBynMYhX2vktk6nnPdlZyiTVzU4bpLJUYCce0uza9QUuN7r4F/xrq7hA/Bs X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:06.7613 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ea9ad7c-e11e-48ce-84d3-08dcd9c47a4e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4138 CXL memory device registers provide additional information about device memory and advanced control interface for type-3 device. However, it is not mandatory for a type-2 device. A type-2 device can have HDMs but not CXL memory device registers. Allow a type-2 device not to hanve memory device register when probing CXL registers. Signed-off-by: Zhi Wang --- drivers/cxl/pci.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index e00ce7f4d0f9..3fbee31995f1 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -529,13 +529,13 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) int rc; rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, - cxlds->capabilities); - if (rc) - return rc; - - rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); - if (rc) - return rc; + cxlds->capabilities); + if (!rc) { + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); + if (rc) + dev_dbg(&pdev->dev, + "Failed to map device registers.\n"); + } rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &cxlds->reg_map, cxlds->capabilities); From patchwork Fri Sep 20 22:34:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhi Wang X-Patchwork-Id: 13808731 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2046.outbound.protection.outlook.com [40.107.223.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B868F178383; 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Fri, 20 Sep 2024 15:34:54 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 20 Sep 2024 15:34:53 -0700 Received: from inno-linux.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 20 Sep 2024 15:34:52 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC 02/13] cxl: introduce cxl_get_hdm_info() Date: Fri, 20 Sep 2024 15:34:35 -0700 Message-ID: <20240920223446.1908673-3-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920223446.1908673-1-zhiw@nvidia.com> References: <20240920223446.1908673-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|PH8PR12MB6817:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ea38c5f-0a95-4e0f-fd43-08dcd9c47b41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:08.3726 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ea38c5f-0a95-4e0f-fd43-08dcd9c47b41 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6817 CXL core has the information of what CXL register groups a device has. When initializing the device, the CXL core probes the register groups and saves the information. The probing sequence is quite complicated. vfio-cxl requires the HDM register information to emualte the HDM decoder registers. Introduce cxl_get_hdm_info() for vfio-cxl to leverage the HDM register information in the CXL core. Thus, it doesn't need to implement its own probing sequence. Signed-off-by: Zhi Wang --- drivers/cxl/core/pci.c | 28 ++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 +++ include/linux/cxl_accel_mem.h | 2 ++ 3 files changed, 33 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a663e7566c48..7b6c2b6211b3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -502,6 +502,34 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, } EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, + u64 *hdm_reg_offset, u64 *hdm_reg_size) +{ + struct pci_dev *pdev = to_pci_dev(cxlds->dev); + int d = cxlds->cxl_dvsec; + u16 cap; + int rc; + + if (!cxlds->reg_map.component_map.hdm_decoder.valid) { + *hdm_reg_offset = *hdm_reg_size = 0; + } else { + struct cxl_component_reg_map *map = + &cxlds->reg_map.component_map; + + *hdm_reg_offset = map->hdm_decoder.offset; + *hdm_reg_size = map->hdm_decoder.size; + } + + rc = pci_read_config_word(pdev, + d + CXL_DVSEC_CAP_OFFSET, &cap); + if (rc) + return rc; + + *hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_get_hdm_info, CXL); + #define CXL_DOE_TABLE_ACCESS_REQ_CODE 0x000000ff #define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ 0 #define CXL_DOE_TABLE_ACCESS_TABLE_TYPE 0x0000ff00 diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 4da07727ab9c..8d4458f7e45b 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -129,4 +129,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); + +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, + u64 *hdm_reg_offset, u64 *hdm_reg_size); #endif /* __CXL_PCI_H__ */ diff --git a/include/linux/cxl_accel_mem.h b/include/linux/cxl_accel_mem.h index 5d715eea6e91..db4182fc1936 100644 --- a/include/linux/cxl_accel_mem.h +++ b/include/linux/cxl_accel_mem.h @@ -55,4 +55,6 @@ struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd, int cxl_region_detach(struct cxl_endpoint_decoder *cxled); int cxl_accel_get_region_params(struct cxl_region *region, resource_size_t *start, resource_size_t *end); +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, + u64 *hdm_reg_offset, u64 *hdm_reg_size); #endif From patchwork Fri Sep 20 22:34:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhi Wang X-Patchwork-Id: 13808733 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2058.outbound.protection.outlook.com [40.107.237.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5278918C93D; Fri, 20 Sep 2024 22:35:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726871716; cv=fail; b=OnmBRu9mwtNhbVmYcTZdldkbYiarggwr4hkjDZCR3ZAy9TWG8S4pqg88PjIK5bTsuXnAOIkU0hajX2Ur+FlksnM9KuEwndbW3sO6pV2LvodUi3uLBl9NjqDY9tXUFSFsVaUYahHvv10X/TfX67tx9RWAgdbBXHZ90l78uG3lwhI= ARC-Message-Signature: i=2; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:09.7008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b7835c5-a439-446d-0c97-08dcd9c47c0f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4396 CXL core has the information of what CXL register groups a device has.When initializing the device, the CXL core probes the register groups and saves the information. The probing sequence is quite complicated. vfio-cxl needs to handle the CXL MMIO BAR specially. E.g. emulate the HDM decoder register inside the component registers. Thus it requires to know the offset of the CXL component register to locate the PCI BAR where the component register sits. Introduce cxl_find_comp_regblock_offset() for vfio-cxl to leverage the register information in the CXL core. Thus, it doesn't need to implement its own probing sequence. Signed-off-by: Zhi Wang --- drivers/cxl/core/regs.c | 22 ++++++++++++++++++++++ drivers/cxl/cxl.h | 1 + include/linux/cxl_accel_mem.h | 1 + 3 files changed, 24 insertions(+) diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 9d218ebe180d..7db3c8fcd66f 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -364,6 +364,28 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL); +/** + * cxl_find_comp_regblock_offset() - Locate the offset of component + * register blocks + * @pdev: The CXL PCI device to enumerate. + * @offset: Enumeration output, clobbered on error + * + * Return: 0 if register block enumerated, negative error code otherwise + */ +int cxl_find_comp_regblock_offset(struct pci_dev *pdev, u64 *offset) +{ + struct cxl_register_map map; + int ret; + + ret = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map); + if (ret) + return ret; + + *offset = map.resource; + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_find_comp_regblock_offset, CXL); + /** * cxl_count_regblock() - Count instances of a given regblock type. * @pdev: The CXL PCI device to enumerate. diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 5e2b5b3e8f38..33dfdc278b47 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -300,6 +300,7 @@ int cxl_find_regblock_instance(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map, int index); int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map); +int cxl_find_comp_regblock_offset(struct pci_dev *pdev, u64 *offset); int cxl_setup_regs(struct cxl_register_map *map, uint8_t caps); struct cxl_dport; resource_size_t cxl_rcd_component_reg_phys(struct device *dev, diff --git a/include/linux/cxl_accel_mem.h b/include/linux/cxl_accel_mem.h index db4182fc1936..6f585aae7eb6 100644 --- a/include/linux/cxl_accel_mem.h +++ b/include/linux/cxl_accel_mem.h @@ -57,4 +57,5 @@ int cxl_accel_get_region_params(struct cxl_region *region, resource_size_t *start, resource_size_t *end); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:10.0895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75265c47-9c5b-484d-8164-08dcd9c47c51 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6701 In VFIO, common functions that used by VFIO variant drivers are managed in a set of "core" functions. E.g. the vfio-pci-core provides the common functions used by VFIO variant drviers to support PCI device passhthrough. Although the CXL type-2 device has a PCI-compatible interface for device configuration and programming, they still needs special handlings when initialize the device: - Probing the CXL DVSECs in the configuration. - Probing the CXL register groups implemented by the device. - Configuring the CXL device state required by the kernel CXL core. - Create the CXL region. - Special handlings of the CXL MMIO BAR. Introduce vfio-cxl core predules to hold all the common functions used by VFIO variant drivers to support CXL device passthrough. Signed-off-by: Zhi Wang --- drivers/vfio/pci/Kconfig | 4 + drivers/vfio/pci/Makefile | 3 + drivers/vfio/pci/vfio_cxl_core.c | 264 +++++++++++++++++++++++++++++++ include/linux/vfio_pci_core.h | 37 +++++ 4 files changed, 308 insertions(+) create mode 100644 drivers/vfio/pci/vfio_cxl_core.c diff --git a/drivers/vfio/pci/Kconfig b/drivers/vfio/pci/Kconfig index bf50ffa10bde..2196e79b132b 100644 --- a/drivers/vfio/pci/Kconfig +++ b/drivers/vfio/pci/Kconfig @@ -7,6 +7,10 @@ config VFIO_PCI_CORE select VFIO_VIRQFD select IRQ_BYPASS_MANAGER +config VFIO_CXL_CORE + tristate + select VFIO_PCI_CORE + config VFIO_PCI_MMAP def_bool y if !S390 depends on VFIO_PCI_CORE diff --git a/drivers/vfio/pci/Makefile b/drivers/vfio/pci/Makefile index cf00c0a7e55c..b51221b94b0b 100644 --- a/drivers/vfio/pci/Makefile +++ b/drivers/vfio/pci/Makefile @@ -8,6 +8,9 @@ vfio-pci-y := vfio_pci.o vfio-pci-$(CONFIG_VFIO_PCI_IGD) += vfio_pci_igd.o obj-$(CONFIG_VFIO_PCI) += vfio-pci.o +vfio-cxl-core-y := vfio_cxl_core.o +obj-$(CONFIG_VFIO_CXL_CORE) += vfio-cxl-core.o + obj-$(CONFIG_MLX5_VFIO_PCI) += mlx5/ obj-$(CONFIG_HISI_ACC_VFIO_PCI) += hisilicon/ diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c new file mode 100644 index 000000000000..6a7859333f67 --- /dev/null +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vfio_pci_priv.h" + +#define DRIVER_AUTHOR "Zhi Wang " +#define DRIVER_DESC "core driver for VFIO based CXL devices" + +static int get_hpa_and_request_dpa(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + struct pci_dev *pdev = core_dev->pdev; + u64 max; + + cxl->cxlrd = cxl_get_hpa_freespace(cxl->endpoint, 1, + CXL_DECODER_F_RAM | + CXL_DECODER_F_TYPE2, + &max); + if (IS_ERR(cxl->cxlrd)) { + pci_err(pdev, "Fail to get HPA space.\n"); + return PTR_ERR(cxl->cxlrd); + } + + if (max < cxl->region.size) { + pci_err(pdev, "No enough free HPA space %llu < %llu\n", + max, cxl->region.size); + return -ENOSPC; + } + + cxl->cxled = cxl_request_dpa(cxl->endpoint, true, cxl->region.size, + cxl->region.size); + if (IS_ERR(cxl->cxled)) { + pci_err(pdev, "Fail to request DPA\n"); + return PTR_ERR(cxl->cxled); + } + + return 0; +} + +static int create_cxl_region(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + struct pci_dev *pdev = core_dev->pdev; + resource_size_t start, end; + int ret; + + ret = cxl_accel_request_resource(cxl->cxlds, true); + if (ret) { + pci_err(pdev, "Fail to request CXL resource\n"); + return ret; + } + + if (!cxl_await_media_ready(cxl->cxlds)) { + cxl_accel_set_media_ready(cxl->cxlds); + } else { + pci_err(pdev, "CXL media is not active\n"); + return ret; + } + + cxl->cxlmd = devm_cxl_add_memdev(&pdev->dev, cxl->cxlds); + if (IS_ERR(cxl->cxlmd)) { + pci_err(pdev, "Fail to create CXL memdev\n"); + return PTR_ERR(cxl->cxlmd); + } + + cxl->endpoint = cxl_acquire_endpoint(cxl->cxlmd); + if (IS_ERR(cxl->endpoint)) { + pci_err(pdev, "Fail to acquire CXL endpoint\n"); + return PTR_ERR(cxl->endpoint); + } + + ret = get_hpa_and_request_dpa(core_dev); + if (ret) + goto out; + + cxl->region.region = cxl_create_region(cxl->cxlrd, &cxl->cxled, 1); + if (IS_ERR(cxl->region.region)) { + ret = PTR_ERR(cxl->region.region); + pci_err(pdev, "Fail to create CXL region\n"); + cxl_dpa_free(cxl->cxled); + goto out; + } + + cxl_accel_get_region_params(cxl->region.region, &start, &end); + + cxl->region.addr = start; +out: + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); + return ret; +} + +/* Standard CXL-type 2 driver initialization sequence */ +static int enable_cxl(struct vfio_pci_core_device *core_dev, u16 dvsec) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + struct pci_dev *pdev = core_dev->pdev; + u32 count; + u64 offset, size; + int ret; + + cxl->cxlds = cxl_accel_state_create(&pdev->dev, cxl->caps); + if (IS_ERR(cxl->cxlds)) + return PTR_ERR(cxl->cxlds); + + cxl_accel_set_dvsec(cxl->cxlds, dvsec); + cxl_accel_set_serial(cxl->cxlds, pdev->dev.id); + + cxl_accel_set_resource(cxl->cxlds, cxl->dpa_res, CXL_ACCEL_RES_DPA); + cxl_accel_set_resource(cxl->cxlds, cxl->ram_res, CXL_ACCEL_RES_RAM); + + ret = cxl_pci_accel_setup_regs(pdev, cxl->cxlds); + if (ret) { + pci_err(pdev, "Fail to setup CXL accel regs\n"); + return ret; + } + + ret = cxl_get_hdm_info(cxl->cxlds, &count, &offset, &size); + if (ret) + return ret; + + if (!count || !size) { + pci_err(pdev, "Fail to find CXL HDM reg offset\n"); + return -ENODEV; + } + + cxl->hdm_count = count; + cxl->hdm_reg_offset = offset; + cxl->hdm_reg_size = size; + + return create_cxl_region(core_dev); +} + +static void disable_cxl(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + + if (cxl->region.region) + cxl_region_detach(cxl->cxled); + + if (cxl->cxled) + cxl_dpa_free(cxl->cxled); +} + +int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + struct pci_dev *pdev = core_dev->pdev; + u16 dvsec; + int ret; + + dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, + CXL_DVSEC_PCIE_DEVICE); + if (!dvsec) + return -ENODEV; + + if (!cxl->region.size) + return -EINVAL; + + ret = vfio_pci_core_enable(core_dev); + if (ret) + return ret; + + ret = enable_cxl(core_dev, dvsec); + if (ret) + goto err_enable_cxl_device; + + return 0; + +err_enable_cxl_device: + vfio_pci_core_disable(core_dev); + return ret; +} +EXPORT_SYMBOL(vfio_cxl_core_enable); + +void vfio_cxl_core_finish_enable(struct vfio_pci_core_device *core_dev) +{ + vfio_pci_core_finish_enable(core_dev); +} +EXPORT_SYMBOL(vfio_cxl_core_finish_enable); + +void vfio_cxl_core_close_device(struct vfio_device *vdev) +{ + struct vfio_pci_core_device *core_dev = + container_of(vdev, struct vfio_pci_core_device, vdev); + + disable_cxl(core_dev); + vfio_pci_core_close_device(vdev); +} +EXPORT_SYMBOL(vfio_cxl_core_close_device); + +/* + * Configure the resource required by the kernel CXL core: + * device DPA and device RAM size + */ +void vfio_cxl_core_set_resource(struct vfio_pci_core_device *core_dev, + struct resource res, + enum accel_resource type) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + + switch (type) { + case CXL_ACCEL_RES_DPA: + cxl->dpa_size = res.end - res.start + 1; + cxl->dpa_res = res; + break; + + case CXL_ACCEL_RES_RAM: + cxl->ram_res = res; + break; + + default: + WARN(1, "invalid resource type: %d\n", type); + break; + } +} +EXPORT_SYMBOL(vfio_cxl_core_set_resource); + +/* Configure the expected CXL region size to be created */ +void vfio_cxl_core_set_region_size(struct vfio_pci_core_device *core_dev, + u64 size) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + + if (WARN_ON(size > cxl->dpa_size)) + return; + + if (WARN_ON(cxl->region.region)) + return; + + cxl->region.size = size; +} +EXPORT_SYMBOL(vfio_cxl_core_set_region_size); + +/* Configure the driver cap required by the kernel CXL core */ +void vfio_cxl_core_set_driver_hdm_cap(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + + cxl->caps |= CXL_ACCEL_DRIVER_CAP_HDM; +} +EXPORT_SYMBOL(vfio_cxl_core_set_driver_hdm_cap); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_IMPORT_NS(CXL); diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index fbb472dd99b3..7762d4a3e825 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -15,6 +15,8 @@ #include #include #include +#include +#include #ifndef VFIO_PCI_CORE_H #define VFIO_PCI_CORE_H @@ -49,6 +51,31 @@ struct vfio_pci_region { u32 flags; }; +struct vfio_cxl_region { + u64 size; + u64 addr; + struct cxl_region *region; +}; + +struct vfio_cxl { + u8 caps; + u64 dpa_size; + + u32 hdm_count; + u64 hdm_reg_offset; + u64 hdm_reg_size; + + struct cxl_dev_state *cxlds; + struct cxl_memdev *cxlmd; + struct cxl_root_decoder *cxlrd; + struct cxl_port *endpoint; + struct cxl_endpoint_decoder *cxled; + struct resource dpa_res; + struct resource ram_res; + + struct vfio_cxl_region region; +}; + struct vfio_pci_core_device { struct vfio_device vdev; struct pci_dev *pdev; @@ -94,6 +121,7 @@ struct vfio_pci_core_device { struct vfio_pci_core_device *sriov_pf_core_dev; struct notifier_block nb; struct rw_semaphore memory_lock; + struct vfio_cxl cxl; }; /* Will be exported for vfio pci drivers usage */ @@ -159,4 +187,13 @@ VFIO_IOREAD_DECLARATION(32) VFIO_IOREAD_DECLARATION(64) #endif +int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev); +void vfio_cxl_core_finish_enable(struct vfio_pci_core_device *core_dev); +void vfio_cxl_core_close_device(struct vfio_device *vdev); +void vfio_cxl_core_set_resource(struct vfio_pci_core_device *core_dev, + struct resource res, + enum accel_resource type); +void vfio_cxl_core_set_region_size(struct vfio_pci_core_device *core_dev, + u64 size); +void vfio_cxl_core_set_driver_hdm_cap(struct vfio_pci_core_device *core_dev); #endif /* VFIO_PCI_CORE_H */ From patchwork Fri Sep 20 22:34:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhi Wang X-Patchwork-Id: 13808734 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2078.outbound.protection.outlook.com [40.107.237.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9445918CBFC; Fri, 20 Sep 2024 22:35:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.78 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:10.7737 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d31c9b6-f999-4728-714c-08dcd9c47cc3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8415 To directly access the device memory, a CXL region is required. Creating a CXL region requires to configure HDM decoders on the path to map the access of HPA level by level and evetually hit the DPA in the CXL topology. For the usersapce, e.g. QEMU, to access the CXL region, the region is required to be exposed via VFIO interfaces. Introduce a new VFIO device region and region ops to expose the created CXL region when initailize the device in the vfio-cxl-core. Introduce a new sub region type for the userspace to identify a CXL region. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_cxl_core.c | 140 ++++++++++++++++++++++++++++- drivers/vfio/pci/vfio_pci_config.c | 1 + include/linux/vfio_pci_core.h | 1 + include/uapi/linux/vfio.h | 3 + 4 files changed, 144 insertions(+), 1 deletion(-) diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c index 6a7859333f67..ffc15fd94b22 100644 --- a/drivers/vfio/pci/vfio_cxl_core.c +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -102,6 +102,13 @@ static int create_cxl_region(struct vfio_pci_core_device *core_dev) cxl_accel_get_region_params(cxl->region.region, &start, &end); cxl->region.addr = start; + cxl->region.vaddr = ioremap(start, end - start); + if (!cxl->region.addr) { + pci_err(pdev, "Fail to map CXL region\n"); + cxl_region_detach(cxl->cxled); + cxl_dpa_free(cxl->cxled); + goto out; + } out: cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); return ret; @@ -152,17 +159,135 @@ static void disable_cxl(struct vfio_pci_core_device *core_dev) { struct vfio_cxl *cxl = &core_dev->cxl; - if (cxl->region.region) + if (cxl->region.region) { + iounmap(cxl->region.vaddr); cxl_region_detach(cxl->cxled); + } if (cxl->cxled) cxl_dpa_free(cxl->cxled); } +static unsigned long vma_to_pfn(struct vm_area_struct *vma) +{ + struct vfio_pci_core_device *vdev = vma->vm_private_data; + struct vfio_cxl *cxl = &vdev->cxl; + u64 pgoff; + + pgoff = vma->vm_pgoff & + ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); + + return (cxl->region.addr >> PAGE_SHIFT) + pgoff; +} + +static vm_fault_t vfio_cxl_mmap_fault(struct vm_fault *vmf) +{ + struct vm_area_struct *vma = vmf->vma; + struct vfio_pci_core_device *vdev = vma->vm_private_data; + unsigned long pfn, pgoff = vmf->pgoff - vma->vm_pgoff; + unsigned long addr = vma->vm_start; + vm_fault_t ret = VM_FAULT_SIGBUS; + + pfn = vma_to_pfn(vma); + + down_read(&vdev->memory_lock); + + if (vdev->pm_runtime_engaged || !__vfio_pci_memory_enabled(vdev)) + goto out_unlock; + + ret = vmf_insert_pfn(vma, vmf->address, pfn + pgoff); + if (ret & VM_FAULT_ERROR) + goto out_unlock; + + for (; addr < vma->vm_end; addr += PAGE_SIZE, pfn++) { + if (addr == vmf->address) + continue; + + if (vmf_insert_pfn(vma, addr, pfn) & VM_FAULT_ERROR) + break; + } + +out_unlock: + up_read(&vdev->memory_lock); + + return ret; +} + +static const struct vm_operations_struct vfio_cxl_mmap_ops = { + .fault = vfio_cxl_mmap_fault, +}; + +static int vfio_cxl_region_mmap(struct vfio_pci_core_device *core_dev, + struct vfio_pci_region *region, + struct vm_area_struct *vma) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + u64 phys_len, req_len, pgoff, req_start; + + if (!(region->flags & VFIO_REGION_INFO_FLAG_MMAP)) + return -EINVAL; + + if (!(region->flags & VFIO_REGION_INFO_FLAG_READ) && + (vma->vm_flags & VM_READ)) + return -EPERM; + + if (!(region->flags & VFIO_REGION_INFO_FLAG_WRITE) && + (vma->vm_flags & VM_WRITE)) + return -EPERM; + + phys_len = cxl->region.size; + req_len = vma->vm_end - vma->vm_start; + pgoff = vma->vm_pgoff & + ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); + req_start = pgoff << PAGE_SHIFT; + + if (req_start + req_len > phys_len) + return -EINVAL; + + vma->vm_private_data = core_dev; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); + + vm_flags_set(vma, VM_ALLOW_ANY_UNCACHED | VM_IO | VM_PFNMAP | + VM_DONTEXPAND | VM_DONTDUMP); + vma->vm_ops = &vfio_cxl_mmap_ops; + + return 0; +} + +static ssize_t vfio_cxl_region_rw(struct vfio_pci_core_device *core_dev, + char __user *buf, size_t count, loff_t *ppos, + bool iswrite) +{ + unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - VFIO_PCI_NUM_REGIONS; + struct vfio_cxl_region *cxl_region = core_dev->region[i].data; + loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; + + if (!count) + return 0; + + return vfio_pci_core_do_io_rw(core_dev, false, + cxl_region->vaddr, + (char __user *)buf, pos, count, + 0, 0, iswrite); +} + +static void vfio_cxl_region_release(struct vfio_pci_core_device *vdev, + struct vfio_pci_region *region) +{ +} + +static const struct vfio_pci_regops vfio_cxl_regops = { + .rw = vfio_cxl_region_rw, + .mmap = vfio_cxl_region_mmap, + .release = vfio_cxl_region_release, +}; + int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) { struct vfio_cxl *cxl = &core_dev->cxl; struct pci_dev *pdev = core_dev->pdev; + u32 flags; u16 dvsec; int ret; @@ -182,8 +307,21 @@ int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) if (ret) goto err_enable_cxl_device; + flags = VFIO_REGION_INFO_FLAG_READ | + VFIO_REGION_INFO_FLAG_WRITE | + VFIO_REGION_INFO_FLAG_MMAP; + + ret = vfio_pci_core_register_dev_region(core_dev, + PCI_VENDOR_ID_CXL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, + VFIO_REGION_SUBTYPE_CXL, &vfio_cxl_regops, + cxl->region.size, flags, &cxl->region); + if (ret) + goto err_register_cxl_region; + return 0; +err_register_cxl_region: + disable_cxl(core_dev); err_enable_cxl_device: vfio_pci_core_disable(core_dev); return ret; diff --git a/drivers/vfio/pci/vfio_pci_config.c b/drivers/vfio/pci/vfio_pci_config.c index 97422aafaa7b..98f3ac2d305c 100644 --- a/drivers/vfio/pci/vfio_pci_config.c +++ b/drivers/vfio/pci/vfio_pci_config.c @@ -412,6 +412,7 @@ bool __vfio_pci_memory_enabled(struct vfio_pci_core_device *vdev) return pdev->current_state < PCI_D3hot && (pdev->no_command_memory || (cmd & PCI_COMMAND_MEMORY)); } +EXPORT_SYMBOL(__vfio_pci_memory_enabled); /* * Restore the *real* BARs after we detect a FLR or backdoor reset. diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 7762d4a3e825..6523d9d1bffe 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -54,6 +54,7 @@ struct vfio_pci_region { struct vfio_cxl_region { u64 size; u64 addr; + void *vaddr; struct cxl_region *region; }; diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 2b68e6cdf190..71f766c29060 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -372,6 +372,9 @@ struct vfio_region_info_cap_type { /* sub-types for VFIO_REGION_TYPE_GFX */ #define VFIO_REGION_SUBTYPE_GFX_EDID (1) +/* sub-types for VFIO CXL region */ +#define VFIO_REGION_SUBTYPE_CXL (1) + /** * struct vfio_region_gfx_edid - EDID region layout. * From patchwork Fri Sep 20 22:34:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhi Wang X-Patchwork-Id: 13808735 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2069.outbound.protection.outlook.com [40.107.220.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C57F18DF66; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:11.7737 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de1e1571-85bf-4dd7-a5d9-08dcd9c47d59 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7654 vfio_pci_rw() is the common function for handling PCI device read and write. A CXL device programming interface is built on top PCI interfaces. Expose vfio_pci_rw() for vfio-cxl-core to handle the access not interesting for it. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_pci_core.c | 5 +++-- include/linux/vfio_pci_core.h | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index ba0ce0075b2f..9373942f1acb 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1537,8 +1537,8 @@ int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags, } EXPORT_SYMBOL_GPL(vfio_pci_core_ioctl_feature); -static ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, - size_t count, loff_t *ppos, bool iswrite) +ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, + size_t count, loff_t *ppos, bool iswrite) { unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); int ret; @@ -1583,6 +1583,7 @@ static ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, pm_runtime_put(&vdev->pdev->dev); return ret; } +EXPORT_SYMBOL_GPL(vfio_pci_rw); ssize_t vfio_pci_core_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos) diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 6523d9d1bffe..62fa0f54a567 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -144,6 +144,8 @@ long vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd, unsigned long arg); int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags, void __user *arg, size_t argsz); +ssize_t vfio_pci_rw(struct vfio_pci_core_device *vdev, char __user *buf, + size_t count, loff_t *ppos, bool iswrite); ssize_t vfio_pci_core_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos); ssize_t vfio_pci_core_write(struct vfio_device *core_vdev, const char __user *buf, From patchwork Fri Sep 20 22:34:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhi Wang X-Patchwork-Id: 13808739 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2046.outbound.protection.outlook.com [40.107.94.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A10ED18DF93; Fri, 20 Sep 2024 22:35:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.46 ARC-Seal: i=2; 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X-Microsoft-Antispam-Message-Info: yP/8Bjf9ZzPlcZDrax67rK8qe/WhXEz2m2MHpII7D0n/xzZmjVJiu7y/ViOo2pgBeahLKxyEZzXsxLAlO13tUMn78dLi1cR4Ba54jNlapW+GHMbe+reKmuyos3zrVT013XoDKPw/366V4+JuRXyClej/hjUmJX5+sMCfbdYEM95uhvYGiJjM+ufW0h/uP309xgn9JTOyIKuMPzlGheJL0Byn+WEnj6LOUSmYk9scFNYfztT12dm5G+zFScl8jlF+ZuVTUakHL3qTEY/EA+PlK2LABb5/WGPwxq+NFsEMgxGeTDGQlYKywFs0Jhet+uFwmRFVSRslBnIBD6rQhokrNzvqsKRG5gYxM7MxlclVZzXJ4Wb3oolFj38HsH0jLj2NFWpZFL3VKKTnuRyZXD5svvV1KabA9GwSnsaowE8S5Fqp+NhVbze0bQpKuu6uKYLuVXDAcc7FbcvVBJrtL+wT6EdmO1FKZYFDBquBsqxLFqMYdswnYiYaPIijhRNQFeHyoqfRzn2c3KXxzhGzLuknCk3/HVfzVvqJUc6af84BEyPaBtR1PCc1/KAwYaJ0J00xlOHKPBO8ZzNChrz5Yq61pGu8GRUiYcllodc6hbQQHBwnpMyn7YJJlNaKUtuekIejb+0eWMWKrjaW7XcVgNPTh8/0XbWA1pZSOlzKQArrxlNcsZ/BIUn+B6zoAuTnHgTqi6b+TupKfFX5lEPzwDEfjqhPDXU3X+mZe6WCC8HhxwBIlBMa9OqVQn8/isK4pneCFOHpnR6c5bjarmoCs2Ccl8l1MAZRmETXfsmS9FVhwkLqytD/VPTjUtRmqIDGVd8EUPpXMTBG373oQyaIkTLmXLrvO3kWVOF/SrcTRUCIXAl6MJjOPvQoGaK/LlPPaVlbQqgSsjBhZQzaGBOiRA8mt+gn6dQld3Mr/lVsBfteMufUAXP4KYPntd7Avs5mLhfP2hn7eodAc4TWkgjKvYD4he13V2GkR0dwZPRdbGJMHzLHQFvMnGZjfFGK6Fx+gCd59ZXE25S21ssBmu7l/lHRO3uMPI4G7Wp+VZbkkerGHaXE5ogVLwbT6+Ol625VN/EZp66EUQBMTvekKU1+yy7kU4g4HmJTBjVvy4kGiM1ojuirtWPXgD3n1GARAVHYNIbzEGSl9Id69MJmH/3gFAzg5rUBwdBmfe5HZ6Tkk1xMoh73fLxz6qlmmAo4p+UHwkmMWmTtqe/eQHbO06yuKa4N/uR34sUvG7Bv4wLb8vxP+wo89wLy7ckci58DHrmvWXUKlhjIBBb1emgDcOA3Pi7KSnZDmOnL0rnQLeJuRpKm5f7RFwJRjuOYj6v6sNp8xgNvh3zoXVkHZTORpfzINq4/60MXJU6oxcy2GdpAovFc8+03+mjizaOOXre/DjgffV1pltfTqXEYwWj32CxWzm4wE5+Cnyo1gCgTXSn7e4Nr/JeDcq0ABGdI290T2fWoEchN X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:14.8056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e77516d8-f883-40b8-a900-08dcd9c47f2a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029928.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5903 The read/write callbacks in vfio_device_ops is for accessing the device when mmap is not support. It is also used for VFIO variant driver to emulate the device registers. CXL spec illusrates the standard programming interface, part of them are MMIO registers sit in a PCI BAR. Some of them are emulated when passing the CXL type-2 device to the VM. E.g. HDM decoder registers are emulated. Introduce vfio_cxl_core_{read, write}() in the vfio-cxl-core to prepare for emulating the CXL MMIO registers in the PCI BAR. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_cxl_core.c | 20 ++++++++++++++++++++ include/linux/vfio_pci_core.h | 5 +++++ 2 files changed, 25 insertions(+) diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c index ffc15fd94b22..68a935515256 100644 --- a/drivers/vfio/pci/vfio_cxl_core.c +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -396,6 +396,26 @@ void vfio_cxl_core_set_driver_hdm_cap(struct vfio_pci_core_device *core_dev) } EXPORT_SYMBOL(vfio_cxl_core_set_driver_hdm_cap); +ssize_t vfio_cxl_core_read(struct vfio_device *core_vdev, char __user *buf, + size_t count, loff_t *ppos) +{ + struct vfio_pci_core_device *vdev = + container_of(core_vdev, struct vfio_pci_core_device, vdev); + + return vfio_pci_rw(vdev, buf, count, ppos, false); +} +EXPORT_SYMBOL_GPL(vfio_cxl_core_read); + +ssize_t vfio_cxl_core_write(struct vfio_device *core_vdev, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct vfio_pci_core_device *vdev = + container_of(core_vdev, struct vfio_pci_core_device, vdev); + + return vfio_pci_rw(vdev, (char __user *)buf, count, ppos, true); +} +EXPORT_SYMBOL_GPL(vfio_cxl_core_write); + MODULE_LICENSE("GPL"); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 62fa0f54a567..64ccdcdfa95e 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -199,4 +199,9 @@ void vfio_cxl_core_set_resource(struct vfio_pci_core_device *core_dev, void vfio_cxl_core_set_region_size(struct vfio_pci_core_device *core_dev, u64 size); void vfio_cxl_core_set_driver_hdm_cap(struct vfio_pci_core_device *core_dev); +ssize_t vfio_cxl_core_read(struct vfio_device *core_vdev, char __user *buf, + size_t count, loff_t *ppos); +ssize_t vfio_cxl_core_write(struct vfio_device *core_vdev, const char __user *buf, + size_t count, loff_t *ppos); + #endif /* VFIO_PCI_CORE_H */ From patchwork Fri Sep 20 22:34:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhi Wang X-Patchwork-Id: 13808738 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2071.outbound.protection.outlook.com [40.107.94.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12DD018DF8C; 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Fri, 20 Sep 2024 15:35:02 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 20 Sep 2024 15:35:01 -0700 Received: from inno-linux.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 20 Sep 2024 15:35:00 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC 08/13] vfio/cxl: emulate HDM decoder registers Date: Fri, 20 Sep 2024 15:34:41 -0700 Message-ID: <20240920223446.1908673-9-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920223446.1908673-1-zhiw@nvidia.com> References: <20240920223446.1908673-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00029928:EE_|MN0PR12MB6367:EE_ X-MS-Office365-Filtering-Correlation-Id: 74d6b09f-7005-4c0c-a1e9-08dcd9c47fc5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|376014|82310400026|36860700013; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:15.8212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74d6b09f-7005-4c0c-a1e9-08dcd9c47fc5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029928.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6367 To directly access the device memory, the HDM decoder registers on the path from CXL root port to the device needs to be configured when creating a CXL region. However, the physical HDM decoders are owned by the kernel CXL core when creating and configuring a CXL region. Thus the VM is forbidden to access and configure the phsyical HDM decoder registers. The HDM decoder register in the CXL component register group needs to be emulated. Emulate the HDM decoder registers in the vfio-cxl-core. Locate the BAR where the component registers sit. Take a snapshot of component registers before initialize the CXL device. Emulate the HDM decoder registers when VM access them from vfio_device_ops->{read, write}. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_cxl_core.c | 208 ++++++++++++++++++++++++++++++- include/linux/cxl_accel_pci.h | 6 + include/linux/vfio_pci_core.h | 5 + 3 files changed, 216 insertions(+), 3 deletions(-) diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c index 68a935515256..bbb968cb1b70 100644 --- a/drivers/vfio/pci/vfio_cxl_core.c +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -283,6 +283,90 @@ static const struct vfio_pci_regops vfio_cxl_regops = { .release = vfio_cxl_region_release, }; +static int find_bar(struct pci_dev *pdev, u64 *offset, int *bar, u64 size) +{ + u64 start, end, flags; + int index, i; + + for (i = 0; i < PCI_STD_NUM_BARS; i++) { + index = i + PCI_STD_RESOURCES; + flags = pci_resource_flags(pdev, index); + + start = pci_resource_start(pdev, index); + end = pci_resource_end(pdev, index); + + if (*offset >= start && *offset + size - 1 <= end) + break; + + if (flags & IORESOURCE_MEM_64) + i++; + } + + if (i == PCI_STD_NUM_BARS) + return -ENODEV; + + *offset = *offset - start; + *bar = index; + + return 0; +} + +static int find_comp_regs(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + struct pci_dev *pdev = core_dev->pdev; + u64 offset; + int ret, bar; + + ret = cxl_find_comp_regblock_offset(pdev, &offset); + if (ret) + return ret; + + ret = find_bar(pdev, &offset, &bar, SZ_64K); + if (ret) + return ret; + + cxl->comp_reg_bar = bar; + cxl->comp_reg_offset = offset; + cxl->comp_reg_size = SZ_64K; + return 0; +} + +static void clean_virt_comp_regs(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + + kvfree(cxl->comp_reg_virt); +} + +static int setup_virt_comp_regs(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + struct pci_dev *pdev = core_dev->pdev; + u64 offset = cxl->comp_reg_offset; + int bar = cxl->comp_reg_bar; + u64 size = cxl->comp_reg_size; + void *regs; + unsigned int i; + + cxl->comp_reg_virt = kvzalloc(size, GFP_KERNEL); + if (!cxl->comp_reg_virt) + return -ENOMEM; + + regs = ioremap(pci_resource_start(pdev, bar) + offset, size); + if (!regs) { + kvfree(cxl->comp_reg_virt); + return -EFAULT; + } + + for (i = 0; i < size; i += 4) + *(u32 *)(cxl->comp_reg_virt + i) = readl(regs + i); + + iounmap(regs); + + return 0; +} + int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) { struct vfio_cxl *cxl = &core_dev->cxl; @@ -299,10 +383,18 @@ int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) if (!cxl->region.size) return -EINVAL; - ret = vfio_pci_core_enable(core_dev); + ret = find_comp_regs(core_dev); + if (ret) + return ret; + + ret = setup_virt_comp_regs(core_dev); if (ret) return ret; + ret = vfio_pci_core_enable(core_dev); + if (ret) + goto err_pci_core_enable; + ret = enable_cxl(core_dev, dvsec); if (ret) goto err_enable_cxl_device; @@ -324,6 +416,8 @@ int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) disable_cxl(core_dev); err_enable_cxl_device: vfio_pci_core_disable(core_dev); +err_pci_core_enable: + clean_virt_comp_regs(core_dev); return ret; } EXPORT_SYMBOL(vfio_cxl_core_enable); @@ -341,6 +435,7 @@ void vfio_cxl_core_close_device(struct vfio_device *vdev) disable_cxl(core_dev); vfio_pci_core_close_device(vdev); + clean_virt_comp_regs(core_dev); } EXPORT_SYMBOL(vfio_cxl_core_close_device); @@ -396,13 +491,102 @@ void vfio_cxl_core_set_driver_hdm_cap(struct vfio_pci_core_device *core_dev) } EXPORT_SYMBOL(vfio_cxl_core_set_driver_hdm_cap); +static bool is_hdm_regblock(struct vfio_cxl *cxl, u64 offset, size_t count) +{ + return offset >= cxl->hdm_reg_offset && + offset + count < cxl->hdm_reg_offset + + cxl->hdm_reg_size; +} + +static void write_hdm_decoder_global(void *virt, u64 offset, u32 v) +{ + if (offset == 0x4) + *(u32 *)(virt + offset) = v & GENMASK(1, 0); +} + +static void write_hdm_decoder_n(void *virt, u64 offset, u32 v) +{ + u32 cur, index; + + index = (offset - 0x10) / 0x20; + + /* HDM decoder registers are locked? */ + cur = *(u32 *)(virt + index * 0x20 + 0x20); + + if (cur & CXL_HDM_DECODER0_CTRL_LOCK && + cur & CXL_HDM_DECODER0_CTRL_COMMITTED) + return; + + /* emulate HDM_DECODER_CTRL. */ + if (offset == CXL_HDM_DECODER0_CTRL_OFFSET(index)) { + v &= ~CXL_HDM_DECODER0_CTRL_COMMIT_ERROR; + + /* commit/de-commit */ + if (v & CXL_HDM_DECODER0_CTRL_COMMIT) + v |= CXL_HDM_DECODER0_CTRL_COMMITTED; + else + v &= ~CXL_HDM_DECODER0_CTRL_COMMITTED; + } + *(u32 *)(virt + offset) = v; +} + +static ssize_t +emulate_hdm_regblock(struct vfio_device *vdev, char __user *buf, + size_t count, loff_t *ppos, bool write) +{ + struct vfio_pci_core_device *core_dev = + container_of(vdev, struct vfio_pci_core_device, vdev); + struct vfio_cxl *cxl = &core_dev->cxl; + u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; + void *hdm_reg_virt; + u64 hdm_offset; + u32 v; + + hdm_offset = pos - cxl->hdm_reg_offset; + hdm_reg_virt = cxl->comp_reg_virt + + (cxl->hdm_reg_offset - cxl->comp_reg_offset); + + if (!write) { + v = *(u32 *)(hdm_reg_virt + hdm_offset); + + if (copy_to_user(buf, &v, 4)) + return -EFAULT; + } else { + if (copy_from_user(&v, buf, 4)) + return -EFAULT; + + if (hdm_offset < 0x10) + write_hdm_decoder_global(hdm_reg_virt, hdm_offset, v); + else + write_hdm_decoder_n(hdm_reg_virt, hdm_offset, v); + } + return count; +} + ssize_t vfio_cxl_core_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos) { struct vfio_pci_core_device *vdev = container_of(core_vdev, struct vfio_pci_core_device, vdev); + struct vfio_cxl *cxl = &vdev->cxl; + u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; + unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); + + if (!count) + return 0; + + if (index != cxl->comp_reg_bar) + return vfio_pci_rw(vdev, buf, count, ppos, false); + + if (WARN_ON_ONCE(!IS_ALIGNED(pos, 4) || count != 4)) + return -EINVAL; - return vfio_pci_rw(vdev, buf, count, ppos, false); + if (is_hdm_regblock(cxl, pos, count)) + return emulate_hdm_regblock(core_vdev, buf, count, + ppos, false); + else + return vfio_pci_rw(vdev, (char __user *)buf, count, + ppos, false); } EXPORT_SYMBOL_GPL(vfio_cxl_core_read); @@ -411,8 +595,26 @@ ssize_t vfio_cxl_core_write(struct vfio_device *core_vdev, const char __user *bu { struct vfio_pci_core_device *vdev = container_of(core_vdev, struct vfio_pci_core_device, vdev); + struct vfio_cxl *cxl = &vdev->cxl; + u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; + unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); + + if (!count) + return 0; + + if (index != cxl->comp_reg_bar) + return vfio_pci_rw(vdev, (char __user *)buf, count, ppos, + true); + + if (WARN_ON_ONCE(!IS_ALIGNED(pos, 4) || count != 4)) + return -EINVAL; - return vfio_pci_rw(vdev, (char __user *)buf, count, ppos, true); + if (is_hdm_regblock(cxl, pos, count)) + return emulate_hdm_regblock(core_vdev, (char __user *)buf, + count, ppos, true); + else + return vfio_pci_rw(vdev, (char __user *)buf, count, ppos, + true); } EXPORT_SYMBOL_GPL(vfio_cxl_core_write); diff --git a/include/linux/cxl_accel_pci.h b/include/linux/cxl_accel_pci.h index c337ae8797e6..090f60fb9a3f 100644 --- a/include/linux/cxl_accel_pci.h +++ b/include/linux/cxl_accel_pci.h @@ -20,4 +20,10 @@ #define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) #define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28) +#define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20) +#define CXL_HDM_DECODER0_CTRL_LOCK BIT(8) +#define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9) +#define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10) +#define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11) + #endif diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 64ccdcdfa95e..9d295ca9382a 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -62,6 +62,11 @@ struct vfio_cxl { u8 caps; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:14.7790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f319e89-6e3f-4cd8-1080-08dcd9c47f1d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7230 CXL device programming interfaces are built upon PCI interfaces. Thus the vfio-pci-core can be leveraged to handle a CXL device. However, CXL device also has difference with PCI devicce: - No INTX support, only MSI/MSIX is supported. - Resest is one via CXL reset. FLR only resets CXL.io. Introduce the CXL device awareness to the vfio-pci-core. Expose a new VFIO device flags to the userspace to identify the VFIO device is a CXL device. Disable INTX support in the vfio-pci-core. Disable FLR reset for the CXL device as the kernel CXL core hasn't support CXL reset yet. Disable mmap support on the CXL MMIO BAR in vfio-pci-core. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_cxl_core.c | 8 ++++++ drivers/vfio/pci/vfio_pci_core.c | 42 +++++++++++++++++++++----------- include/linux/vfio_pci_core.h | 2 ++ include/uapi/linux/vfio.h | 1 + 4 files changed, 39 insertions(+), 14 deletions(-) diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c index bbb968cb1b70..d8b51f8792a2 100644 --- a/drivers/vfio/pci/vfio_cxl_core.c +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -391,6 +391,8 @@ int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) if (ret) return ret; + vfio_pci_core_enable_cxl(core_dev); + ret = vfio_pci_core_enable(core_dev); if (ret) goto err_pci_core_enable; @@ -618,6 +620,12 @@ ssize_t vfio_cxl_core_write(struct vfio_device *core_vdev, const char __user *bu } EXPORT_SYMBOL_GPL(vfio_cxl_core_write); +void vfio_pci_core_enable_cxl(struct vfio_pci_core_device *core_dev) +{ + core_dev->has_cxl = true; +} +EXPORT_SYMBOL(vfio_pci_core_enable_cxl); + MODULE_LICENSE("GPL"); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 9373942f1acb..e0f23b538858 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -126,6 +126,9 @@ static void vfio_pci_probe_mmaps(struct vfio_pci_core_device *vdev) if (!(res->flags & IORESOURCE_MEM)) goto no_mmap; + if (vdev->has_cxl && bar == vdev->cxl.comp_reg_bar) + goto no_mmap; + /* * The PCI core shouldn't set up a resource with a * type but zero size. But there may be bugs that @@ -487,10 +490,15 @@ int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) if (ret) goto out_power; - /* If reset fails because of the device lock, fail this path entirely */ - ret = pci_try_reset_function(pdev); - if (ret == -EAGAIN) - goto out_disable_device; + if (!vdev->has_cxl) { + /* If reset fails because of the device lock, fail this path entirely */ + ret = pci_try_reset_function(pdev); + if (ret == -EAGAIN) + goto out_disable_device; + } else { + /* CXL Reset is missing in CXL core. FLR only resets CXL.io path. */ + ret = -ENODEV; + } vdev->reset_works = !ret; pci_save_state(pdev); @@ -498,14 +506,17 @@ int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) if (!vdev->pci_saved_state) pci_dbg(pdev, "%s: Couldn't store saved state\n", __func__); - if (likely(!nointxmask)) { - if (vfio_pci_nointx(pdev)) { - pci_info(pdev, "Masking broken INTx support\n"); - vdev->nointx = true; - pci_intx(pdev, 0); - } else - vdev->pci_2_3 = pci_intx_mask_supported(pdev); - } + if (!vdev->has_cxl) { + if (likely(!nointxmask)) { + if (vfio_pci_nointx(pdev)) { + pci_info(pdev, "Masking broken INTx support\n"); + vdev->nointx = true; + pci_intx(pdev, 0); + } else + vdev->pci_2_3 = pci_intx_mask_supported(pdev); + } + } else + vdev->nointx = true; /* CXL device doesn't have INTX. */ pci_read_config_word(pdev, PCI_COMMAND, &cmd); if (vdev->pci_2_3 && (cmd & PCI_COMMAND_INTX_DISABLE)) { @@ -541,7 +552,6 @@ int vfio_pci_core_enable(struct vfio_pci_core_device *vdev) if (!vfio_vga_disabled() && vfio_pci_is_vga(pdev)) vdev->has_vga = true; - return 0; out_free_zdev: @@ -657,7 +667,8 @@ void vfio_pci_core_disable(struct vfio_pci_core_device *vdev) * Disable INTx and MSI, presumably to avoid spurious interrupts * during reset. Stolen from pci_reset_function() */ - pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); + if (!vdev->nointx) + pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); /* * Try to get the locks ourselves to prevent a deadlock. The @@ -973,6 +984,9 @@ static int vfio_pci_ioctl_get_info(struct vfio_pci_core_device *vdev, if (vdev->reset_works) info.flags |= VFIO_DEVICE_FLAGS_RESET; + if (vdev->has_cxl) + info.flags |= VFIO_DEVICE_FLAGS_CXL; + info.num_regions = VFIO_PCI_NUM_REGIONS + vdev->num_regions; info.num_irqs = VFIO_PCI_NUM_IRQS; diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index 9d295ca9382a..e5646aad3eb3 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -113,6 +113,7 @@ struct vfio_pci_core_device { bool needs_pm_restore:1; bool pm_intx_masked:1; bool pm_runtime_engaged:1; + bool has_cxl:1; struct pci_saved_state *pci_saved_state; struct pci_saved_state *pm_save; int ioeventfds_nr; @@ -208,5 +209,6 @@ ssize_t vfio_cxl_core_read(struct vfio_device *core_vdev, char __user *buf, size_t count, loff_t *ppos); ssize_t vfio_cxl_core_write(struct vfio_device *core_vdev, const char __user *buf, size_t count, loff_t *ppos); +void vfio_pci_core_enable_cxl(struct vfio_pci_core_device *core_dev); #endif /* VFIO_PCI_CORE_H */ diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 71f766c29060..0895183feaac 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -214,6 +214,7 @@ struct vfio_device_info { #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6) /* vfio-fsl-mc device */ #define VFIO_DEVICE_FLAGS_CAPS (1 << 7) /* Info supports caps */ #define VFIO_DEVICE_FLAGS_CDX (1 << 8) /* vfio-cdx device */ +#define VFIO_DEVICE_FLAGS_CXL (1 << 9) /* Device supports CXL support */ __u32 num_regions; /* Max region index + 1 */ __u32 num_irqs; /* Max IRQ index + 1 */ __u32 cap_offset; /* Offset within info struct of first cap */ From patchwork Fri Sep 20 22:34:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhi Wang X-Patchwork-Id: 13808740 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2055.outbound.protection.outlook.com [40.107.243.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 352EC18CC00; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:19.5513 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8945d7a3-2ca6-4203-a575-08dcd9c481f7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5635 A CXL device has many DVSEC registers in the configuration space for device control and enumeration. E.g. enable CXL.mem/CXL.cahce. However, the kernel CXL core owns those registers to control the device. Thus, the VM is forbidden to touch the physical device control registers. Read/write the CXL DVSEC from/to the virt configuration space. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_pci_config.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/vfio/pci/vfio_pci_config.c b/drivers/vfio/pci/vfio_pci_config.c index 98f3ac2d305c..af8c0997c796 100644 --- a/drivers/vfio/pci/vfio_pci_config.c +++ b/drivers/vfio/pci/vfio_pci_config.c @@ -1902,6 +1902,15 @@ static ssize_t vfio_config_do_rw(struct vfio_pci_core_device *vdev, char __user perm = &ecap_perms[cap_id]; cap_start = vfio_find_cap_start(vdev, *ppos); + + if (cap_id == PCI_EXT_CAP_ID_DVSEC) { + u32 dword; + + memcpy(&dword, vdev->vconfig + cap_start + PCI_DVSEC_HEADER1, 4); + + if (PCI_DVSEC_HEADER1_VID(dword) == PCI_VENDOR_ID_CXL) + perm = &virt_perms; + } } else { WARN_ON(cap_id > PCI_CAP_ID_MAX); From patchwork Fri Sep 20 22:34:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhi Wang X-Patchwork-Id: 13808741 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2056.outbound.protection.outlook.com [40.107.94.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D312218CC02; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:20.7830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9058ca05-4d2c-453e-6d7f-08dcd9c482cb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5719 The userspace needs CXL device information, e.g. HDM decoder registers offset to know when the VM updates the HDM decoder and re-build the mapping between GPA in the virtual HDM decoder base registers and the HPA of the CXL region created by the vfio-cxl-core when initialize the CXL device. To acheive this, a new VFIO CXL device cap is required to convey those information to the usersapce. Introduce a new VFIO CXL device cap to expose necessary information to the userspace. Initialize the cap with the information filled when the CXL device is being initialized. vfio-pci-core fills the CXL cap into the caps returned to userapce when CXL is enabled. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_cxl_core.c | 15 +++++++++++++++ drivers/vfio/pci/vfio_pci_core.c | 19 ++++++++++++++++++- include/linux/vfio_pci_core.h | 1 + include/uapi/linux/vfio.h | 10 ++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/vfio/pci/vfio_cxl_core.c b/drivers/vfio/pci/vfio_cxl_core.c index d8b51f8792a2..cebc444b54b7 100644 --- a/drivers/vfio/pci/vfio_cxl_core.c +++ b/drivers/vfio/pci/vfio_cxl_core.c @@ -367,6 +367,19 @@ static int setup_virt_comp_regs(struct vfio_pci_core_device *core_dev) return 0; } +static void init_vfio_cxl_cap(struct vfio_pci_core_device *core_dev) +{ + struct vfio_cxl *cxl = &core_dev->cxl; + + cxl->cap.header.id = VFIO_DEVICE_INFO_CAP_CXL; + cxl->cap.header.version = 1; + cxl->cap.hdm_count = cxl->hdm_count; + cxl->cap.hdm_reg_offset = cxl->hdm_reg_offset; + cxl->cap.hdm_reg_size = cxl->hdm_reg_size; + cxl->cap.hdm_reg_bar_index = cxl->comp_reg_bar; + cxl->cap.dpa_size = cxl->dpa_size; +} + int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) { struct vfio_cxl *cxl = &core_dev->cxl; @@ -401,6 +414,8 @@ int vfio_cxl_core_enable(struct vfio_pci_core_device *core_dev) if (ret) goto err_enable_cxl_device; + init_vfio_cxl_cap(core_dev); + flags = VFIO_REGION_INFO_FLAG_READ | VFIO_REGION_INFO_FLAG_WRITE | VFIO_REGION_INFO_FLAG_MMAP; diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index e0f23b538858..47e65e28a42b 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -963,6 +963,15 @@ static int vfio_pci_info_atomic_cap(struct vfio_pci_core_device *vdev, return vfio_info_add_capability(caps, &cap.header, sizeof(cap)); } +static int vfio_pci_info_cxl_cap(struct vfio_pci_core_device *vdev, + struct vfio_info_cap *caps) +{ + struct vfio_cxl *cxl = &vdev->cxl; + + return vfio_info_add_capability(caps, &cxl->cap.header, + sizeof(cxl->cap)); +} + static int vfio_pci_ioctl_get_info(struct vfio_pci_core_device *vdev, struct vfio_device_info __user *arg) { @@ -984,9 +993,17 @@ static int vfio_pci_ioctl_get_info(struct vfio_pci_core_device *vdev, if (vdev->reset_works) info.flags |= VFIO_DEVICE_FLAGS_RESET; - if (vdev->has_cxl) + if (vdev->has_cxl) { info.flags |= VFIO_DEVICE_FLAGS_CXL; + ret = vfio_pci_info_cxl_cap(vdev, &caps); + if (ret) { + pci_warn(vdev->pdev, + "Failed to setup CXL capabilities\n"); + return ret; + } + } + info.num_regions = VFIO_PCI_NUM_REGIONS + vdev->num_regions; info.num_irqs = VFIO_PCI_NUM_IRQS; diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index e5646aad3eb3..d79f7a91d977 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -80,6 +80,7 @@ struct vfio_cxl { struct resource ram_res; struct vfio_cxl_region region; + struct vfio_device_info_cap_cxl cap; }; struct vfio_pci_core_device { diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 0895183feaac..9a5972961280 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -257,6 +257,16 @@ struct vfio_device_info_cap_pci_atomic_comp { __u32 reserved; }; +#define VFIO_DEVICE_INFO_CAP_CXL 6 +struct vfio_device_info_cap_cxl { + struct vfio_info_cap_header header; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:23.6338 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b602c0b5-eaa5-4c8f-3421-08dcd9c48464 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5788 To demostrate the VFIO CXL core, a VFIO variant driver for QEMU CXL accel device is introduced, so that people to test can try the patches. This patch is not meant to be merged. Signed-off-by: Zhi Wang --- drivers/vfio/pci/Kconfig | 2 + drivers/vfio/pci/Makefile | 2 + drivers/vfio/pci/cxl-accel/Kconfig | 6 ++ drivers/vfio/pci/cxl-accel/Makefile | 3 + drivers/vfio/pci/cxl-accel/main.c | 116 ++++++++++++++++++++++++++++ 5 files changed, 129 insertions(+) create mode 100644 drivers/vfio/pci/cxl-accel/Kconfig create mode 100644 drivers/vfio/pci/cxl-accel/Makefile create mode 100644 drivers/vfio/pci/cxl-accel/main.c diff --git a/drivers/vfio/pci/Kconfig b/drivers/vfio/pci/Kconfig index 2196e79b132b..9eebce09ffa2 100644 --- a/drivers/vfio/pci/Kconfig +++ b/drivers/vfio/pci/Kconfig @@ -75,4 +75,6 @@ source "drivers/vfio/pci/nvgrace-gpu/Kconfig" source "drivers/vfio/pci/qat/Kconfig" +source "drivers/vfio/pci/cxl-accel/Kconfig" + endmenu diff --git a/drivers/vfio/pci/Makefile b/drivers/vfio/pci/Makefile index b51221b94b0b..03293b52c5e3 100644 --- a/drivers/vfio/pci/Makefile +++ b/drivers/vfio/pci/Makefile @@ -22,3 +22,5 @@ obj-$(CONFIG_VIRTIO_VFIO_PCI) += virtio/ obj-$(CONFIG_NVGRACE_GPU_VFIO_PCI) += nvgrace-gpu/ obj-$(CONFIG_QAT_VFIO_PCI) += qat/ + +obj-$(CONFIG_CXL_ACCEL_VFIO_PCI) += cxl-accel/ diff --git a/drivers/vfio/pci/cxl-accel/Kconfig b/drivers/vfio/pci/cxl-accel/Kconfig new file mode 100644 index 000000000000..c3c9d7ec7fa4 --- /dev/null +++ b/drivers/vfio/pci/cxl-accel/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +config CXL_ACCEL_VFIO_PCI + tristate "VFIO support for the QEMU CXL accel device" + select VFIO_CXL_CORE + help + If you don't know what to do here, say N. diff --git a/drivers/vfio/pci/cxl-accel/Makefile b/drivers/vfio/pci/cxl-accel/Makefile new file mode 100644 index 000000000000..20f190482cc9 --- /dev/null +++ b/drivers/vfio/pci/cxl-accel/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_CXL_ACCEL_VFIO_PCI) += cxl-accel-vfio-pci.o +cxl-accel-vfio-pci-y := main.o diff --git a/drivers/vfio/pci/cxl-accel/main.c b/drivers/vfio/pci/cxl-accel/main.c new file mode 100644 index 000000000000..1672fb9d9232 --- /dev/null +++ b/drivers/vfio/pci/cxl-accel/main.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved + */ + +#include +#include + +struct cxl_device { + struct vfio_pci_core_device core_device; +}; + +static int cxl_open_device(struct vfio_device *vdev) +{ + struct vfio_pci_core_device *core_dev = + container_of(vdev, struct vfio_pci_core_device, vdev); + struct resource res; + int ret; + + /* Provide the device infomation to the kernel CXL core.*/ + /* Device DPA */ + res = DEFINE_RES_MEM(0, SZ_256M); + vfio_cxl_core_set_resource(core_dev, res, CXL_ACCEL_RES_DPA); + + /* Device RAM */ + res = DEFINE_RES_MEM_NAMED(0, SZ_256M, "ram"); + vfio_cxl_core_set_resource(core_dev, res, CXL_ACCEL_RES_RAM); + + /* The expected size of the CXL region to be created */ + vfio_cxl_core_set_region_size(core_dev, SZ_256M); + vfio_cxl_core_set_driver_hdm_cap(core_dev); + + /* Initailize the CXL device and enable the vfio-pci-core */ + ret = vfio_cxl_core_enable(core_dev); + if (ret) + return ret; + + vfio_cxl_core_finish_enable(core_dev); + + return 0; +} + +static const struct vfio_device_ops cxl_core_ops = { + .name = "cxl-vfio-pci", + .init = vfio_pci_core_init_dev, + .release = vfio_pci_core_release_dev, + .open_device = cxl_open_device, + .close_device = vfio_cxl_core_close_device, + .ioctl = vfio_pci_core_ioctl, + .device_feature = vfio_pci_core_ioctl_feature, + .read = vfio_cxl_core_read, + .write = vfio_cxl_core_write, + .mmap = vfio_pci_core_mmap, + .request = vfio_pci_core_request, + .match = vfio_pci_core_match, + .bind_iommufd = vfio_iommufd_physical_bind, + .unbind_iommufd = vfio_iommufd_physical_unbind, + .attach_ioas = vfio_iommufd_physical_attach_ioas, + .detach_ioas = vfio_iommufd_physical_detach_ioas, +}; + +static int cxl_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + const struct vfio_device_ops *ops = &cxl_core_ops; + struct cxl_device *cxl_device; + int ret; + + cxl_device = vfio_alloc_device(cxl_device, core_device.vdev, + &pdev->dev, ops); + if (IS_ERR(cxl_device)) + return PTR_ERR(cxl_device); + + dev_set_drvdata(&pdev->dev, &cxl_device->core_device); + + ret = vfio_pci_core_register_device(&cxl_device->core_device); + if (ret) + goto out_put_vdev; + + return ret; + +out_put_vdev: + vfio_put_device(&cxl_device->core_device.vdev); + return ret; +} + +static void cxl_remove(struct pci_dev *pdev) +{ + struct vfio_pci_core_device *core_device = dev_get_drvdata(&pdev->dev); + + vfio_pci_core_unregister_device(core_device); + vfio_put_device(&core_device->vdev); +} + +static const struct pci_device_id cxl_vfio_pci_table[] = { + { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_INTEL, 0xd94) }, + {} +}; + +MODULE_DEVICE_TABLE(pci, cxl_vfio_pci_table); + +static struct pci_driver cxl_vfio_pci_driver = { + .name = KBUILD_MODNAME, + .id_table = cxl_vfio_pci_table, + .probe = cxl_probe, + .remove = cxl_remove, + .err_handler = &vfio_pci_core_err_handlers, + .driver_managed_dma = true, +}; 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Fri, 20 Sep 2024 15:35:08 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 20 Sep 2024 15:35:07 -0700 Received: from inno-linux.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 20 Sep 2024 15:35:06 -0700 From: Zhi Wang To: , CC: , , , , , , , , , , , , , , , , , , , Subject: [RFC 13/13] vfio/cxl: workaround: don't take resource region when cxl is enabled. Date: Fri, 20 Sep 2024 15:34:46 -0700 Message-ID: <20240920223446.1908673-14-zhiw@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240920223446.1908673-1-zhiw@nvidia.com> References: <20240920223446.1908673-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992A:EE_|SN7PR12MB7452:EE_ X-MS-Office365-Filtering-Correlation-Id: e5f1de34-add2-4b63-f95b-08dcd9c484f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: x1oK/IPxaSt6TbWzlRCmcv7HmXJO37cZsmpJWYkvk1QJmyr4m5mykTbp5mXkYID+JLhU3pfY3dbW4JUVcN211+ytJFwFPPMNMlZNzZsdxwRvQPmk+ECXQp1FAD0LEsGdmCDIR6NT9xxhyABq4TcqstpzSlMS8Qqk6a1QRlHZgqEhpfHr+lHa09tYdTxq1Yd5NWg/56MQozFsN76Q2hajikqGR24Y5Vz2+9mig7qGDkBVOLmt+70G6s82zpmy1qAJQroUtFMDjKo1kGJu//RAuA0fBCD1GBqkGcqgmYxidAPXzqxpYh1Zp9/s4qo6YMWa/XF3d5e7XuNYSRSKlLbMicTZtolBNlGFt2KsAu+qN8T7XZ+9tRGRH1MpBW/Ai1xUeMoLu0EW8PQxdOBzyPWXG51H2wY8mfy54f+bMLFrP/95XW+XtCdJAxjKPPc8pxm1bZAvCdJw+tcElXhzIbS/PeFx4M6j3wSPFeEwGQknIWNLEXq6PKXJio4Kr84Kznc5S+5rsURt6zurXOLeayyOuITDSuvHrF8OEH4qs9UWV164WVE+ZtqKQsLbb4YLF0wobPjBZ3tY3N1FVOl/5cqu3uXmlY2Dtw85Ulmtt0oGoE2cVs5oedWtKXoySNH/CFL4YhahV+yPEYWEo0I+aHO3xEwAmEiE0d6RtTCjvoVaTXzu9UuJfcfPYy9bpxyl5Ft/En62p3GiGB9jGUhnrrEM6rHrYtOAqUep8zanD68xFCRGVaZSc0Y0SaV9aoBQv+e5VyO3wAlLgEWSJu4JJS0chIWUCCo4C8rhG9VJ64nkrMG7C5UIH/0JU91o/OW96Ctu+ATSSCJDt4Qt/spXMKauokT4yuhygqKpD0nOJzhzz6bP3BSqLPuWjAxZIsq4jMCy0tYCSY50fatqhOcSXvWEcWPDoWi/QTUZMxS0b4MJPVHDG2lngSEmARq8OBCW7WH7nXItSideraBVqebQfANw/xEYbvhv2H54GsveqA8dgbXOR6yTGZPYFTsigpq8qifqckU6JAKKzoiVWLXia91hkZhM03U8S48P9XMfzWpVsTNibOwBLVzTVYmcv8XPTPrIK+UNKQgk3Ff9ElBu/2Vv2afyX+ZJXWoPSWzxXWsWari2zk5AKuIYEorOC2sM0u5mymFKJgELjz505AOPanNW+Io2AN4lz88bZBhyGABdYZ/QA6J1IZwzFJcvS+pmRsO0vKeM5uxy2BVYQrumLp+gmWUHDOxaMn2KCw9mJSCJyOQQv86vdzbnGmAnby/M4qmxSLhsrX79cenrKpi4Wz8LVF9aAKl4OoElC3X6WWiKhZuBMNAFpBR5sRXz2VxkAuwViGM5QPzyrFtJzz1BX70NAhJkzUDHvriHSApXZSyn7CiosieIE+/7t55A+LzW2oswNl5UHGEE1H/KXv/kGVs3c0kYcXzq9Qid46j9G2RluQCpmFDCbiG5PewKvs8bQo6F X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2024 22:35:24.5044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5f1de34-add2-4b63-f95b-08dcd9c484f4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7452 Looking for a better suggestion here. vfio-cxl-core uses the kernel CXL core to initialize the CXL device and the kernel CXL core has requested the resource regions when accessing the PCI BARs. Thus, requesting resource region in vfio-pci-core always fails. Signed-off-by: Zhi Wang --- drivers/vfio/pci/vfio_pci_core.c | 15 +++++++++------ drivers/vfio/pci/vfio_pci_rdwr.c | 8 +++++--- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 47e65e28a42b..91f8b984b53c 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -633,7 +633,8 @@ void vfio_pci_core_disable(struct vfio_pci_core_device *vdev) if (!vdev->barmap[bar]) continue; pci_iounmap(pdev, vdev->barmap[bar]); - pci_release_selected_regions(pdev, 1 << bar); + if (!vdev->has_cxl) + pci_release_selected_regions(pdev, 1 << bar); vdev->barmap[bar] = NULL; } @@ -1775,13 +1776,15 @@ int vfio_pci_core_mmap(struct vfio_device *core_vdev, struct vm_area_struct *vma * we need to request the region and the barmap tracks that. */ if (!vdev->barmap[index]) { - ret = pci_request_selected_regions(pdev, - 1 << index, "vfio-pci"); - if (ret) - return ret; + if (!vdev->has_cxl) { + ret = pci_request_selected_regions(pdev, + 1 << index, "vfio-pci"); + if (ret) + return ret; + } vdev->barmap[index] = pci_iomap(pdev, index, 0); - if (!vdev->barmap[index]) { + if (!vdev->barmap[index] && !vdev->has_cxl) { pci_release_selected_regions(pdev, 1 << index); return -ENOMEM; } diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index 66b72c289284..df7b5aa078e9 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -214,9 +214,11 @@ int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar) if (vdev->barmap[bar]) return 0; - ret = pci_request_selected_regions(pdev, 1 << bar, "vfio"); - if (ret) - return ret; + if (!vdev->has_cxl) { + ret = pci_request_selected_regions(pdev, 1 << bar, "vfio"); + if (ret) + return ret; + } io = pci_iomap(pdev, bar, 0); if (!io) {