From patchwork Fri Sep 20 22:48:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shushura X-Patchwork-Id: 13808767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D3FFCF9C69 for ; Sat, 21 Sep 2024 01:12:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sroeT-0003G4-Qf; Fri, 20 Sep 2024 21:11:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1srmQp-0003Lq-Gm for qemu-devel@nongnu.org; Fri, 20 Sep 2024 18:48:55 -0400 Received: from mail-4323.proton.ch ([185.70.43.23]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1srmQl-0004MK-VN for qemu-devel@nongnu.org; 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envelope-from=me@nikitashushura.com; helo=mail-4323.proton.ch X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 20 Sep 2024 21:11:05 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --- hw/intc/grlib_irqmp.c | 68 +++++++++++++++++++++++++++++++------------ 1 file changed, 49 insertions(+), 19 deletions(-) diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 37ac63fd80..2fd76dd1b4 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -1,8 +1,6 @@ /* * QEMU GRLIB IRQMP Emulator * - * (Extended interrupt not supported) - * * SPDX-License-Identifier: MIT * * Copyright (c) 2010-2024 AdaCore @@ -38,25 +36,29 @@ #include "qemu/module.h" #include "qom/object.h" -#define IRQMP_MAX_CPU 16 -#define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */ +#define IRQMP_MAX_CPU (16) +#define IRQMP_REG_SIZE (256) /* Size of memory mapped registers */ /* Memory mapped register offsets */ -#define LEVEL_OFFSET 0x00 -#define PENDING_OFFSET 0x04 -#define FORCE0_OFFSET 0x08 -#define CLEAR_OFFSET 0x0C -#define MP_STATUS_OFFSET 0x10 -#define BROADCAST_OFFSET 0x14 -#define MASK_OFFSET 0x40 -#define FORCE_OFFSET 0x80 -#define EXTENDED_OFFSET 0xC0 +#define LEVEL_OFFSET (0x00) +#define PENDING_OFFSET (0x04) +#define FORCE0_OFFSET (0x08) +#define CLEAR_OFFSET (0x0C) +#define MP_STATUS_OFFSET (0x10) +#define BROADCAST_OFFSET (0x14) +#define MASK_OFFSET (0x40) +#define FORCE_OFFSET (0x80) +#define EXTENDED_OFFSET (0xC0) /* Multiprocessor Status Register */ #define MP_STATUS_CPU_STATUS_MASK ((1 << IRQMP_MAX_CPU)-2) -#define MP_STATUS_NCPU_SHIFT 28 +#define MP_STATUS_NCPU_SHIFT (28) +#define MP_STATUS_EIRQ_OFFSET (16) + +#define MAX_PILS_STD (16) +#define MAX_PILS_EXT (32) -#define MAX_PILS 16 +#define DEFAULT_EIRQ (12) OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP) @@ -68,6 +70,7 @@ struct IRQMP { MemoryRegion iomem; unsigned int ncpus; + unsigned int eirq; IRQMPState *state; qemu_irq start_signal[IRQMP_MAX_CPU]; qemu_irq irq[IRQMP_MAX_CPU]; @@ -89,13 +92,25 @@ struct IRQMPState { static void grlib_irqmp_check_irqs(IRQMPState *state) { - int i; + int i, j; assert(state != NULL); assert(state->parent != NULL); for (i = 0; i < state->parent->ncpus; i++) { uint32_t pend = (state->pending | state->force[i]) & state->mask[i]; + + /* + * Check is pending interrupt is extended, + * if so set pending to EIRQ and acknowledge extended interrupt" + */ + for (j = MAX_PILS_STD; j <= MAX_PILS_EXT; j++) { + if ((pend & (1 << j)) != 0) { + pend = (1 << state->parent->eirq); + state->extended[i] = (j & 0xffff); + } + } + uint32_t level0 = pend & ~state->level; uint32_t level1 = pend & state->level; @@ -110,6 +125,10 @@ static void grlib_irqmp_check_irqs(IRQMPState *state) static void grlib_irqmp_ack_mask(IRQMPState *state, unsigned int cpu, uint32_t mask) { + if ((mask & (1 << state->parent->eirq)) != 0) { + mask |= (1 << state->extended[cpu]); + } + /* Clear registers */ state->pending &= ~mask; state->force[cpu] &= ~mask; @@ -144,7 +163,6 @@ static void grlib_irqmp_set_irq(void *opaque, int irq, int level) assert(s != NULL); assert(s->parent != NULL); - if (level) { trace_grlib_irqmp_set_irq(irq); @@ -278,6 +296,9 @@ static void grlib_irqmp_write(void *opaque, hwaddr addr, state->mpstatus &= ~(1 << i); } } + + /* Writing EIRQ number */ + state->mpstatus |= (state->parent->eirq << MP_STATUS_EIRQ_OFFSET); return; case BROADCAST_OFFSET: @@ -345,7 +366,8 @@ static void grlib_irqmp_reset(DeviceState *d) memset(irqmp->state, 0, sizeof *irqmp->state); irqmp->state->parent = irqmp; irqmp->state->mpstatus = ((irqmp->ncpus - 1) << MP_STATUS_NCPU_SHIFT) | - ((1 << irqmp->ncpus) - 2); + ((1 << irqmp->ncpus) - 2) | + (irqmp->eirq << MP_STATUS_EIRQ_OFFSET); } static void grlib_irqmp_realize(DeviceState *dev, Error **errp) @@ -359,7 +381,14 @@ static void grlib_irqmp_realize(DeviceState *dev, Error **errp) return; } - qdev_init_gpio_in(dev, grlib_irqmp_set_irq, MAX_PILS); + if ((!irqmp->eirq) || (irqmp->eirq >= MAX_PILS_STD)) { + error_setg(errp, "Invalid eirq properties: " + "%u, must be 0 < eirq < %u.", irqmp->eirq, + MAX_PILS_STD); + return; + } + + qdev_init_gpio_in(dev, grlib_irqmp_set_irq, MAX_PILS_EXT); /* * Transitionning from 0 to 1 starts the CPUs. The opposite can't @@ -378,6 +407,7 @@ static void grlib_irqmp_realize(DeviceState *dev, Error **errp) static Property grlib_irqmp_properties[] = { DEFINE_PROP_UINT32("ncpus", IRQMP, ncpus, 1), + DEFINE_PROP_UINT32("eirq", IRQMP, eirq, DEFAULT_EIRQ), DEFINE_PROP_END_OF_LIST(), }; From patchwork Fri Sep 20 22:54:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shushura X-Patchwork-Id: 13808766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED430CF9C68 for ; Sat, 21 Sep 2024 01:12:27 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sroeU-0003LQ-UO; Fri, 20 Sep 2024 21:11:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1srmWa-0003tD-1w for qemu-devel@nongnu.org; Fri, 20 Sep 2024 18:54:52 -0400 Received: from mail-4317.proton.ch ([185.70.43.17]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1srmWX-0004jn-FS for qemu-devel@nongnu.org; Fri, 20 Sep 2024 18:54:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nikitashushura.com; s=protonmail; t=1726872888; x=1727132088; bh=Xx6Js4iGgbGQOsO4T0rtRdX9oAdowWMajldiUEcOs1I=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=o8qyKHSm1PqigL7ok0iKJ9yjUmHTBribmNml/yQD4G8Fj9M+HWlwISQNOM5JNh9bL ri4G2TEKXgmiF+en/Z1YvEsOI638fedKO4XGiwNjKyBsbX6Y0wU7HxbcPPmKqsaET6 l8X5A5uTCogEpP5yKq06+lJ5sMXTEpaxiARGZZnbNz4a0289peNQgpexHaEeAG3f7a scybLofBi5XuaK7Ut7BGyCEF4z+FktnhtHdAmeDrR7wz5Ij7+8g/4NogQZdtT45NGj o14onKf5LTEAffRNHCsKdc97AP6mdmDfBof0/IO9t7M0yYS+OP6iiLOwembg/iPfe5 KN7h9k4Tka/dw== Date: Fri, 20 Sep 2024 22:54:44 +0000 To: qemu-devel@nongnu.org From: Nikita Shushura Cc: Nikita Shushura Subject: [PATCH 2/2] hw/sparc/leon3: add second uart with extended interrupt usage Message-ID: <20240920225401.69536-2-me@nikitashushura.com> In-Reply-To: <20240920225401.69536-1-me@nikitashushura.com> References: <20240920225401.69536-1-me@nikitashushura.com> Feedback-ID: 120968030:user:proton X-Pm-Message-ID: 2b0da8aaf0017b133cd68a9a4dee8f1c76b3bee1 MIME-Version: 1.0 Received-SPF: pass client-ip=185.70.43.17; envelope-from=me@nikitashushura.com; helo=mail-4317.proton.ch X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 20 Sep 2024 21:11:05 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Nikita Shushura --- hw/sparc/leon3.c | 63 +++++++++++++++++++++++++++++++++++------------- 1 file changed, 46 insertions(+), 17 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 6aaa04cb19..c559854e5e 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -54,10 +54,14 @@ #define LEON3_PROM_OFFSET (0x00000000) #define LEON3_RAM_OFFSET (0x40000000) -#define MAX_CPUS 4 +#define MAX_CPUS (4) +#define LEON3_EIRQ (12) -#define LEON3_UART_OFFSET (0x80000100) -#define LEON3_UART_IRQ (3) +#define LEON3_UART0_OFFSET (0x80000100) +#define LEON3_UART0_IRQ (2) + +#define LEON3_UART1_OFFSET (0x80100100) +#define LEON3_UART1_IRQ (17) #define LEON3_IRQMP_OFFSET (0x80000200) @@ -65,7 +69,8 @@ #define LEON3_TIMER_IRQ (6) #define LEON3_TIMER_COUNT (2) -#define LEON3_APB_PNP_OFFSET (0x800FF000) +#define LEON3_APB1_PNP_OFFSET (0x800FF000) +#define LEON3_APB2_PNP_OFFSET (0x801FF000) #define LEON3_AHB_PNP_OFFSET (0xFFFFF000) typedef struct ResetData { @@ -122,7 +127,8 @@ static void write_bootloader(void *ptr, hwaddr kernel_addr) /* Initialize the UARTs */ /* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */ - p = gen_store_u32(p, 0x80000108, 3); + p = gen_store_u32(p, LEON3_UART0_OFFSET + 0x8, 3); + p = gen_store_u32(p, LEON3_UART1_OFFSET + 0x8, 3); /* Initialize the TIMER 0 */ /* *GPTIMER_SCALER_RELOAD = 40 - 1; */ @@ -271,7 +277,8 @@ static void leon3_generic_hw_init(MachineState *machine) DeviceState *dev, *irqmpdev; int i; AHBPnp *ahb_pnp; - APBPnp *apb_pnp; + APBPnp *apb1_pnp; + APBPnp *apb2_pnp; reset_info = g_malloc0(sizeof(ResetData)); @@ -298,10 +305,19 @@ static void leon3_generic_hw_init(MachineState *machine) GRLIB_LEON3_DEV, GRLIB_AHB_MASTER, GRLIB_CPU_AREA); - apb_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP)); - sysbus_realize_and_unref(SYS_BUS_DEVICE(apb_pnp), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET); - grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF, + /* Initialize APB1 */ + apb1_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(apb1_pnp), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(apb1_pnp), 0, LEON3_APB1_PNP_OFFSET); + grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB1_PNP_OFFSET, 0xFFF, + GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV, + GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA); + + /* Initialize APB2 */ + apb2_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(apb2_pnp), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(apb2_pnp), 0, LEON3_APB2_PNP_OFFSET); + grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB2_PNP_OFFSET, 0xFFF, GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV, GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA); @@ -309,6 +325,8 @@ static void leon3_generic_hw_init(MachineState *machine) irqmpdev = qdev_new(TYPE_GRLIB_IRQMP); object_property_set_int(OBJECT(irqmpdev), "ncpus", machine->smp.cpus, &error_fatal); + /*object_property_set_int(OBJECT(irqmpdev), "eirq", LEON3_EIRQ,*/ + /* &error_fatal);*/ sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal); for (i = 0; i < machine->smp.cpus; i++) { @@ -325,7 +343,7 @@ static void leon3_generic_hw_init(MachineState *machine) } sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET); - grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF, + grlib_apb_pnp_add_entry(apb1_pnp, LEON3_IRQMP_OFFSET, 0xFFF, GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV, 2, 0, GRLIB_APBIO_AREA); @@ -417,20 +435,31 @@ static void leon3_generic_hw_init(MachineState *machine) qdev_get_gpio_in(irqmpdev, LEON3_TIMER_IRQ + i)); } - grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF, + grlib_apb_pnp_add_entry(apb1_pnp, LEON3_TIMER_OFFSET, 0xFFF, GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV, 0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA); - /* Allocate uart */ + /* Allocate UART0 */ dev = qdev_new(TYPE_GRLIB_APB_UART); qdev_prop_set_chr(dev, "chrdev", serial_hd(0)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART0_OFFSET); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, + qdev_get_gpio_in(irqmpdev, LEON3_UART0_IRQ)); + grlib_apb_pnp_add_entry(apb1_pnp, LEON3_UART0_OFFSET, 0xFFF, + GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1, + LEON3_UART0_IRQ, GRLIB_APBIO_AREA); + + /* Allocate UART1 */ + dev = qdev_new(TYPE_GRLIB_APB_UART); + qdev_prop_set_chr(dev, "chrdev", serial_hd(1)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART1_OFFSET); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, - qdev_get_gpio_in(irqmpdev, LEON3_UART_IRQ)); - grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF, + qdev_get_gpio_in(irqmpdev, LEON3_UART1_IRQ)); + grlib_apb_pnp_add_entry(apb1_pnp, LEON3_UART1_OFFSET, 0xFFF, GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1, - LEON3_UART_IRQ, GRLIB_APBIO_AREA); + LEON3_UART1_IRQ, GRLIB_APBIO_AREA); } static void leon3_generic_machine_init(MachineClass *mc)