From patchwork Mon Sep 23 15:24:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13809773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32D05CF9C74 for ; Mon, 23 Sep 2024 15:25:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DEA810E425; Mon, 23 Sep 2024 15:25:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ggTjwiZq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B7A410E41B; Mon, 23 Sep 2024 15:24:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727105099; x=1758641099; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7vuhyj4veHwH0xdFxLlDPcBUuP5lbuYNE3XmAVk43ZM=; b=ggTjwiZqxyf69jQiitCs30NQ0q/MWR1LeZkEyYP1w15H05hcuOh3cvuf JVn8MFZQWNAVW25eCdTYFeM5ARsrQqO2pt/+9wELDDBrCELEYCXPPMDBk /GG1E4c5YeswIzvMSuOqdHgyhgf3Xo2GnIbGJKs+5ycCR8gTG9FF76amP w7dZjW9fPkTjf+U5j2POmN1V6iVFmwTPQLymjgAe3v1S/CJY1FRme+H9f 5FIQ0cFlkA/lklZ8Th1kO8/r9ner8HEKxLTegOxXGrGvys8vQs0gCZCcm KrDs3CDSApuT9ZcMgO4uzqW6AqzFo0G2oUBPGOUV5qTHA89CAJRFxECve w==; X-CSE-ConnectionGUID: 7yPsnCEBR325g44YR4RPKw== X-CSE-MsgGUID: f3jCNGKMRL61ZZe2469pyA== X-IronPort-AV: E=McAfee;i="6700,10204,11204"; a="26013436" X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="26013436" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2024 08:24:59 -0700 X-CSE-ConnectionGUID: +l9U3A+TS06OFkAzzh3c7w== X-CSE-MsgGUID: kUoHc9+LQJyNUU2zv0W75w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="71239554" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 23 Sep 2024 08:24:57 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 23 Sep 2024 18:24:56 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH v2 1/6] drm/i915/bios: Use drm_dbg_kms() consistently Date: Mon, 23 Sep 2024 18:24:48 +0300 Message-ID: <20240923152453.11230-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240923152453.11230-1-ville.syrjala@linux.intel.com> References: <20240923152453.11230-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Replace the few oddball drm_dbg() calls in VBT related code with drm_dbg_kms() as that is what we generally use for all display code. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bios.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index daa4b9535123..b00aad23d6c2 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1706,8 +1706,8 @@ parse_mipi_config(struct intel_display *display, return; } - drm_dbg(display->drm, "Found MIPI Config block, panel index = %d\n", - panel_type); + drm_dbg_kms(display->drm, "Found MIPI Config block, panel index = %d\n", + panel_type); /* * get hold of the correct configuration block and pps data as per @@ -2067,8 +2067,8 @@ parse_mipi_sequence(struct intel_display *display, return; } - drm_dbg(display->drm, "Found MIPI sequence block v%u\n", - sequence->version); + drm_dbg_kms(display->drm, "Found MIPI sequence block v%u\n", + sequence->version); seq_data = find_panel_sequence_block(display, sequence, panel_type, &seq_size); if (!seq_data) @@ -2114,7 +2114,7 @@ parse_mipi_sequence(struct intel_display *display, fixup_mipi_sequences(display, panel); - drm_dbg(display->drm, "MIPI related VBT parsing complete\n"); + drm_dbg_kms(display->drm, "MIPI related VBT parsing complete\n"); return; err: @@ -2771,9 +2771,9 @@ static bool child_device_size_valid(struct intel_display *display, int size) expected_size = child_device_expected_size(display->vbt.version); if (expected_size < 0) { expected_size = sizeof(struct child_device_config); - drm_dbg(display->drm, - "Expected child device config size for VBT version %u not known; assuming %d\n", - display->vbt.version, expected_size); + drm_dbg_kms(display->drm, + "Expected child device config size for VBT version %u not known; assuming %d\n", + display->vbt.version, expected_size); } /* Flag an error for unexpected size, but continue anyway. */ @@ -3143,14 +3143,14 @@ static struct vbt_header *oprom_get_vbt(struct intel_display *display, goto err_unmap_oprom; if (sizeof(struct vbt_header) > size) { - drm_dbg(display->drm, "VBT header incomplete\n"); + drm_dbg_kms(display->drm, "VBT header incomplete\n"); goto err_unmap_oprom; } vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size)); if (vbt_size > size) { - drm_dbg(display->drm, - "VBT incomplete (vbt_size overflows)\n"); + drm_dbg_kms(display->drm, + "VBT incomplete (vbt_size overflows)\n"); goto err_unmap_oprom; } From patchwork Mon Sep 23 15:24:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13809774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A8CACF9C72 for ; Mon, 23 Sep 2024 15:25:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C998210E42E; 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X-CSE-ConnectionGUID: 38F3xkFGT9280bpqldGlbw== X-CSE-MsgGUID: xnTru7TjTTuiF1Iduss1LQ== X-IronPort-AV: E=McAfee;i="6700,10204,11204"; a="26013451" X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="26013451" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2024 08:25:02 -0700 X-CSE-ConnectionGUID: Tgo/g8uPRf6p5QVZnJOZ0w== X-CSE-MsgGUID: Q8fMuC6OTLKgl/Qbht6IYA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="71239664" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 23 Sep 2024 08:25:00 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 23 Sep 2024 18:24:59 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 2/6] drm/i915/bios: Add some size checks to SPI VBT read Date: Mon, 23 Sep 2024 18:24:49 +0300 Message-ID: <20240923152453.11230-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240923152453.11230-1-ville.syrjala@linux.intel.com> References: <20240923152453.11230-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Unify the SPI vs. PCI ROM VBT read codepaths a bit by pulling some size overflow checks from the PCI side into the SPI side. v2: s/drm_dbg()/drm_dbg_kms()/ Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bios.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index b00aad23d6c2..37f30bb76e08 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3088,11 +3088,22 @@ static struct vbt_header *spi_oprom_get_vbt(struct intel_display *display, if (count >= oprom_size) goto err_not_found; + if (sizeof(struct vbt_header) > oprom_size - count) { + drm_dbg_kms(display->drm, "VBT header incomplete\n"); + goto err_not_found; + } + /* Get VBT size and allocate space for the VBT */ vbt_size = intel_spi_read(&i915->uncore, found + offsetof(struct vbt_header, vbt_size)); vbt_size &= 0xffff; + if (vbt_size > oprom_size - count) { + drm_dbg_kms(display->drm, + "VBT incomplete (vbt_size overflows)\n"); + goto err_not_found; + } + vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL); if (!vbt) goto err_not_found; From patchwork Mon Sep 23 15:24:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13809775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BF27CF9C77 for ; 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X-CSE-ConnectionGUID: SP7aBMLaSKCFUOpx5qxRTw== X-CSE-MsgGUID: NtObWu+qR02AoyQhjk8e0w== X-IronPort-AV: E=McAfee;i="6700,10204,11204"; a="26013471" X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="26013471" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2024 08:25:05 -0700 X-CSE-ConnectionGUID: Xi0vFIX1Tj+znF6b1FTaLQ== X-CSE-MsgGUID: JJaf8vKCRga2cFIx40FaBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="71239776" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 23 Sep 2024 08:25:03 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 23 Sep 2024 18:25:02 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 3/6] drm/i915/bios: Round PCI ROM VBT allocation to multiple of 4 Date: Mon, 23 Sep 2024 18:24:50 +0300 Message-ID: <20240923152453.11230-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240923152453.11230-1-ville.syrjala@linux.intel.com> References: <20240923152453.11230-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The SPI code rounds the VBT allocation to a multiple of four bytes (presumably because it reads the VBT 4 bytes at a time). Do the same for the PCI ROM side to eliminate pointless differences between the two codepaths. This will make no functional difference. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 37f30bb76e08..d4281234773c 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3166,7 +3166,7 @@ static struct vbt_header *oprom_get_vbt(struct intel_display *display, } /* The rest will be validated by intel_bios_is_valid_vbt() */ - vbt = kmalloc(vbt_size, GFP_KERNEL); + vbt = kmalloc(round_up(vbt_size, 4), GFP_KERNEL); if (!vbt) goto err_unmap_oprom; From patchwork Mon Sep 23 15:24:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13809776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 62A54CF9C74 for ; Mon, 23 Sep 2024 15:25:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 04AC410E43E; Mon, 23 Sep 2024 15:25:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UfOT8zm1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE56510E430; Mon, 23 Sep 2024 15:25:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727105108; x=1758641108; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sR0O5d7hDN3AxBJ3a8L2d/6f1GVle1JkUCu2PZIa5v0=; b=UfOT8zm1PIIKAikQvdxF9AvFefRbO8yP9Eu15e34DEnvhYx4UvB1hL1J r8g6LSdzCKdT4OCu2hEMLZPtEfeCET2o+ntiMpjfAWNUGjkfNb7wixwGj 5OApRfR3Ebg9AkaXh5aY6PIZ02OzAdbHpYmC0YZ9JM1nJVHmG2CtMZhe3 8wu8j7rvTpqceu92Ysuazea97eb6h+DJlE42YGQidPnPpZXtTR+T77lgj /83wmrGpdoOaunUC3XHijk2qNU4/DMuEyiLrqb12L1/A8hSPtguK3iHlr L7Hg8hv419nyCrSBJ+OhrerlirTZS/xvbaYnomc1w4c7U30lXGdskwkH9 w==; X-CSE-ConnectionGUID: X9nfsbAxQE6Oq63c4ipRJQ== X-CSE-MsgGUID: nmN+UXPwTFmEY6M5+M3MzA== X-IronPort-AV: E=McAfee;i="6700,10204,11204"; a="26013480" X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="26013480" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2024 08:25:08 -0700 X-CSE-ConnectionGUID: Vcx7F8/pS3GZfu7uqdP1Hw== X-CSE-MsgGUID: FAjq39tlSYGATuV+8OekQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="71239838" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 23 Sep 2024 08:25:06 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 23 Sep 2024 18:25:05 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 4/6] drm/i915/bios: Extract intel_spi_read16() Date: Mon, 23 Sep 2024 18:24:51 +0300 Message-ID: <20240923152453.11230-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240923152453.11230-1-ville.syrjala@linux.intel.com> References: <20240923152453.11230-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The SPI VBT codepath only knows how to read 4 bytes at a time. So to read the 2 byte vbt_size it masks out the unwanted msbs. Hide that little implementation detail inside a new intel_spi_read16() helper. Alse rename the existing intel_spi_read() to intel_spi_read32() to make it clear what it does. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bios.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index d4281234773c..38ea92b4ff13 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3053,13 +3053,18 @@ static struct vbt_header *firmware_get_vbt(struct intel_display *display, return vbt; } -static u32 intel_spi_read(struct intel_uncore *uncore, u32 offset) +static u32 intel_spi_read32(struct intel_uncore *uncore, u32 offset) { intel_uncore_write(uncore, PRIMARY_SPI_ADDRESS, offset); return intel_uncore_read(uncore, PRIMARY_SPI_TRIGGER); } +static u16 intel_spi_read16(struct intel_uncore *uncore, u32 offset) +{ + return intel_spi_read32(uncore, offset) & 0xffff; +} + static struct vbt_header *spi_oprom_get_vbt(struct intel_display *display, size_t *size) { @@ -3078,7 +3083,7 @@ static struct vbt_header *spi_oprom_get_vbt(struct intel_display *display, oprom_offset &= OROM_OFFSET_MASK; for (count = 0; count < oprom_size; count += 4) { - data = intel_spi_read(&i915->uncore, oprom_offset + count); + data = intel_spi_read32(&i915->uncore, oprom_offset + count); if (data == *((const u32 *)"$VBT")) { found = oprom_offset + count; break; @@ -3094,9 +3099,8 @@ static struct vbt_header *spi_oprom_get_vbt(struct intel_display *display, } /* Get VBT size and allocate space for the VBT */ - vbt_size = intel_spi_read(&i915->uncore, - found + offsetof(struct vbt_header, vbt_size)); - vbt_size &= 0xffff; + vbt_size = intel_spi_read16(&i915->uncore, + found + offsetof(struct vbt_header, vbt_size)); if (vbt_size > oprom_size - count) { drm_dbg_kms(display->drm, @@ -3109,7 +3113,7 @@ static struct vbt_header *spi_oprom_get_vbt(struct intel_display *display, goto err_not_found; for (count = 0; count < vbt_size; count += 4) - *(vbt + store++) = intel_spi_read(&i915->uncore, found + count); + *(vbt + store++) = intel_spi_read32(&i915->uncore, found + count); if (!intel_bios_is_valid_vbt(display, vbt, vbt_size)) goto err_free_vbt; From patchwork Mon Sep 23 15:24:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13809777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BEB1CF9C74 for ; Mon, 23 Sep 2024 15:25:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E6EFB10E420; Mon, 23 Sep 2024 15:25:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EjPYoFY3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3BD3310E421; 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23 Sep 2024 08:25:12 -0700 X-CSE-ConnectionGUID: GcERdoXbT6mtQji1isKUPg== X-CSE-MsgGUID: ss6FHqC1SKe5v2+++3HnOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="71239920" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 23 Sep 2024 08:25:09 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 23 Sep 2024 18:25:08 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 5/6] drm/i915/bios: Extract vbt_signature[] Date: Mon, 23 Sep 2024 18:24:52 +0300 Message-ID: <20240923152453.11230-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240923152453.11230-1-ville.syrjala@linux.intel.com> References: <20240923152453.11230-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Replace the three hand rolled "$VBT"s with a vbt_signature[] to avoid accidents. v2: Include terminating '\0' for safety (Jani) Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bios.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 38ea92b4ff13..c57426940cf8 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2964,6 +2964,9 @@ static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) return _vbt + vbt->bdb_offset; } +static const char vbt_signature[] = "$VBT"; +static const int vbt_signature_len = 4; + /** * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT * @display: display device @@ -2986,7 +2989,7 @@ bool intel_bios_is_valid_vbt(struct intel_display *display, return false; } - if (memcmp(vbt->signature, "$VBT", 4)) { + if (memcmp(vbt->signature, vbt_signature, vbt_signature_len)) { drm_dbg_kms(display->drm, "VBT invalid signature\n"); return false; } @@ -3082,9 +3085,12 @@ static struct vbt_header *spi_oprom_get_vbt(struct intel_display *display, oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET); oprom_offset &= OROM_OFFSET_MASK; + BUILD_BUG_ON(vbt_signature_len != sizeof(vbt_signature) - 1); + BUILD_BUG_ON(vbt_signature_len != sizeof(u32)); + for (count = 0; count < oprom_size; count += 4) { data = intel_spi_read32(&i915->uncore, oprom_offset + count); - if (data == *((const u32 *)"$VBT")) { + if (data == *((const u32 *)vbt_signature)) { found = oprom_offset + count; break; } @@ -3144,9 +3150,12 @@ static struct vbt_header *oprom_get_vbt(struct intel_display *display, if (!oprom) return NULL; + BUILD_BUG_ON(vbt_signature_len != sizeof(vbt_signature) - 1); + BUILD_BUG_ON(vbt_signature_len != sizeof(u32)); + /* Scour memory looking for the VBT signature. */ for (i = 0; i + 4 < size; i += 4) { - if (ioread32(oprom + i) != *((const u32 *)"$VBT")) + if (ioread32(oprom + i) != *((const u32 *)vbt_signature)) continue; p = oprom + i; From patchwork Mon Sep 23 15:24:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13809778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4250ECF9C6F for ; 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X-CSE-ConnectionGUID: m5Gu0x6ySsq2XimDBjcKBA== X-CSE-MsgGUID: qwYr9CpJTJqpVg2wI5BDtA== X-IronPort-AV: E=McAfee;i="6700,10204,11204"; a="26013513" X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="26013513" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2024 08:25:15 -0700 X-CSE-ConnectionGUID: WqPubCsPRAq7aBOlMWMr9w== X-CSE-MsgGUID: RsqX0LwxTgy2Yih+XP1fcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,251,1719903600"; d="scan'208";a="71239981" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 23 Sep 2024 08:25:12 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 23 Sep 2024 18:25:12 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Jani Nikula Subject: [PATCH v2 6/6] drm/i915/bios: Extract soc/intel_rom.c Date: Mon, 23 Sep 2024 18:24:53 +0300 Message-ID: <20240923152453.11230-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240923152453.11230-1-ville.syrjala@linux.intel.com> References: <20240923152453.11230-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Abstract away the nuts and bolts of the SPI vs. PCI ROM stuff, and hide it all in soc/intel_rom.c so that the VBT code doesn't have to care about this stuff. This leaves intel_bios.c with a single codepath that can focus on the details related to the VBT layout. This should have no functional changes. v2: Rebase due to vbt_signature changes Drop unnecessary cast (Jani) Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/display/intel_bios.c | 149 +++------------- drivers/gpu/drm/i915/soc/intel_rom.c | 160 ++++++++++++++++++ drivers/gpu/drm/i915/soc/intel_rom.h | 25 +++ drivers/gpu/drm/xe/Makefile | 3 +- .../xe/compat-i915-headers/soc/intel_rom.h | 6 + 6 files changed, 223 insertions(+), 123 deletions(-) create mode 100644 drivers/gpu/drm/i915/soc/intel_rom.c create mode 100644 drivers/gpu/drm/i915/soc/intel_rom.h create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/soc/intel_rom.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 70771e521b1c..e033bcaef4f3 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -51,7 +51,8 @@ i915-y += \ i915-y += \ soc/intel_dram.o \ soc/intel_gmch.o \ - soc/intel_pch.o + soc/intel_pch.o \ + soc/intel_rom.o # core library code i915-y += \ diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index c57426940cf8..9967b65e3cf6 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -33,12 +33,12 @@ #include #include +#include "soc/intel_rom.h" + #include "i915_drv.h" -#include "i915_reg.h" #include "intel_display.h" #include "intel_display_types.h" #include "intel_gmbus.h" -#include "intel_uncore.h" #define _INTEL_BIOS_PRIVATE #include "intel_vbt_defs.h" @@ -3056,152 +3056,59 @@ static struct vbt_header *firmware_get_vbt(struct intel_display *display, return vbt; } -static u32 intel_spi_read32(struct intel_uncore *uncore, u32 offset) +static struct vbt_header *oprom_get_vbt(struct intel_display *display, + struct intel_rom *rom, + size_t *size, const char *type) { - intel_uncore_write(uncore, PRIMARY_SPI_ADDRESS, offset); + struct vbt_header *vbt; + size_t vbt_size; + loff_t offset; - return intel_uncore_read(uncore, PRIMARY_SPI_TRIGGER); -} - -static u16 intel_spi_read16(struct intel_uncore *uncore, u32 offset) -{ - return intel_spi_read32(uncore, offset) & 0xffff; -} - -static struct vbt_header *spi_oprom_get_vbt(struct intel_display *display, - size_t *size) -{ - struct drm_i915_private *i915 = to_i915(display->drm); - u32 count, data, found, store = 0; - u32 static_region, oprom_offset; - u32 oprom_size = 0x200000; - u16 vbt_size; - u32 *vbt; - - static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS); - static_region &= OPTIONROM_SPI_REGIONID_MASK; - intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region); - - oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET); - oprom_offset &= OROM_OFFSET_MASK; + if (!rom) + return NULL; BUILD_BUG_ON(vbt_signature_len != sizeof(vbt_signature) - 1); BUILD_BUG_ON(vbt_signature_len != sizeof(u32)); - for (count = 0; count < oprom_size; count += 4) { - data = intel_spi_read32(&i915->uncore, oprom_offset + count); - if (data == *((const u32 *)vbt_signature)) { - found = oprom_offset + count; - break; - } - } + offset = intel_rom_find(rom, *(const u32 *)vbt_signature); + if (offset < 0) + goto err_free_rom; - if (count >= oprom_size) - goto err_not_found; - - if (sizeof(struct vbt_header) > oprom_size - count) { + if (sizeof(struct vbt_header) > intel_rom_size(rom) - offset) { drm_dbg_kms(display->drm, "VBT header incomplete\n"); - goto err_not_found; + goto err_free_rom; } - /* Get VBT size and allocate space for the VBT */ - vbt_size = intel_spi_read16(&i915->uncore, - found + offsetof(struct vbt_header, vbt_size)); + BUILD_BUG_ON(sizeof(vbt->vbt_size) != sizeof(u16)); - if (vbt_size > oprom_size - count) { - drm_dbg_kms(display->drm, - "VBT incomplete (vbt_size overflows)\n"); - goto err_not_found; + vbt_size = intel_rom_read16(rom, offset + offsetof(struct vbt_header, vbt_size)); + if (vbt_size > intel_rom_size(rom) - offset) { + drm_dbg_kms(display->drm, "VBT incomplete (vbt_size overflows)\n"); + goto err_free_rom; } vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL); if (!vbt) - goto err_not_found; + goto err_free_rom; - for (count = 0; count < vbt_size; count += 4) - *(vbt + store++) = intel_spi_read32(&i915->uncore, found + count); + intel_rom_read_block(rom, vbt, offset, vbt_size); if (!intel_bios_is_valid_vbt(display, vbt, vbt_size)) goto err_free_vbt; - drm_dbg_kms(display->drm, "Found valid VBT in SPI flash\n"); + drm_dbg_kms(display->drm, "Found valid VBT in %s\n", type); if (size) *size = vbt_size; - return (struct vbt_header *)vbt; - -err_free_vbt: - kfree(vbt); -err_not_found: - return NULL; -} - -static struct vbt_header *oprom_get_vbt(struct intel_display *display, - size_t *sizep) -{ - struct pci_dev *pdev = to_pci_dev(display->drm->dev); - void __iomem *p = NULL, *oprom; - struct vbt_header *vbt; - u16 vbt_size; - size_t i, size; - - oprom = pci_map_rom(pdev, &size); - if (!oprom) - return NULL; - - BUILD_BUG_ON(vbt_signature_len != sizeof(vbt_signature) - 1); - BUILD_BUG_ON(vbt_signature_len != sizeof(u32)); - - /* Scour memory looking for the VBT signature. */ - for (i = 0; i + 4 < size; i += 4) { - if (ioread32(oprom + i) != *((const u32 *)vbt_signature)) - continue; - - p = oprom + i; - size -= i; - break; - } - - if (!p) - goto err_unmap_oprom; - - if (sizeof(struct vbt_header) > size) { - drm_dbg_kms(display->drm, "VBT header incomplete\n"); - goto err_unmap_oprom; - } - - vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size)); - if (vbt_size > size) { - drm_dbg_kms(display->drm, - "VBT incomplete (vbt_size overflows)\n"); - goto err_unmap_oprom; - } - - /* The rest will be validated by intel_bios_is_valid_vbt() */ - vbt = kmalloc(round_up(vbt_size, 4), GFP_KERNEL); - if (!vbt) - goto err_unmap_oprom; - - memcpy_fromio(vbt, p, vbt_size); - - if (!intel_bios_is_valid_vbt(display, vbt, vbt_size)) - goto err_free_vbt; - - pci_unmap_rom(pdev, oprom); - - if (sizep) - *sizep = vbt_size; - - drm_dbg_kms(display->drm, "Found valid VBT in PCI ROM\n"); + intel_rom_free(rom); return vbt; err_free_vbt: kfree(vbt); -err_unmap_oprom: - pci_unmap_rom(pdev, oprom); - +err_free_rom: + intel_rom_free(rom); return NULL; } @@ -3223,11 +3130,11 @@ static const struct vbt_header *intel_bios_get_vbt(struct intel_display *display */ if (!vbt && IS_DGFX(i915)) with_intel_runtime_pm(&i915->runtime_pm, wakeref) - vbt = spi_oprom_get_vbt(display, sizep); + vbt = oprom_get_vbt(display, intel_rom_spi(i915), sizep, "SPI flash"); if (!vbt) with_intel_runtime_pm(&i915->runtime_pm, wakeref) - vbt = oprom_get_vbt(display, sizep); + vbt = oprom_get_vbt(display, intel_rom_pci(i915), sizep, "PCI ROM"); return vbt; } diff --git a/drivers/gpu/drm/i915/soc/intel_rom.c b/drivers/gpu/drm/i915/soc/intel_rom.c new file mode 100644 index 000000000000..243d98cab8c3 --- /dev/null +++ b/drivers/gpu/drm/i915/soc/intel_rom.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#include "i915_drv.h" +#include "i915_reg.h" + +#include "intel_rom.h" +#include "intel_uncore.h" + +struct intel_rom { + /* for PCI ROM */ + struct pci_dev *pdev; + void __iomem *oprom; + + /* for SPI */ + struct intel_uncore *uncore; + loff_t offset; + + size_t size; + + u32 (*read32)(struct intel_rom *rom, loff_t offset); + u16 (*read16)(struct intel_rom *rom, loff_t offset); + void (*read_block)(struct intel_rom *rom, void *data, loff_t offset, size_t size); + void (*free)(struct intel_rom *rom); +}; + +static u32 spi_read32(struct intel_rom *rom, loff_t offset) +{ + intel_uncore_write(rom->uncore, PRIMARY_SPI_ADDRESS, + rom->offset + offset); + + return intel_uncore_read(rom->uncore, PRIMARY_SPI_TRIGGER); +} + +static u16 spi_read16(struct intel_rom *rom, loff_t offset) +{ + return spi_read32(rom, offset) & 0xffff; +} + +struct intel_rom *intel_rom_spi(struct drm_i915_private *i915) +{ + struct intel_rom *rom; + u32 static_region; + + rom = kzalloc(sizeof(*rom), GFP_KERNEL); + if (!rom) + return NULL; + + rom->uncore = &i915->uncore; + + static_region = intel_uncore_read(rom->uncore, SPI_STATIC_REGIONS); + static_region &= OPTIONROM_SPI_REGIONID_MASK; + intel_uncore_write(rom->uncore, PRIMARY_SPI_REGIONID, static_region); + + rom->offset = intel_uncore_read(rom->uncore, OROM_OFFSET) & OROM_OFFSET_MASK; + + rom->size = 0x200000; + + rom->read32 = spi_read32; + rom->read16 = spi_read16; + + return rom; +} + +static u32 pci_read32(struct intel_rom *rom, loff_t offset) +{ + return ioread32(rom->oprom + offset); +} + +static u16 pci_read16(struct intel_rom *rom, loff_t offset) +{ + return ioread16(rom->oprom + offset); +} + +static void pci_read_block(struct intel_rom *rom, void *data, + loff_t offset, size_t size) +{ + memcpy_fromio(data, rom->oprom + offset, size); +} + +static void pci_free(struct intel_rom *rom) +{ + pci_unmap_rom(rom->pdev, rom->oprom); +} + +struct intel_rom *intel_rom_pci(struct drm_i915_private *i915) +{ + struct intel_rom *rom; + + rom = kzalloc(sizeof(*rom), GFP_KERNEL); + if (!rom) + return NULL; + + rom->pdev = to_pci_dev(i915->drm.dev); + + rom->oprom = pci_map_rom(rom->pdev, &rom->size); + if (!rom->oprom) { + kfree(rom); + return NULL; + } + + rom->read32 = pci_read32; + rom->read16 = pci_read16; + rom->read_block = pci_read_block; + rom->free = pci_free; + + return rom; +} + +u32 intel_rom_read32(struct intel_rom *rom, loff_t offset) +{ + return rom->read32(rom, offset); +} + +u16 intel_rom_read16(struct intel_rom *rom, loff_t offset) +{ + return rom->read16(rom, offset); +} + +void intel_rom_read_block(struct intel_rom *rom, void *data, + loff_t offset, size_t size) +{ + u32 *ptr = data; + loff_t index; + + if (rom->read_block) { + rom->read_block(rom, data, offset, size); + return; + } + + for (index = 0; index < size; index += 4) + *ptr++ = rom->read32(rom, offset + index); +} + +loff_t intel_rom_find(struct intel_rom *rom, u32 needle) +{ + loff_t offset; + + for (offset = 0; offset < rom->size; offset += 4) { + if (rom->read32(rom, offset) == needle) + return offset; + } + + return -ENOENT; +} + +size_t intel_rom_size(struct intel_rom *rom) +{ + return rom->size; +} + +void intel_rom_free(struct intel_rom *rom) +{ + if (rom && rom->free) + rom->free(rom); + + kfree(rom); +} diff --git a/drivers/gpu/drm/i915/soc/intel_rom.h b/drivers/gpu/drm/i915/soc/intel_rom.h new file mode 100644 index 000000000000..fb2979c8ef7f --- /dev/null +++ b/drivers/gpu/drm/i915/soc/intel_rom.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_ROM_H__ +#define __INTEL_ROM_H__ + +#include + +struct drm_i915_private; +struct intel_rom; + +struct intel_rom *intel_rom_spi(struct drm_i915_private *i915); +struct intel_rom *intel_rom_pci(struct drm_i915_private *i915); + +u32 intel_rom_read32(struct intel_rom *rom, loff_t offset); +u16 intel_rom_read16(struct intel_rom *rom, loff_t offset); +void intel_rom_read_block(struct intel_rom *rom, void *data, + loff_t offset, size_t size); +loff_t intel_rom_find(struct intel_rom *rom, u32 needle); +size_t intel_rom_size(struct intel_rom *rom); +void intel_rom_free(struct intel_rom *rom); + +#endif /* __INTEL_ROM_H__ */ diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 1122765c711d..26cd21bc7189 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -181,7 +181,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ # SOC code shared with i915 xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-soc/intel_dram.o \ - i915-soc/intel_pch.o + i915-soc/intel_pch.o \ + i915-soc/intel_rom.o # Display code shared with i915 xe-$(CONFIG_DRM_XE_DISPLAY) += \ diff --git a/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_rom.h b/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_rom.h new file mode 100644 index 000000000000..05cbfb697b2b --- /dev/null +++ b/drivers/gpu/drm/xe/compat-i915-headers/soc/intel_rom.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#include "../../../i915/soc/intel_rom.h"