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Document them. Signed-off-by: Shivnandan Kumar --- .../devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index f7342d04beec..4a7ea072a3c1 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -15,8 +15,9 @@ description: properties: compatible: - items: - - const: qcom,x1e80100-cpucp-mbox + enum: + - qcom,x1e80100-cpucp-mbox + - qcom,sc7280-cpucp-mbox reg: items: From patchwork Tue Sep 24 05:09:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shivnandan Kumar X-Patchwork-Id: 13810110 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 049EB45C1C; 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Tue, 24 Sep 2024 05:11:59 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48O5BwHN011907 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Sep 2024 05:11:58 GMT Received: from hu-kshivnan-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 23 Sep 2024 22:11:54 -0700 From: Shivnandan Kumar To: Sibi Sankar , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , , Bjorn Andersson , Konrad Dybcio CC: , , , Ramakrishna Gottimukkula , Shivnandan Kumar Subject: [PATCH 2/3] mailbox: qcom-cpucp-mbox: Add support for SC7280 CPUCP mailbox controller Date: Tue, 24 Sep 2024 10:39:40 +0530 Message-ID: <20240924050941.1251485-3-quic_kshivnan@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240924050941.1251485-1-quic_kshivnan@quicinc.com> References: <20240924050941.1251485-1-quic_kshivnan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 66CTGxjBCzYDSgsLKTrifceN5LtkU4mR X-Proofpoint-ORIG-GUID: 66CTGxjBCzYDSgsLKTrifceN5LtkU4mR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 mlxscore=0 phishscore=0 suspectscore=0 impostorscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409240033 The SC7280 CPUCP mailbox controller is compatible with legacy mailbox hardware. Implement support for this functionality which enable HLOS to CPUCP communication. Signed-off-by: Shivnandan Kumar --- drivers/mailbox/qcom-cpucp-mbox.c | 156 +++++++++++++++++++++++------- 1 file changed, 122 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c index e5437c294803..faae6e069ea1 100644 --- a/drivers/mailbox/qcom-cpucp-mbox.c +++ b/drivers/mailbox/qcom-cpucp-mbox.c @@ -13,18 +13,24 @@ #include #define APSS_CPUCP_IPC_CHAN_SUPPORTED 3 -#define APSS_CPUCP_MBOX_CMD_OFF 0x4 - -/* Tx Registers */ -#define APSS_CPUCP_TX_MBOX_CMD(i) (0x100 + ((i) * 8)) /* Rx Registers */ -#define APSS_CPUCP_RX_MBOX_CMD(i) (0x100 + ((i) * 8)) -#define APSS_CPUCP_RX_MBOX_MAP 0x4000 -#define APSS_CPUCP_RX_MBOX_STAT 0x4400 -#define APSS_CPUCP_RX_MBOX_CLEAR 0x4800 -#define APSS_CPUCP_RX_MBOX_EN 0x4c00 -#define APSS_CPUCP_RX_MBOX_CMD_MASK GENMASK_ULL(63, 0) +#define APSS_CPUCP_V2_RX_MBOX_CMD_MASK GENMASK_ULL(63, 0) +#define APSS_CPUCP_V1_SEND_IRQ_VAL BIT(28) +#define APSS_CPUCP_V1_CLEAR_IRQ_VAL BIT(3) +#define APSS_CPUCP_V1_STATUS_IRQ_VAL BIT(3) + +struct qcom_cpucp_mbox_desc { + u32 enable_reg; + u32 map_reg; + u32 rx_reg; + u32 tx_reg; + u32 status_reg; + u32 clear_reg; + u32 chan_stride; + bool v2_mbox; + u32 num_chans; +}; /** * struct qcom_cpucp_mbox - Holder for the mailbox driver @@ -35,6 +41,7 @@ */ struct qcom_cpucp_mbox { struct mbox_chan chans[APSS_CPUCP_IPC_CHAN_SUPPORTED]; + const struct qcom_cpucp_mbox_desc *desc; struct mbox_controller mbox; void __iomem *tx_base; void __iomem *rx_base; @@ -48,13 +55,40 @@ static inline int channel_number(struct mbox_chan *chan) static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) { struct qcom_cpucp_mbox *cpucp = data; + const struct qcom_cpucp_mbox_desc *desc = cpucp->desc; + int i; + + for (i = 0; i < desc->num_chans; i++) { + u32 val = readl(cpucp->rx_base + desc->status_reg + (i * desc->chan_stride)); + struct mbox_chan *chan = &cpucp->chans[i]; + unsigned long flags; + + if (val & APSS_CPUCP_V1_STATUS_IRQ_VAL) { + writel(APSS_CPUCP_V1_CLEAR_IRQ_VAL, + cpucp->rx_base + desc->clear_reg + (i * desc->chan_stride)); + /* Make sure reg write is complete before proceeding */ + mb(); + spin_lock_irqsave(&chan->lock, flags); + if (chan->cl) + mbox_chan_received_data(chan, NULL); + spin_unlock_irqrestore(&chan->lock, flags); + } + } + + return IRQ_HANDLED; +} + +static irqreturn_t qcom_cpucp_v2_mbox_irq_fn(int irq, void *data) +{ + struct qcom_cpucp_mbox *cpucp = data; + const struct qcom_cpucp_mbox_desc *desc = cpucp->desc; u64 status; int i; - status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); + status = readq(cpucp->rx_base + desc->status_reg); - for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN_SUPPORTED) { - u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); + for_each_set_bit(i, (unsigned long *)&status, desc->num_chans) { + u32 val = readl(cpucp->rx_base + desc->rx_reg + (i * desc->chan_stride)); struct mbox_chan *chan = &cpucp->chans[i]; unsigned long flags; @@ -62,7 +96,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) spin_lock_irqsave(&chan->lock, flags); if (chan->cl) mbox_chan_received_data(chan, &val); - writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); + writeq(BIT(i), cpucp->rx_base + desc->clear_reg); spin_unlock_irqrestore(&chan->lock, flags); } @@ -72,12 +106,15 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) static int qcom_cpucp_mbox_startup(struct mbox_chan *chan) { struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox); + const struct qcom_cpucp_mbox_desc *desc = cpucp->desc; unsigned long chan_id = channel_number(chan); u64 val; - val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); - val |= BIT(chan_id); - writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + if (desc->v2_mbox) { + val = readq(cpucp->rx_base + desc->enable_reg); + val |= BIT(chan_id); + writeq(val, cpucp->rx_base + desc->enable_reg); + } return 0; } @@ -85,22 +122,26 @@ static int qcom_cpucp_mbox_startup(struct mbox_chan *chan) static void qcom_cpucp_mbox_shutdown(struct mbox_chan *chan) { struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox); + const struct qcom_cpucp_mbox_desc *desc = cpucp->desc; unsigned long chan_id = channel_number(chan); u64 val; - val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); - val &= ~BIT(chan_id); - writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + if (desc->v2_mbox) { + val = readq(cpucp->rx_base + desc->enable_reg); + val &= ~BIT(chan_id); + writeq(val, cpucp->rx_base + desc->enable_reg); + } } static int qcom_cpucp_mbox_send_data(struct mbox_chan *chan, void *data) { struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox); + const struct qcom_cpucp_mbox_desc *desc = cpucp->desc; + u32 val = desc->v2_mbox ? *(u32 *)data : APSS_CPUCP_V1_SEND_IRQ_VAL; unsigned long chan_id = channel_number(chan); - u32 *val = data; - - writel(*val, cpucp->tx_base + APSS_CPUCP_TX_MBOX_CMD(chan_id) + APSS_CPUCP_MBOX_CMD_OFF); + u32 offset = desc->v2_mbox ? (chan_id * desc->chan_stride) : 0; + writel(val, cpucp->tx_base + desc->tx_reg + offset); return 0; } @@ -112,41 +153,66 @@ static const struct mbox_chan_ops qcom_cpucp_mbox_chan_ops = { static int qcom_cpucp_mbox_probe(struct platform_device *pdev) { + const struct qcom_cpucp_mbox_desc *desc; struct device *dev = &pdev->dev; struct qcom_cpucp_mbox *cpucp; struct mbox_controller *mbox; + struct resource *res; int irq, ret; + desc = device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + cpucp = devm_kzalloc(dev, sizeof(*cpucp), GFP_KERNEL); if (!cpucp) return -ENOMEM; - cpucp->rx_base = devm_of_iomap(dev, dev->of_node, 0, NULL); - if (IS_ERR(cpucp->rx_base)) - return PTR_ERR(cpucp->rx_base); + cpucp->desc = desc; + + if (desc->v2_mbox) { + cpucp->rx_base = devm_of_iomap(dev, dev->of_node, 0, NULL); + if (IS_ERR(cpucp->rx_base)) + return PTR_ERR(cpucp->rx_base); + /* Legacy mailbox quirks due to shared region with EPSS register space */ + } else { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "Failed to get the device base address\n"); + return -ENODEV; + } + cpucp->rx_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!cpucp->rx_base) { + dev_err(dev, "Failed to ioremap the cpucp rx irq addr\n"); + return -ENOMEM; + } + } cpucp->tx_base = devm_of_iomap(dev, dev->of_node, 1, NULL); if (IS_ERR(cpucp->tx_base)) return PTR_ERR(cpucp->tx_base); - writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); - writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); - writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP); + if (desc->v2_mbox) { + writeq(0, cpucp->rx_base + desc->enable_reg); + writeq(0, cpucp->rx_base + desc->clear_reg); + writeq(0, cpucp->rx_base + desc->map_reg); + } irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; - ret = devm_request_irq(dev, irq, qcom_cpucp_mbox_irq_fn, - IRQF_TRIGGER_HIGH, "apss_cpucp_mbox", cpucp); + ret = devm_request_irq(dev, irq, desc->v2_mbox ? qcom_cpucp_v2_mbox_irq_fn : + qcom_cpucp_mbox_irq_fn, IRQF_TRIGGER_HIGH, "apss_cpucp_mbox", cpucp); if (ret < 0) return dev_err_probe(dev, ret, "Failed to register irq: %d\n", irq); - writeq(APSS_CPUCP_RX_MBOX_CMD_MASK, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP); + if (desc->v2_mbox) + writeq(APSS_CPUCP_V2_RX_MBOX_CMD_MASK, cpucp->rx_base + desc->map_reg); mbox = &cpucp->mbox; mbox->dev = dev; - mbox->num_chans = APSS_CPUCP_IPC_CHAN_SUPPORTED; + mbox->num_chans = desc->num_chans; mbox->chans = cpucp->chans; mbox->ops = &qcom_cpucp_mbox_chan_ops; @@ -157,8 +223,30 @@ static int qcom_cpucp_mbox_probe(struct platform_device *pdev) return 0; } +static const struct qcom_cpucp_mbox_desc sc7280_cpucp_mbox = { + .tx_reg = 0xC, + .chan_stride = 0x1000, + .status_reg = 0x30C, + .clear_reg = 0x308, + .v2_mbox = false, + .num_chans = 2, +}; + +static const struct qcom_cpucp_mbox_desc x1e80100_cpucp_mbox = { + .rx_reg = 0x104, + .tx_reg = 0x104, + .chan_stride = 0x8, + .map_reg = 0x4000, + .status_reg = 0x4400, + .clear_reg = 0x4800, + .enable_reg = 0x4C00, + .v2_mbox = true, + .num_chans = 3, +}; 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Tue, 24 Sep 2024 05:12:05 GMT Received: from hu-kshivnan-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 23 Sep 2024 22:12:01 -0700 From: Shivnandan Kumar To: Sibi Sankar , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , , Bjorn Andersson , Konrad Dybcio CC: , , , Ramakrishna Gottimukkula , Shivnandan Kumar Subject: [PATCH 3/3] arm64: dts: qcom: sc7280: Add cpucp mbox node Date: Tue, 24 Sep 2024 10:39:41 +0530 Message-ID: <20240924050941.1251485-4-quic_kshivnan@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240924050941.1251485-1-quic_kshivnan@quicinc.com> References: <20240924050941.1251485-1-quic_kshivnan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5VluUoa7tBpd_AUdoi1vJB0jHoZSDy83 X-Proofpoint-ORIG-GUID: 5VluUoa7tBpd_AUdoi1vJB0jHoZSDy83 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 adultscore=0 phishscore=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409240033 Add the CPUCP mailbox node required for communication with CPUCP. Signed-off-by: Shivnandan Kumar --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.25.1 diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3d8410683402..4b9b26a75c62 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4009,6 +4009,14 @@ gem_noc: interconnect@9100000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + cpucp_mbox: mailbox@17430000 { + compatible = "qcom,sc7280-cpucp-mbox"; + reg = <0 0x18590000 0 0x2000>, + <0 0x17C00000 0 0x10>; + interrupts = ; + #mbox-cells = <1>; + }; + system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,