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[61.220.246.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20af1821f33sm10678895ad.219.2024.09.24.07.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2024 07:04:23 -0700 (PDT) From: Yang Chen To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au, andrew@codeconstruct.com.au, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, patrick@stwcx.xyz, amithash@meta.com Cc: Jerry.Lin@quantatw.com, yangchen.openbmc@gmail.com Subject: [PATCH v1 1/3] ARM: dts: aspeed: minerva: Revise the SGPIO line name Date: Tue, 24 Sep 2024 22:02:13 +0800 Message-Id: <20240924140215.2484170-2-yangchen.openbmc@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240924140215.2484170-1-yangchen.openbmc@gmail.com> References: <20240924140215.2484170-1-yangchen.openbmc@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240924_070425_996402_D837FCA3 X-CRM114-Status: GOOD ( 10.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Modify the SGPIO line names sent from the CMM CPLD in the DVT version and map the blade and FCB numbers to match the silkscreen labels on the rack as follows: 1. Change the compute blade numbering from 0-15 to 1-16. 2. Change the network blade numbering from 0-5 to 1-6. 3. Update the FCB numbering from TOP0/1, MID0/1, and BOT0/1 to FCB1-6. 4. Revise the SGPIO line name for DVT changed. Signed-off-by: Yang Chen --- .../aspeed/aspeed-bmc-facebook-minerva.dts | 110 +++++++++--------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts index 41e2246cfbd1..38eb42aaa98b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts @@ -627,7 +627,6 @@ &sgpiom0 { gpio-line-names = /*"input pin","output pin"*/ /*A0 - A7*/ - "PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN_N", "PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN_N", "PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN_N", "PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN_N", @@ -635,8 +634,8 @@ &sgpiom0 { "PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN_N", "PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN_N", "PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN_N", - /*B0 - B7*/ "PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN_N", + /*B0 - B7*/ "PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN_N", "PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN_N", "PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN_N", @@ -644,80 +643,80 @@ &sgpiom0 { "PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN_N", "PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN_N", "PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN_N", + "PRSNT_MTIA_BLADE16_N","PWREN_MTIA_BLADE16_EN_N", /*C0 - C7*/ - "PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN_N", "PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN_N", "PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN_N", "PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN_N", "PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN_N", "PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN_N", - "PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN_N", - "PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN_N", + "PRSNT_NW_BLADE6_N","PWREN_NW_BLADE6_EN_N", + "PRSNT_FCB_1_N","PWREN_MTIA_BLADE1_HSC_EN_N", + "PRSNT_FCB_2_N","PWREN_MTIA_BLADE2_HSC_EN_N", /*D0 - D7*/ - "PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN_N", - "PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN_N", - "PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE4_HSC_EN_N", - "PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE5_HSC_EN_N", - "PWRGD_MTIA_BLADE0_PWROK_N","PWREN_MTIA_BLADE6_HSC_EN_N", + "PRSNT_FCB_3_N","PWREN_MTIA_BLADE3_HSC_EN_N", + "PRSNT_FCB_4_N","PWREN_MTIA_BLADE4_HSC_EN_N", + "PRSNT_FCB_6_N","PWREN_MTIA_BLADE5_HSC_EN_N", + "PRSNT_FCB_5_N","PWREN_MTIA_BLADE6_HSC_EN_N", "PWRGD_MTIA_BLADE1_PWROK_N","PWREN_MTIA_BLADE7_HSC_EN_N", "PWRGD_MTIA_BLADE2_PWROK_N","PWREN_MTIA_BLADE8_HSC_EN_N", "PWRGD_MTIA_BLADE3_PWROK_N","PWREN_MTIA_BLADE9_HSC_EN_N", - /*E0 - E7*/ "PWRGD_MTIA_BLADE4_PWROK_N","PWREN_MTIA_BLADE10_HSC_EN_N", + /*E0 - E7*/ "PWRGD_MTIA_BLADE5_PWROK_N","PWREN_MTIA_BLADE11_HSC_EN_N", "PWRGD_MTIA_BLADE6_PWROK_N","PWREN_MTIA_BLADE12_HSC_EN_N", "PWRGD_MTIA_BLADE7_PWROK_N","PWREN_MTIA_BLADE13_HSC_EN_N", "PWRGD_MTIA_BLADE8_PWROK_N","PWREN_MTIA_BLADE14_HSC_EN_N", "PWRGD_MTIA_BLADE9_PWROK_N","PWREN_MTIA_BLADE15_HSC_EN_N", - "PWRGD_MTIA_BLADE10_PWROK_N","PWREN_NW_BLADE0_HSC_EN_N", + "PWRGD_MTIA_BLADE10_PWROK_N","PWREN_MTIA_BLADE16_HSC_EN_N", "PWRGD_MTIA_BLADE11_PWROK_N","PWREN_NW_BLADE1_HSC_EN_N", - /*F0 - F7*/ "PWRGD_MTIA_BLADE12_PWROK_N","PWREN_NW_BLADE2_HSC_EN_N", + /*F0 - F7*/ "PWRGD_MTIA_BLADE13_PWROK_N","PWREN_NW_BLADE3_HSC_EN_N", "PWRGD_MTIA_BLADE14_PWROK_N","PWREN_NW_BLADE4_HSC_EN_N", "PWRGD_MTIA_BLADE15_PWROK_N","PWREN_NW_BLADE5_HSC_EN_N", - "PWRGD_NW_BLADE0_PWROK_N","PWREN_FCB_TOP_0_EN_N", - "PWRGD_NW_BLADE1_PWROK_N","PWREN_FCB_TOP_1_EN_N", - "PWRGD_NW_BLADE2_PWROK_N","PWREN_FCB_MIDDLE_0_EN_N", - "PWRGD_NW_BLADE3_PWROK_N","PWREN_FCB_MIDDLE_1_EN_N", + "PWRGD_MTIA_BLADE16_PWROK_N","PWREN_NW_BLADE6_HSC_EN_N", + "PWRGD_NW_BLADE1_PWROK_N","PWREN_SGPIO_FCB_2_EN_N", + "PWRGD_NW_BLADE2_PWROK_N","PWREN_SGPIO_FCB_1_EN_N", + "PWRGD_NW_BLADE3_PWROK_N","PWREN_SGPIO_FCB_4_EN_N", + "PWRGD_NW_BLADE4_PWROK_N","PWREN_SGPIO_FCB_3_EN_N", /*G0 - G7*/ - "PWRGD_NW_BLADE4_PWROK_N","PWREN_FCB_BOTTOM_1_EN_N", - "PWRGD_NW_BLADE5_PWROK_N","PWREN_FCB_BOTTOM_0_EN_N", - "PWRGD_FCB_TOP_0_PWROK_N","FM_CMM_AC_CYCLE_N", - "PWRGD_FCB_TOP_1_PWROK_N","MGMT_SFP_TX_DIS", - "PWRGD_FCB_MIDDLE_0_PWROK_N","FM_MDIO_SW_SEL", - "PWRGD_FCB_MIDDLE_1_PWROK_N","FM_P24V_SMPWR_EN", - "PWRGD_FCB_BOTTOM_1_PWROK_N","", - "PWRGD_FCB_BOTTOM_0_PWROK_N","", + "PWRGD_NW_BLADE5_PWROK_N","PWREN_SGPIO_FCB_5_EN_N", + "PWRGD_NW_BLADE6_PWROK_N","PWREN_SGPIO_FCB_6_EN_N", + "PWRGD_FCB_1","FM_BMC_RST_RTCRST_R", + "PWRGD_FCB_2","", + "PWRGD_FCB_3","FM_MDIO_SW_SEL", + "PWRGD_FCB_4","FM_P24V_SMPWR_EN", + "PWRGD_FCB_6","", + "PWRGD_FCB_5","", /*H0 - H7*/ - "LEAK_DETECT_MTIA_BLADE0_N","", "LEAK_DETECT_MTIA_BLADE1_N","", "LEAK_DETECT_MTIA_BLADE2_N","", "LEAK_DETECT_MTIA_BLADE3_N","", "LEAK_DETECT_MTIA_BLADE4_N","", "LEAK_DETECT_MTIA_BLADE5_N","", "LEAK_DETECT_MTIA_BLADE6_N","", - "LEAK_DETECT_MTIA_BLADE7_N","", + "LEAK_DETECT_MTIA_BLADE7_N","ERR_INJECT_CMM_PWR_FAIL_N", + "LEAK_DETECT_MTIA_BLADE8_N","", /*I0 - I7*/ - "LEAK_DETECT_MTIA_BLADE8_N","RST_I2CRST_FCB_BOTTOM_1_N", - "LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_BOTTOM_0_N", - "LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_MIDDLE_0_N", - "LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_MIDDLE_1_N", - "LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_TOP_0_N", - "LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_TOP_1_N", - "LEAK_DETECT_MTIA_BLADE14_N","BMC_READY", - "LEAK_DETECT_MTIA_BLADE15_N","FM_88E6393X_BIN_UPDATE_EN_N", + "LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_5_N", + "LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_6_N", + "LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_4_N", + "LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_3_N", + "LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_2_N", + "LEAK_DETECT_MTIA_BLADE14_N","RST_I2CRST_FCB_1_N", + "LEAK_DETECT_MTIA_BLADE15_N","BMC_READY", + "LEAK_DETECT_MTIA_BLADE16_N","FM_88E6393X_BIN_UPDATE_EN_N", /*J0 - J7*/ - "LEAK_DETECT_NW_BLADE0_N","WATER_VALVE_CLOSED_N", - "LEAK_DETECT_NW_BLADE1_N","", + "LEAK_DETECT_NW_BLADE1_N","WATER_VALVE_CLOSED_N", "LEAK_DETECT_NW_BLADE2_N","", "LEAK_DETECT_NW_BLADE3_N","", "LEAK_DETECT_NW_BLADE4_N","", "LEAK_DETECT_NW_BLADE5_N","", - "PWRGD_MTIA_BLADE0_HSC_PWROK_N","", + "LEAK_DETECT_NW_BLADE6_N","", "PWRGD_MTIA_BLADE1_HSC_PWROK_N","", - /*K0 - K7*/ "PWRGD_MTIA_BLADE2_HSC_PWROK_N","", + /*K0 - K7*/ "PWRGD_MTIA_BLADE3_HSC_PWROK_N","", "PWRGD_MTIA_BLADE4_HSC_PWROK_N","", "PWRGD_MTIA_BLADE5_HSC_PWROK_N","", @@ -725,49 +724,50 @@ &sgpiom0 { "PWRGD_MTIA_BLADE7_HSC_PWROK_N","", "PWRGD_MTIA_BLADE8_HSC_PWROK_N","", "PWRGD_MTIA_BLADE9_HSC_PWROK_N","", - /*L0 - L7*/ "PWRGD_MTIA_BLADE10_HSC_PWROK_N","", + /*L0 - L7*/ "PWRGD_MTIA_BLADE11_HSC_PWROK_N","", "PWRGD_MTIA_BLADE12_HSC_PWROK_N","", "PWRGD_MTIA_BLADE13_HSC_PWROK_N","", "PWRGD_MTIA_BLADE14_HSC_PWROK_N","", "PWRGD_MTIA_BLADE15_HSC_PWROK_N","", - "PWRGD_NW_BLADE0_HSC_PWROK_N","", + "PWRGD_MTIA_BLADE16_HSC_PWROK_N","", "PWRGD_NW_BLADE1_HSC_PWROK_N","", - /*M0 - M7*/ "PWRGD_NW_BLADE2_HSC_PWROK_N","", + /*M0 - M7*/ "PWRGD_NW_BLADE3_HSC_PWROK_N","", "PWRGD_NW_BLADE4_HSC_PWROK_N","", "PWRGD_NW_BLADE5_HSC_PWROK_N","", + "PWRGD_NW_BLADE6_HSC_PWROK_N","", "RPU_READY","", "IT_GEAR_RPU_LINK_N","", "IT_GEAR_LEAK","", "WATER_VALVE_CLOSED_N","", /*N0 - N7*/ - "VALVE_STS0","", - "VALVE_STS1","", - "PCA9555_IRQ0_N","", + "VALVE_STATUS_0","", + "VALVE_STATUS_1","", "PCA9555_IRQ1_N","", + "PCA9555_IRQ2_N","", "CR_TOGGLE_BOOT_N","", - "IRQ_FCB_TOP0_N","", - "IRQ_FCB_TOP1_N","", + "IRQ_FCB_1_N","", + "IRQ_FCB_2_N","", "CMM_CABLE_CARTRIDGE_PRSNT_BOT_N","", /*O0 - O7*/ "CMM_CABLE_CARTRIDGE_PRSNT_TOP_N","", "BOT_BCB_CABLE_PRSNT_N","", "TOP_BCB_CABLE_PRSNT_N","", - "IRQ_FCB_MID0_N","", - "IRQ_FCB_MID1_N","", + "IRQ_FCB_3_N","", + "IRQ_FCB_4_N","", "CHASSIS_LEAK0_DETECT_N","", "CHASSIS_LEAK1_DETECT_N","", - "VALVE_RMON_A_1","", + "PCA9555_IRQ3_N","", /*P0 - P7*/ - "VALVE_RMON_A_2","", - "VALVE_RMON_B_1","", - "VALVE_RMON_B_2","", + "PCA9555_IRQ4_N","", + "PCA9555_IRQ5_N","", + "CMM_AC_PWR_BTN_N","", "RPU_READY_SPARE","", "IT_GEAR_LEAK_SPARE","", "IT_GEAR_RPU_LINK_SPARE_N","", - "IRQ_FCB_BOT0_N","", - "IRQ_FCB_BOT0_N",""; + "IRQ_FCB_6_N","", + "IRQ_FCB_5_N",""; }; From patchwork Tue Sep 24 14:02:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Chen X-Patchwork-Id: 13810995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 708F2CF9C6B for ; Tue, 24 Sep 2024 14:08:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=t41RrvA9ibashCj3l3oDsqUmb7XQG+ol4j0yx1LSoJs=; b=Mhb25U314zze9S+mHC7ZsX7D93 LEFsSaudEPPDbbI5ulxHwtwweJfmTs8Vk1hYs774x1nXJefDyqrO4QtoWN00h1sGFxX3+DJOCEACl 4g9fnMPCScXfiMLXHu3KoKmb9RvhzMWcbB6XHMnrUNUrrcRc9JX71j95MyKJ+7GkCarFHQ22YqCRQ LVqjJlEmPCA8XNhYJW3TNB2lx6ri5++PMzcUqcq7o5nWcQFQjQBc9tqrcmaEiIr1BHiu5rJAbMyHH ARHe+p+QGxi5F0CsDuUloBl01aEdcKRrcBn0cLpLyNEQBdQ0nPcOH4GVOaMWNRW4kWlEniOuioRSR mkf3IG7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1st6Cm-00000002VRR-2NNT; Tue, 24 Sep 2024 14:07:52 +0000 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1st69U-00000002UsF-0hC4 for linux-arm-kernel@lists.infradead.org; Tue, 24 Sep 2024 14:04:30 +0000 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-20551e2f1f8so64645585ad.2 for ; Tue, 24 Sep 2024 07:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727186667; x=1727791467; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t41RrvA9ibashCj3l3oDsqUmb7XQG+ol4j0yx1LSoJs=; b=njMtPq1azenNit0qNZZ6HUhz+DT0YPykd761DqrTg6Nk7reHbCBaZ+SW0N2/POuZbH +N4EfPhRkO724dE8vHoAZl7eg51uQYQF7iQYKazVCdhu99MRUQqtWZBodtPTwY9ayOK6 i1xh3MckajBrr1N8KSL6XAYguVRM9jBy20EBZkNkvfdb9WQu+r8fNT7Xn7ZCbRqfHOX+ 1R8gxTU3dO5uGFjnTM4WaMM5UmD6XsJW1pNvQUmau3H0DehqOi4+tf7Qa4EzC7kgm2sh +7+CTQ8XTEenF+Zg2AzQQ7IRAaDWM3CTr1SiUyIm0A6KArYQQBiWurqjkHNHGR1YJTvd r2bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727186667; x=1727791467; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t41RrvA9ibashCj3l3oDsqUmb7XQG+ol4j0yx1LSoJs=; b=ajPKoONgbgn/0iJt3DhgjVmcJ3JWA07H0/LNf8OimyMF5lWEK1+rdyn3qhfNEH9TGN g7u6tqu5mac4RlPbclWR5on38pZkm+8PEAgj0QCcL2aWigr/Chc9ysNsszREuV9dcwin Zw6a1sMDxzuC9zbCDxt1YxVM2tpgKYzebGP4wt3RmU8yJCOn3VHee5HnCzeQP1KsR7eH /Nzz6ArjbizzPh72am5Y/NylkS1rxbfoL79SGxOhKZbgXb6kwsXP1YxmImxAOFMs3L/o yEcbyN5slowc6T6Gba5ER3QeWipiU+Am7sK4ncD0cMlkMyo9R62M9a22jjY+tDKK4jKv EO6Q== X-Forwarded-Encrypted: i=1; AJvYcCXgc2CoDEmyWR/Cf/j+w4h1j6rmIg+jQc/o/cvlOwes24kSqRMqX1C3ftIn69A+aVzOFQ5c3/RzrfeqNtdLJREk@lists.infradead.org X-Gm-Message-State: AOJu0YxnegxV7qtdqW64BI2HvUsi9auGHT5l58pReIpv/ss8Oqd5peuy gwWSNqf5JgAfeen9AZX18pIONf4KPHTqeHo4y1+GJvi5w8UG38fD X-Google-Smtp-Source: AGHT+IHnzkG8P7QQgG9rKuqx66HrjkDX9178ig3DFr0CaK8vzpF07XzLy0C6tKxwVlqORq0CLbLAzQ== X-Received: by 2002:a17:902:d4d2:b0:207:3a4a:de43 with SMTP id d9443c01a7336-208d83c8114mr188656825ad.34.1727186666859; Tue, 24 Sep 2024 07:04:26 -0700 (PDT) Received: from obliging-System-Product-Name.dhcpserver.bu9bmc.local (61-220-246-151.hinet-ip.hinet.net. [61.220.246.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20af1821f33sm10678895ad.219.2024.09.24.07.04.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2024 07:04:26 -0700 (PDT) From: Yang Chen To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au, andrew@codeconstruct.com.au, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, patrick@stwcx.xyz, amithash@meta.com Cc: Jerry.Lin@quantatw.com, yangchen.openbmc@gmail.com Subject: [PATCH v1 2/3] ARM: dts: aspeed: minerva: change the i2c mux number for FCBs Date: Tue, 24 Sep 2024 22:02:14 +0800 Message-Id: <20240924140215.2484170-3-yangchen.openbmc@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240924140215.2484170-1-yangchen.openbmc@gmail.com> References: <20240924140215.2484170-1-yangchen.openbmc@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240924_070428_228513_B4D53EEF X-CRM114-Status: GOOD ( 11.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Change the i2c mux channel to match the correct fan board location. Signed-off-by: Yang Chen --- .../aspeed/aspeed-bmc-facebook-minerva.dts | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts index 38eb42aaa98b..c915db28a806 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts @@ -213,10 +213,11 @@ i2c-mux@77 { #size-cells = <0>; i2c-mux-idle-disconnect; - imux16: i2c@0 { + // FCB 1 + imux16: i2c@1 { #address-cells = <1>; #size-cells = <0>; - reg = <0>; + reg = <1>; eeprom@50 { compatible = "atmel,24c128"; @@ -259,11 +260,11 @@ temperature-sensor@4b { reg = <0x4b>; }; }; - - imux17: i2c@1 { + // FCB 2 + imux17: i2c@0 { #address-cells = <1>; #size-cells = <0>; - reg = <1>; + reg = <0>; eeprom@50 { compatible = "atmel,24c128"; @@ -306,11 +307,11 @@ temperature-sensor@4b { reg = <0x4b>; }; }; - - imux18: i2c@2 { + // FCB 3 + imux18: i2c@3 { #address-cells = <1>; #size-cells = <0>; - reg = <2>; + reg = <3>; eeprom@50 { compatible = "atmel,24c128"; @@ -353,11 +354,11 @@ temperature-sensor@4b { reg = <0x4b>; }; }; - - imux19: i2c@3 { + // FCB 4 + imux19: i2c@2 { #address-cells = <1>; #size-cells = <0>; - reg = <3>; + reg = <2>; eeprom@50 { compatible = "atmel,24c128"; @@ -400,8 +401,8 @@ temperature-sensor@4b { reg = <0x4b>; }; }; - - imux20: i2c@5 { + // FCB 5 + imux20: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; @@ -446,8 +447,8 @@ temperature-sensor@4b { reg = <0x4b>; }; }; - - imux21: i2c@4 { + // FCB 6 + imux21: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; From patchwork Tue Sep 24 14:02:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Chen X-Patchwork-Id: 13810996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98CEFCF9C6F for ; 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[61.220.246.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20af1821f33sm10678895ad.219.2024.09.24.07.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2024 07:04:29 -0700 (PDT) From: Yang Chen To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au, andrew@codeconstruct.com.au, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, patrick@stwcx.xyz, amithash@meta.com Cc: Jerry.Lin@quantatw.com, yangchen.openbmc@gmail.com Subject: [PATCH v1 3/3] ARM: dts: aspeed: minerva: add fru device for other blades Date: Tue, 24 Sep 2024 22:02:15 +0800 Message-Id: <20240924140215.2484170-4-yangchen.openbmc@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240924140215.2484170-1-yangchen.openbmc@gmail.com> References: <20240924140215.2484170-1-yangchen.openbmc@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240924_070431_731682_806A3674 X-CRM114-Status: GOOD ( 11.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Minerva platform has 16 compute blades and 6 network blades, each with an EEPROM that can be operated by the CMM. This commit adds support for each FRU. Signed-off-by: Yang Chen --- .../aspeed/aspeed-bmc-facebook-minerva.dts | 334 ++++++++++++++++++ 1 file changed, 334 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts index c915db28a806..468a33f50ef2 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts @@ -23,6 +23,32 @@ aliases { i2c19 = &imux19; i2c20 = &imux20; i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + i2c40 = &imux40; + i2c41 = &imux41; + i2c42 = &imux42; + i2c43 = &imux43; + i2c44 = &imux44; + i2c45 = &imux45; + i2c46 = &imux46; + i2c47 = &imux47; spi1 = &spi_gpio; }; @@ -493,23 +519,239 @@ temperature-sensor@4b { reg = <0x4b>; }; }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; &i2c3 { status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; }; &i2c4 { status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + imux28: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux29: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux30: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux31: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; }; &i2c5 { status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; }; &i2c6 { status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + imux36: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux37: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux38: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux39: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; }; &i2c7 { @@ -536,10 +778,102 @@ rtc@51 { &i2c12 { status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + imux40: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux41: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux42: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux43: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; }; &i2c13 { status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + imux44: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux45: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux46: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux47: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; }; &i2c14 {