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Iglesias" To: xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, michal.orzel@amd.com, Volodymyr_Babchuk@epam.com, dpsmith@apertussolutions.com, edgar.iglesias@amd.com Subject: [PATCH v1 1/6] xen/arm: Decrease size of the 2nd ram bank Date: Tue, 24 Sep 2024 18:23:54 +0200 Message-ID: <20240924162359.1390487-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240924162359.1390487-1-edgar.iglesias@gmail.com> References: <20240924162359.1390487-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 From: "Edgar E. Iglesias" The address range between 4G (32bit) and 1TB (40bit) is fully allocated. There's no more room for devices on ARM systems with 40-bit physicall address width. This decreases the size of the second RAM bank to free up space in preparation for virtio-pci and for future use-cases. In the future we may need to add a third RAM bank in higher address ranges. Signed-off-by: Edgar E. Iglesias --- xen/include/public/arch-arm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index e2412a1747..e19f0251a6 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -491,8 +491,8 @@ typedef uint64_t xen_callback_t; #define GUEST_VPCI_PREFETCH_MEM_ADDR xen_mk_ullong(0x100000000) #define GUEST_VPCI_PREFETCH_MEM_SIZE xen_mk_ullong(0x100000000) -#define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 1016GB of RAM @ 8GB */ -#define GUEST_RAM1_SIZE xen_mk_ullong(0xfe00000000) +#define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 952GB of RAM @ 8GB */ +#define GUEST_RAM1_SIZE xen_mk_ullong(0xee00000000) #define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */ /* Largest amount of actual RAM, not including holes */ From patchwork Tue Sep 24 16:23:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 13811056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76215CF9C6F for ; Tue, 24 Sep 2024 16:24:31 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.803099.1213539 (Exim 4.92) (envelope-from ) id 1st8Ku-0006Mx-Kg; Tue, 24 Sep 2024 16:24:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 803099.1213539; Tue, 24 Sep 2024 16:24:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1st8Ku-0006Mq-H8; Tue, 24 Sep 2024 16:24:24 +0000 Received: by outflank-mailman (input) for mailman id 803099; Tue, 24 Sep 2024 16:24:23 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1st8Kt-0005nz-N9 for xen-devel@lists.xenproject.org; Tue, 24 Sep 2024 16:24:23 +0000 Received: from mail-ua1-x933.google.com (mail-ua1-x933.google.com [2607:f8b0:4864:20::933]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7477f009-7a91-11ef-99a2-01e77a169b0f; Tue, 24 Sep 2024 18:24:22 +0200 (CEST) Received: by mail-ua1-x933.google.com with SMTP id a1e0cc1a2514c-846c588fa63so1409205241.1 for ; Tue, 24 Sep 2024 09:24:22 -0700 (PDT) Received: from gmail.com ([168.243.189.171]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-505a9f447c9sm1009620e0c.21.2024.09.24.09.24.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2024 09:24:19 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7477f009-7a91-11ef-99a2-01e77a169b0f DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727195060; x=1727799860; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i9CJig1i8u5IsDi36lSzKV6C9GOB2ljlgBS7lSvvQGU=; b=gb/+R+82dRdYoftMajuBcFSzzzRHpPCeCB13Emr50VE0H6cIEFIK0cCQlmlRAX2gDP ZMomO471Iqu1Q6OlIMJmztJCjITbERqf6WPZ03pGoPkC7P6qyyIeCm3+ztlG4vd5BHTZ /GzcoQPmAn/4s2FBnFKyOSUW2JK3S1sA5KDak6Y/M/ZU1aAVz4etBW8LAZHlzmUuDOS/ g+yV8jSQ1KUFZK/B3eW96sk0JZ26h7wGFlP0wrJdxPzYNMjks6YE4/cwHyS2BChIWzwO fMeKwYNaufUW2INNCxS6jFJ0HkTlJZKsk4dI+SwdCuxSq4XKygvwXFeZF0CdWq4GmlSV YeFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727195060; x=1727799860; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i9CJig1i8u5IsDi36lSzKV6C9GOB2ljlgBS7lSvvQGU=; b=PjrlD5hOfCaGads2nm98DZ7OATbQkXi7FuoHPTv95CjtLZOyFeQOi58pTkKkRFEco8 Jkq5qTa0kMzvpoPF2UjE5EAPti1OXz08PbnDYB1Rj6cfakT847fiD4rEr69paltgPpQU g9thd+eWlTXxbewKvqzM87bSUTvuR1ztWOFsyKUEDiRQ8ZXxDl5OWZnM+41i7XLShT/H nEyyy6t5Gs6jJ+3jGfwpq1LgaCxHNH5r0S6XpmdGuy744dYrpcE53UlIB2HMD/EN/wqC 25ZfJGW7WfQ+6Xv3s5Yj+nULV7fftTYh0IIe4X4pB26BKEql82qK+IAYN7Q4/bSFayMm F7fw== X-Gm-Message-State: AOJu0Yy50GyoMfMKdX6eR/LCBBGyeiPBsz+/x6Lfk81VFkIw2SyVL9Kz yCmBNclPYod+K+Vsl3HHPDe5nTTZIFDo8P6ECU7sekwabJksAMnS0SKcnvGi X-Google-Smtp-Source: AGHT+IFBD/GEOlq+4MH+47ZnN/yNKHDYkjA993DMIapv0ig7Le6AvtB+avT6gcv4xAEnM3dO6MB/pQ== X-Received: by 2002:a05:6122:31a6:b0:4ef:65b6:f3b5 with SMTP id 71dfb90a1353d-505c20925c6mr55521e0c.10.1727195060313; Tue, 24 Sep 2024 09:24:20 -0700 (PDT) From: "Edgar E. Iglesias" To: xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, michal.orzel@amd.com, Volodymyr_Babchuk@epam.com, dpsmith@apertussolutions.com, edgar.iglesias@amd.com Subject: [PATCH v1 2/6] xen/arm: Reserve resources for virtio-pci Date: Tue, 24 Sep 2024 18:23:55 +0200 Message-ID: <20240924162359.1390487-3-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240924162359.1390487-1-edgar.iglesias@gmail.com> References: <20240924162359.1390487-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 From: "Edgar E. Iglesias" Reserve memory ranges and interrupt lines for an externally emulated PCI controller (e.g by QEMU) dedicated to hosting Virtio devices and potentially other emulated devices. Signed-off-by: Edgar E. Iglesias --- xen/include/public/arch-arm.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index e19f0251a6..654b827715 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -494,6 +494,20 @@ typedef uint64_t xen_callback_t; #define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 952GB of RAM @ 8GB */ #define GUEST_RAM1_SIZE xen_mk_ullong(0xee00000000) +/* Virtio PCI - Ordered by decreasing size to keep things aligned */ +#define GUEST_VIRTIO_PCI_PREFETCH_MEM_TYPE xen_mk_ullong(0x43000000) +#define GUEST_VIRTIO_PCI_PREFETCH_MEM_BASE xen_mk_ullong(0x0f000000000) +#define GUEST_VIRTIO_PCI_PREFETCH_MEM_SIZE xen_mk_ullong(0x100000000) + +#define GUEST_VIRTIO_PCI_ECAM_BASE (GUEST_VIRTIO_PCI_PREFETCH_MEM_BASE + \ + GUEST_VIRTIO_PCI_PREFETCH_MEM_SIZE) +#define GUEST_VIRTIO_PCI_ECAM_SIZE xen_mk_ullong(0x10000000) + +#define GUEST_VIRTIO_PCI_MEM_TYPE xen_mk_ullong(0x02000000) +#define GUEST_VIRTIO_PCI_MEM_BASE (GUEST_VIRTIO_PCI_ECAM_BASE + \ + GUEST_VIRTIO_PCI_ECAM_SIZE) +#define GUEST_VIRTIO_PCI_MEM_SIZE xen_mk_ullong(0x00002000000) + #define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */ /* Largest amount of actual RAM, not including holes */ #define GUEST_RAM_MAX (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE) @@ -529,6 +543,9 @@ typedef uint64_t xen_callback_t; #define GUEST_FFA_NOTIF_PEND_INTR_ID 8 #define GUEST_FFA_SCHEDULE_RECV_INTR_ID 9 +#define GUEST_VIRTIO_PCI_SPI_FIRST 44 +#define GUEST_VIRTIO_PCI_SPI_LAST 48 + /* PSCI functions */ #define PSCI_cpu_suspend 0 #define PSCI_cpu_off 1 From patchwork Tue Sep 24 16:23:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. 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Iglesias" To: xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, michal.orzel@amd.com, Volodymyr_Babchuk@epam.com, dpsmith@apertussolutions.com, edgar.iglesias@amd.com, Stewart Hildebrand Subject: [PATCH v1 3/6] xen/arm: create dom0less virtio-pci DT node Date: Tue, 24 Sep 2024 18:23:56 +0200 Message-ID: <20240924162359.1390487-4-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240924162359.1390487-1-edgar.iglesias@gmail.com> References: <20240924162359.1390487-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 From: Stewart Hildebrand When virtio-pci is specified in the dom0less domU properties, create a virtio-pci node in the guest's device tree. Set up an mmio handler with a register for the guest to poll when the backend has connected and virtio-pci bus is ready to be probed. Grant tables may be used by specifying virtio-pci = "grants";. [Edgar: Use GPEX PCI INTX interrupt swizzling (from PCI specs). Make grants iommu-map cover the entire PCI bus. Add virtio-pci-ranges to specify memory-map for direct-mapped guests. Document virtio-pci dom0less fdt bindings.] Signed-off-by: Stewart Hildebrand Signed-off-by: Edgar E. Iglesias --- docs/misc/arm/device-tree/booting.txt | 21 +++ xen/arch/arm/dom0less-build.c | 238 ++++++++++++++++++++++++++ xen/arch/arm/include/asm/kernel.h | 15 ++ 3 files changed, 274 insertions(+) diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-tree/booting.txt index 3a04f5c57f..82f3bd7026 100644 --- a/docs/misc/arm/device-tree/booting.txt +++ b/docs/misc/arm/device-tree/booting.txt @@ -276,6 +276,27 @@ with the following properties: passed through. This option is the default if this property is missing and the user does not provide the device partial device tree for the domain. +- virtio-pci + + A string property specifying whether virtio-pci is enabled for the + domain and if grant table mappings should be used. If no value is set + this property is treated as a boolean and the same way as if set to + "enabled". + Possible property values are: + + - "enabled" + Virtio-pci is enabled for the domain. + + - "grants" + Virtio-pci is enabled for the domain and an grants IOMMU node will be + generated in the domains device-tree. + +- virtio-pci-ranges + + An optional array of 6 u32 values specifying the 2 cells base addresses of + the ECAM, Memory and Prefetchable-Memory regions for virtio-pci. This is + useful to avoid memory-map collisions when using direct-mapped guests. + Under the "xen,domain" compatible node, one or more sub-nodes are present for the DomU kernel and ramdisk. diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 09b65e44ae..dab24fa9e2 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -586,6 +586,189 @@ static int __init domain_handle_dtb_bootmodule(struct domain *d, return res; } +static int __init make_virtio_pci_domU_node(const struct kernel_info *kinfo) +{ + void *fdt = kinfo->fdt; + /* reg is sized to be used for all the needed properties below */ + __be32 reg[(1 + (GUEST_ROOT_ADDRESS_CELLS * 2) + GUEST_ROOT_SIZE_CELLS) + * 2]; + __be32 irq_map[4 * 4 * 8]; + __be32 *cells; + char buf[22]; /* pcie@ + max 16 char address + '\0' */ + int res; + int devfn, intx_pin; + static const char compat[] = "pci-host-ecam-generic"; + static const char reg_names[] = "ecam"; + + if ( p2m_ipa_bits <= 40 ) { + printk("PA bits %d is too small!\nvirtio-pci is only supported " + "on platforms with PA bits > 40\n", p2m_ipa_bits); + return -EINVAL; + } + + snprintf(buf, sizeof(buf), "pcie@%lx", kinfo->virtio_pci.ecam.base); + dt_dprintk("Create virtio-pci node\n"); + res = fdt_begin_node(fdt, buf); + if ( res ) + return res; + + res = fdt_property(fdt, "compatible", compat, sizeof(compat)); + if ( res ) + return res; + + res = fdt_property_string(fdt, "device_type", "pci"); + if ( res ) + return res; + + /* Create reg property */ + cells = ®[0]; + dt_child_set_range(&cells, GUEST_ROOT_ADDRESS_CELLS, GUEST_ROOT_SIZE_CELLS, + kinfo->virtio_pci.ecam.base, GUEST_VIRTIO_PCI_ECAM_SIZE); + + res = fdt_property(fdt, "reg", reg, + (GUEST_ROOT_ADDRESS_CELLS + + GUEST_ROOT_SIZE_CELLS) * sizeof(*reg)); + if ( res ) + return res; + + res = fdt_property(fdt, "reg-names", reg_names, sizeof(reg_names)); + if ( res ) + return res; + + /* Create bus-range property */ + cells = ®[0]; + dt_set_cell(&cells, 1, 0); + dt_set_cell(&cells, 1, 0xff); + res = fdt_property(fdt, "bus-range", reg, 2 * sizeof(*reg)); + if ( res ) + return res; + + res = fdt_property_cell(fdt, "#address-cells", 3); + if ( res ) + return res; + + res = fdt_property_cell(fdt, "#size-cells", 2); + if ( res ) + return res; + + res = fdt_property_string(fdt, "status", "okay"); + if ( res ) + return res; + + /* + * Create ranges property as: + * <(PCI bitfield) (PCI address) (CPU address) (Size)> + */ + cells = ®[0]; + dt_set_cell(&cells, 1, GUEST_VIRTIO_PCI_MEM_TYPE); + dt_set_cell(&cells, GUEST_ROOT_ADDRESS_CELLS, kinfo->virtio_pci.mem.base); + dt_set_cell(&cells, GUEST_ROOT_ADDRESS_CELLS, kinfo->virtio_pci.mem.base); + dt_set_cell(&cells, GUEST_ROOT_SIZE_CELLS, GUEST_VIRTIO_PCI_MEM_SIZE); + dt_set_cell(&cells, 1, GUEST_VIRTIO_PCI_PREFETCH_MEM_TYPE); + dt_set_cell(&cells, GUEST_ROOT_ADDRESS_CELLS, kinfo->virtio_pci.pf_mem.base); + dt_set_cell(&cells, GUEST_ROOT_ADDRESS_CELLS, kinfo->virtio_pci.pf_mem.base); + dt_set_cell(&cells, GUEST_ROOT_SIZE_CELLS, GUEST_VIRTIO_PCI_PREFETCH_MEM_SIZE); + res = fdt_property(fdt, "ranges", reg, 14 * sizeof(*reg)); + if ( res ) + return res; + + res = fdt_property(fdt, "dma-coherent", "", 0); + if ( res ) + return res; + + res = fdt_property_cell(fdt, "#interrupt-cells", 1); + if ( res ) + return res; + + /* + * PCI-to-PCI bridge specification + * 9.1: Interrupt routing. Table 9-1 + * + * the PCI Express Base Specification, Revision 2.1 + * 2.2.8.1: INTx interrupt signaling - Rules + * the Implementation Note + * Table 2-20 + */ + cells = &irq_map[0]; + for (devfn = 0; devfn <= 0x18; devfn += 8) { + for (intx_pin = 0; intx_pin < 4; intx_pin++) { + int irq = GUEST_VIRTIO_PCI_SPI_FIRST - 32; + irq += ((intx_pin + PCI_SLOT(devfn)) % 4); + + dt_set_cell(&cells, 1, devfn << 8); + dt_set_cell(&cells, 1, 0); + dt_set_cell(&cells, 1, 0); + dt_set_cell(&cells, 1, intx_pin + 1); + dt_set_cell(&cells, 1, kinfo->phandle_gic); + /* 3 GIC cells. */ + dt_set_cell(&cells, 1, 0); + dt_set_cell(&cells, 1, irq); + dt_set_cell(&cells, 1, DT_IRQ_TYPE_LEVEL_HIGH); + } + } + + /* Assert we've sized irq_map correctly. */ + BUG_ON(cells - &irq_map[0] != ARRAY_SIZE(irq_map)); + + res = fdt_property(fdt, "interrupt-map", irq_map, sizeof(irq_map)); + if ( res ) + return res; + + cells = ®[0]; + dt_set_cell(&cells, 1, cpu_to_be16(PCI_DEVFN(3, 0))); + dt_set_cell(&cells, 1, 0x0); + dt_set_cell(&cells, 1, 0x0); + dt_set_cell(&cells, 1, 0x7); + res = fdt_property(fdt, "interrupt-map-mask", reg, 4 * sizeof(*reg)); + if ( res ) + return res; + + if ( kinfo->virtio_pci.mode == VIRTIO_PCI_GRANTS ) + { + cells = ®[0]; + dt_set_cell(&cells, 1, 0x0); + dt_set_cell(&cells, 1, GUEST_PHANDLE_IOMMU); + dt_set_cell(&cells, 1, 0x0); + dt_set_cell(&cells, 1, 0x10000); + res = fdt_property(fdt, "iommu-map", reg, 4 * sizeof(*reg)); + if ( res ) + return res; + } + + res = fdt_property_cell(fdt, "linux,pci-domain", 1); + if ( res ) + return res; + + res = fdt_end_node(fdt); + if ( res ) + return res; + + if ( kinfo->virtio_pci.mode == VIRTIO_PCI_GRANTS ) + { + snprintf(buf, sizeof(buf), "xen_iommu"); + + res = fdt_begin_node(fdt, buf); + if ( res ) + return res; + + res = fdt_property_string(fdt, "compatible", "xen,grant-dma"); + if ( res ) + return res; + + res = fdt_property_cell(fdt, "#iommu-cells", 1); + if ( res ) + return res; + + res = fdt_property_cell(fdt, "phandle", GUEST_PHANDLE_IOMMU); + if ( res ) + return res; + + res = fdt_end_node(fdt); + } + + return res; +} + /* * The max size for DT is 2MB. However, the generated DT is small (not including * domU passthrough DT nodes whose size we account separately), 4KB are enough @@ -693,6 +876,13 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) goto err; } + if ( kinfo->virtio_pci.mode ) + { + ret = make_virtio_pci_domU_node(kinfo); + if ( ret ) + goto err; + } + ret = fdt_end_node(kinfo->fdt); if ( ret < 0 ) goto err; @@ -744,11 +934,24 @@ static int __init alloc_xenstore_evtchn(struct domain *d) return 0; } +static u64 combine_u64(u32 v[2]) +{ + u64 v64; + + v64 = v[0]; + v64 <<= 32; + v64 |= v[1]; + return v64; +} + static int __init construct_domU(struct domain *d, const struct dt_device_node *node) { struct kernel_info kinfo = KERNEL_INFO_INIT; const char *dom0less_enhanced; + const char *virtio_pci; + /* virtio-pci ECAM, MEM, PF-MEM each carrying 2 x Address cells. */ + u32 virtio_pci_ranges[3 * 2]; int rc; u64 mem; u32 p2m_mem_mb; @@ -779,6 +982,41 @@ static int __init construct_domU(struct domain *d, kinfo.vpl011 = dt_property_read_bool(node, "vpl011"); + rc = dt_property_read_string(node, "virtio-pci", &virtio_pci); + if ( !rc ) + { + if ( !strcmp(virtio_pci, "enabled") ) + kinfo.virtio_pci.mode = VIRTIO_PCI; + else if ( !strcmp(virtio_pci, "grants") ) + kinfo.virtio_pci.mode = VIRTIO_PCI_GRANTS; + else + { + printk("Invalid \"virtio-pci\" property value (%s)\n", virtio_pci); + return -EINVAL; + } + } + else if ( rc == -ENODATA ) + { + /* Handle missing property value */ + kinfo.virtio_pci.mode = dt_property_read_bool(node, "virtio-pci"); + } + + if ( kinfo.virtio_pci.mode != VIRTIO_PCI_NONE ) + { + rc = dt_property_read_u32_array(node, "virtio-pci-ranges", + virtio_pci_ranges, + ARRAY_SIZE(virtio_pci_ranges)); + if ( rc == 0 ) { + kinfo.virtio_pci.ecam.base = combine_u64(&virtio_pci_ranges[0]); + kinfo.virtio_pci.mem.base = combine_u64(&virtio_pci_ranges[2]); + kinfo.virtio_pci.pf_mem.base = combine_u64(&virtio_pci_ranges[4]); + } else { + kinfo.virtio_pci.ecam.base = GUEST_VIRTIO_PCI_ECAM_BASE; + kinfo.virtio_pci.mem.base = GUEST_VIRTIO_PCI_MEM_BASE; + kinfo.virtio_pci.pf_mem.base = GUEST_VIRTIO_PCI_PREFETCH_MEM_BASE; + } + } + rc = dt_property_read_string(node, "xen,enhanced", &dom0less_enhanced); if ( rc == -EILSEQ || rc == -ENODATA || diff --git a/xen/arch/arm/include/asm/kernel.h b/xen/arch/arm/include/asm/kernel.h index 7e6e3c82a4..2dab2ac88f 100644 --- a/xen/arch/arm/include/asm/kernel.h +++ b/xen/arch/arm/include/asm/kernel.h @@ -29,6 +29,13 @@ #define DOM0LESS_XENSTORE BIT(1, U) #define DOM0LESS_ENHANCED (DOM0LESS_ENHANCED_NO_XS | DOM0LESS_XENSTORE) +/* virtio-pci types */ +enum virtio_pci_type { + VIRTIO_PCI_NONE, + VIRTIO_PCI, + VIRTIO_PCI_GRANTS, +}; + struct kernel_info { #ifdef CONFIG_ARM_64 enum domain_type type; @@ -62,6 +69,14 @@ struct kernel_info { /* Enable/Disable PV drivers interfaces */ uint16_t dom0less_feature; + struct { + enum virtio_pci_type mode; + struct { + u64 base; + } ecam, mem, pf_mem; + u32 pci_intx_irq_base; + } virtio_pci; + /* GIC phandle */ uint32_t phandle_gic; From patchwork Tue Sep 24 16:23:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. 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Iglesias" To: xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, michal.orzel@amd.com, Volodymyr_Babchuk@epam.com, dpsmith@apertussolutions.com, edgar.iglesias@amd.com Subject: [PATCH v1 4/6] xen/arm: io: Add support for mmio background regions Date: Tue, 24 Sep 2024 18:23:57 +0200 Message-ID: <20240924162359.1390487-5-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240924162359.1390487-1-edgar.iglesias@gmail.com> References: <20240924162359.1390487-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 From: "Edgar E. Iglesias" Add support for mmio background regions. These regions can be overlayed by IOREQ handlers and thus act as fallback handlers while IOREQ clients haven't registered. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini --- xen/arch/arm/include/asm/mmio.h | 11 ++++++++++- xen/arch/arm/io.c | 18 ++++++++++++------ 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/include/asm/mmio.h b/xen/arch/arm/include/asm/mmio.h index b22cfdac5b..7da542cd79 100644 --- a/xen/arch/arm/include/asm/mmio.h +++ b/xen/arch/arm/include/asm/mmio.h @@ -70,6 +70,7 @@ struct mmio_handler_ops { struct mmio_handler { paddr_t addr; paddr_t size; + bool background; const struct mmio_handler_ops *ops; void *priv; }; @@ -83,9 +84,17 @@ struct vmmio { enum io_state try_handle_mmio(struct cpu_user_regs *regs, mmio_info_t *info); +void register_mmio_bg_handler(struct domain *d, + bool background, + const struct mmio_handler_ops *ops, + paddr_t addr, paddr_t size, void *priv); +static inline void register_mmio_handler(struct domain *d, const struct mmio_handler_ops *ops, - paddr_t addr, paddr_t size, void *priv); + paddr_t addr, paddr_t size, void *priv) +{ + register_mmio_bg_handler(d, false, ops, addr, size, priv); +} int domain_io_init(struct domain *d, unsigned int max_count); void domain_io_free(struct domain *d); diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index 96c740d563..934a2ad2b9 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -159,6 +159,7 @@ enum io_state try_handle_mmio(struct cpu_user_regs *regs, { struct vcpu *v = current; const struct mmio_handler *handler = NULL; + bool has_background; int rc; ASSERT(info->dabt.ec == HSR_EC_DATA_ABORT_LOWER_EL); @@ -170,13 +171,16 @@ enum io_state try_handle_mmio(struct cpu_user_regs *regs, } handler = find_mmio_handler(v->domain, info->gpa); - if ( !handler ) + has_background = handler && handler->background; + if ( !handler || has_background ) { rc = try_fwd_ioserv(regs, v, info); if ( rc == IO_HANDLED ) return handle_ioserv(regs, v); - - return rc; + else if ( !(rc == IO_UNHANDLED && has_background) ) { + /* Only return failure if there's no background handler. */ + return rc; + } } /* @@ -197,9 +201,10 @@ enum io_state try_handle_mmio(struct cpu_user_regs *regs, return handle_read(handler, v, info); } -void register_mmio_handler(struct domain *d, - const struct mmio_handler_ops *ops, - paddr_t addr, paddr_t size, void *priv) +void register_mmio_bg_handler(struct domain *d, + bool background, + const struct mmio_handler_ops *ops, + paddr_t addr, paddr_t size, void *priv) { struct vmmio *vmmio = &d->arch.vmmio; struct mmio_handler *handler; @@ -213,6 +218,7 @@ void register_mmio_handler(struct domain *d, handler->ops = ops; handler->addr = addr; handler->size = size; + handler->background = background; handler->priv = priv; vmmio->num_entries++; From patchwork Tue Sep 24 16:23:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. 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Iglesias" To: xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, michal.orzel@amd.com, Volodymyr_Babchuk@epam.com, dpsmith@apertussolutions.com, edgar.iglesias@amd.com Subject: [PATCH v1 5/6] xen/arm: io: Add a read-const writes-ignored mmio handler Date: Tue, 24 Sep 2024 18:23:58 +0200 Message-ID: <20240924162359.1390487-6-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240924162359.1390487-1-edgar.iglesias@gmail.com> References: <20240924162359.1390487-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 From: "Edgar E. Iglesias" Add a read-const writes-ignored mmio handler. This is useful to for example register background regions that return a fixed value instead of raising data aborts. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini --- xen/arch/arm/include/asm/mmio.h | 2 ++ xen/arch/arm/io.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/xen/arch/arm/include/asm/mmio.h b/xen/arch/arm/include/asm/mmio.h index 7da542cd79..605620a2f4 100644 --- a/xen/arch/arm/include/asm/mmio.h +++ b/xen/arch/arm/include/asm/mmio.h @@ -82,6 +82,8 @@ struct vmmio { struct mmio_handler *handlers; }; +extern const struct mmio_handler_ops mmio_read_const_writes_ignored; + enum io_state try_handle_mmio(struct cpu_user_regs *regs, mmio_info_t *info); void register_mmio_bg_handler(struct domain *d, diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index 934a2ad2b9..8ab0435afc 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -20,6 +20,27 @@ #include "decode.h" +/* + * Reusable mmio handler useful as background while waiting for IOREQ. + * Register with priv as default read value. Writes ignored. + */ +static int bg_read(struct vcpu *v, mmio_info_t *info, register_t *r, void *priv) +{ + *r = (uintptr_t) priv; + return 1; +} + +static int bg_write(struct vcpu *v, mmio_info_t *info, register_t r, void *priv) +{ + return 1; +} + +/* Read const value (from priv), writes ignored. */ +const struct mmio_handler_ops mmio_read_const_writes_ignored = { + .read = bg_read, + .write = bg_write, +}; + static enum io_state handle_read(const struct mmio_handler *handler, struct vcpu *v, mmio_info_t *info) From patchwork Tue Sep 24 16:23:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. 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Iglesias" To: xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, michal.orzel@amd.com, Volodymyr_Babchuk@epam.com, dpsmith@apertussolutions.com, edgar.iglesias@amd.com Subject: [PATCH v1 6/6] xen/arm: dom0less: Add a background PCI ECAM mmio region Date: Tue, 24 Sep 2024 18:23:59 +0200 Message-ID: <20240924162359.1390487-7-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240924162359.1390487-1-edgar.iglesias@gmail.com> References: <20240924162359.1390487-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 From: "Edgar E. Iglesias" Add a background PCI ECAM mmio region always reading as all ones. This indicates to the OS that there are no PCI devices on the bus. Once the device-model's IOREQ client connects, the OS can rescan the bus and find PV and emulated devices. This avoids a race where domU's come up before the device models, causing domU to crash into a data-abort when accessing ECAM. Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini --- xen/arch/arm/dom0less-build.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index dab24fa9e2..bc5285e7fa 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -1015,6 +1015,16 @@ static int __init construct_domU(struct domain *d, kinfo.virtio_pci.mem.base = GUEST_VIRTIO_PCI_MEM_BASE; kinfo.virtio_pci.pf_mem.base = GUEST_VIRTIO_PCI_PREFETCH_MEM_BASE; } + + /* + * Register a background PCI ECAM region returning ~0. This indicates + * to the OS that there are no PCI devices on the bus. Once an IOREQ + * client connects, the OS can rescan the bus and find devices. + */ + register_mmio_bg_handler(d, true, &mmio_read_const_writes_ignored, + kinfo.virtio_pci.ecam.base, + GUEST_VIRTIO_PCI_ECAM_SIZE, + (void *) ULONG_MAX); } rc = dt_property_read_string(node, "xen,enhanced", &dom0less_enhanced);