From patchwork Wed Sep 25 14:54:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13812076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12F50CF9C7B for ; Wed, 25 Sep 2024 14:57:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+nInyqhFC3BdNTlgq3xlhiMTc4jzcWvJSd9GJ9RnehM=; b=A8P+OZbnwZHrVni2Shl2yV7xYv r4fpE7h59EsuDoshS79W3kLOy7uA6calWeGatYlXOP0ZMgtVH9F6aVG/Y+kziT4idELOWD1BAeKPA 9Y0hw1wQGGgxwm0fAcOr8rKRq8IC5wW4/2U2bTwCsq36bqD08j/nogwunxHDTaul0gS3GDfkQTJXv DUTVlIdC1tXPXcQqLhNzWYLkJ7sIxZ1tcxD8NCSlFS60TSaXbUSzizChivGBc/vYa+rdQMsaK8ril jSiggA/hQVpYlH8i8I2HIkh1YYMcER3dIIrxboj21xh7PaRp/ymBQyAT0fWks31rTzuLKx90UPovB mCkFORCg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1stTS5-00000005jjN-0ois; Wed, 25 Sep 2024 14:57:13 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1stTPl-00000005j39-1cXO for linux-arm-kernel@lists.infradead.org; Wed, 25 Sep 2024 14:54:50 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsiIt019874; Wed, 25 Sep 2024 09:54:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276084; bh=+nInyqhFC3BdNTlgq3xlhiMTc4jzcWvJSd9GJ9RnehM=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=lptLDK1ehW793tio6hxoNjpKLVbCxI0sIpuFrAue55J5l57fEsKkvtvenJtEpxLHz /4KjJ2oQU4LwBFpUkouuwSxj3zSqQycqRu8xdzJKtBQctQaC/4xig9helIYBuMbJYD UzEyGwgb+K60FHCs86M+EdEhgn+xbnnX3Ew5vqSs= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEsh4H091833 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:54:43 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:54:43 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:54:43 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCi110564; Wed, 25 Sep 2024 09:54:39 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:15 +0530 Subject: [PATCH v6 1/6] arm64: dts: ti: k3-am62a: add opp frequencies MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-1-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=3780; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=h4Lsswdhctun8wxkRbSRUFWd5uwJNN09QzsFaxwDKNE=; b=neBvRmpaoiH5bR5BrMbYNBXtdJ9VRDdan67hMh+LFdPbVDLL0gFT/rxAUMJERZz9YX610sSeU W9AUIHowtrECbs1s2lagyzpUzexC8O/deODm5bVzGgQi/bO4WcJYB4B X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240925_075449_521796_1C04E2C3 X-CRM114-Status: GOOD ( 12.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Bryan Brattlof One power management technique available to the Cortex-A53s is their ability to dynamically scale their frequency across the device's Operating Performance Points (OPP) The OPPs available for the Cortex-A53s on the AM62Ax can vary based on the silicon variant used. The SoC variant is encoded into the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit to only OPP entries the variant supports. A table of all these variants can be found in it's data sheet[0] for the AM62Ax family. Add the OPP table into the SoC's fdti file along with the syscon node to describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect the SoC variant. [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 51 +++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index f5ac101a04dfa0bdae8ac4f43b01473725433c51..0b1dd5390cd3f42b0ec56bab042388722b4c22a1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -17,6 +17,11 @@ chipid: chipid@14 { reg = <0x14 0x4>; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi index f86a23404e6dde3ca90e41ac0efdb378948e6d50..6c99221beb6bd8e5ad93888e6b659cc6e08fb679 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -48,6 +48,8 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,6 +96,51 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; }; From patchwork Wed Sep 25 14:54:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13812077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1147BCF9C7A for ; Wed, 25 Sep 2024 14:58:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=NK+aFPtpOPuMKEx44hKVNRmBW7EcmS4qirihAf/Pj8U=; b=xN/cQEqW6ygMTkvxsCfZkeObiY rHW8slCQD6HYcn5x94FD7wUl79EY6WqMVSbapvsn7yeJ5cdNaYAT+ac8cET9RxonbU9aB3VrXkZl3 QTfQJqHuWksmb7qbOuDHGDhtcd0PyVMoMWVBrbsW0rzGS76vFwqEFR0lhF3NPiIehzqe25FCr5K50 sL/cvHyCN6V/BAMfiUGMpWqlNTI2pYPL1MBuW1XJYzXZomWsi6T7zLRzV1AajIu16SeTRdQDCzxvm BrPQJ+u7tKh2hSFNA0fDIDxYtcWrxdQY91ISifoYriDfdUnnCIfXeIOgX8gK1S7ZL1qMVqR2aItN+ bvWqwvIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1stTTE-00000005k7J-3EaH; Wed, 25 Sep 2024 14:58:24 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1stTPn-00000005j3T-0wCp for linux-arm-kernel@lists.infradead.org; Wed, 25 Sep 2024 14:54:52 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsmbu062906; Wed, 25 Sep 2024 09:54:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276088; bh=NK+aFPtpOPuMKEx44hKVNRmBW7EcmS4qirihAf/Pj8U=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=nsX2ra+3Ip62JVHWJymWSjig9RqGPPT78FYvzSFZd9Iz3fVgGIYwp+b8PWY43adKR cT0br7RvvX2DVpqiCtiPMi0NGEIVwl/Q3vUeNaFMKflQPFzyCJbgOG0A1Nxejs311F S/8dmRM61A9yNdGOrXLihg52D+/tq71OoCk1ma54= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEsmwJ101421 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:54:48 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:54:47 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:54:47 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCj110564; Wed, 25 Sep 2024 09:54:44 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:16 +0530 Subject: [PATCH v6 2/6] arm64: dts: ti: k3-am62a7-sk: add 1.4ghz opp entry MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-2-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=1133; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=QKNdDE/Q+mzdtPNctGFPfcbWIa4u1MDTUg8/co9DUGU=; b=AtB9POziL6pfK4Jk8OvZ8M+fdXEs8pyd6ZAwhnELOGgOqNUczu4DZBh7EtOObYrlOH179kHX1 CX6f1MnKfkXAra24GkBdBKagqzp2Z8kOmcGHFjkYh9aCsfavJ3fnC82 X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240925_075451_356043_E9309770 X-CRM114-Status: GOOD ( 11.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Bryan Brattlof The AM62Ax reference board is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 7.5 of the SoC's data sheet[0]. Append the 1.4Ghz entry to the OPP table to enable this OPP [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 67faf46d7a35a5954a5a832b8ab766320b48ea59..a6f0d87a50d8a7ebdb61e609e8071d6681dbec9a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -68,6 +68,15 @@ wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + vmain_pd: regulator-0 { /* TPS25750 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; From patchwork Wed Sep 25 14:54:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13812078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FAE7CF9C7A for ; Wed, 25 Sep 2024 14:59:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=28nm6GciXd1Z/cAECj7/YWo0gE1W8fU4bL/W7b+3Ja8=; b=SuFACM7kEKZbiIf5hUGpclP2Vs oqSyqJPC2/BAwhCQT/m4haJW2McDelLc+cYvlWGTdECixNBunb7Ix/RjbRMHvdmbE2oJwR//noSFm /6C5VBdPQm82uum5v/cTTnn6nKA1/rgRWWQseIBBh9vT/0mdh3TKdMiKH5rsoT7OmUZBc/AuVYfKq YbmzRboH5Jvuxxo3mznJfJHBnMkd3fF1SUrX4Qoosei50RlKLZY+MbO9m9k6KLAJ+Y4oe2KGPNc+J sq4RR9C5owvW+2AaKCm1Cb3jb0HAJmQohIpaah8XRdAn/PHnlMgjgrESahi8tQ/jbW8zYlaYweIzD ZA1dVW4g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1stTUN-00000005kOr-1UD5; Wed, 25 Sep 2024 14:59:35 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1stTPs-00000005j5T-2bng for linux-arm-kernel@lists.infradead.org; Wed, 25 Sep 2024 14:54:58 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsqBn098636; Wed, 25 Sep 2024 09:54:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276092; bh=28nm6GciXd1Z/cAECj7/YWo0gE1W8fU4bL/W7b+3Ja8=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=DVrOljn3SiiGa7sOZ0iWrzsqeWxcA1+YSsOGj9c0E493mr9m7keeRpciOHRr3Mjag scfOOSDUspxrgdlTXiTG3dWl8Tk+J18hVPdlKgUhDfntQRuuMa06L/0fek+ZVIfmrf GiXGc/w7Ac6FululBw2ftZ95qjLD+6/xqBg4s7/Y= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEsqsH091939 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:54:52 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:54:51 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:54:51 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCk110564; Wed, 25 Sep 2024 09:54:48 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:17 +0530 Subject: [PATCH v6 3/6] arm64: dts: ti: k3-am62p: add opp frequencies MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-3-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=3849; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=/9L7M8ngafoj6TyntikdD62vQqSW7r8Y6HKG3GFLThQ=; b=rqu483Mn14TLlHKiR8gqslOwy4LbTQTyHT/4KvUCw0umqaYBHsMc5+92uXUIoHbguwMnJpC/A ZRmemhp5drBCtxx924unU9YhCD1TKWlR2IEjrGZXc3SiBee9JA/d+0k X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240925_075456_769526_504E5E7A X-CRM114-Status: GOOD ( 12.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Bryan Brattlof One power management technique available to the Cortex-A53s is their ability to dynamically scale their frequency across the device's Operating Performance Points (OPP) The OPPs available for the Cortex-A53s on the AM62Px can vary based on the silicon variant used. The SoC variant is encoded into the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit the OPP entries the SoC supports. A table of all these variants can be found in its data sheet[0] for the AM62Px processor family. Add the OPP table into the SoC's fdti file along with the syscon node to describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect the SoC variant. [0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf Signed-off-by: Bryan Brattlof --- .../boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 5 +++ arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 47 ++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 315d0092e73664416998cb34d9b9f5fa70a311c2..6f32135f00a551cfea4cc896fc03147271eab9b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -20,6 +20,11 @@ chipid: chipid@14 { bootph-all; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi index 41f479dca455567c91bbb3a0b75d13810ea11157..140587d02e88e9d391c41001643ec715d41bf262 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 135 0>; }; @@ -62,6 +63,7 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 136 0>; }; @@ -77,6 +79,7 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 137 0>; }; @@ -92,10 +95,54 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; clocks = <&k3_clks 138 0>; }; }; + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; + l2_0: l2-cache0 { compatible = "cache"; cache-unified; From patchwork Wed Sep 25 14:54:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13812144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 454E7CF9C7A for ; Wed, 25 Sep 2024 15:01:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6kNy+oF+7IH4TdlM7HPfJbKXYAWCEdbMeGLixnsPAxc=; b=mVMLTDn1byo9f6SGv97jH19AwQ h2I+SkiCUm1YlJph1Lf1FxuQzr4/FeF/XMZQenTzOVSLgqrJs0nUP248GNAt7YmiuySc2p6XnNnHx +Cq5DzxmeCbVJnN/8c4oBgEY8Gr5m07Pfb8lfFse1qMfsMLuuedEea3LNm+cJsbFHcHAoBJnCnXnY 7pg0p579BtrFeZITp6YCjT+1q7LRyGo9bHhmnKalGihOI94r+R85/x7bRPRxW1jPl8AgWhefsoOiK hRYj06jFaBY+5ReDe8k3HPDPDD50aIFrY3h1nT9UTD/rXRhBn2KObwKf/3GY/CZl0svGVKZ5cvZJz r9JPPQFA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1stTVW-00000005kly-3wC9; Wed, 25 Sep 2024 15:00:47 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1stTPw-00000005j6I-2YHp for linux-arm-kernel@lists.infradead.org; Wed, 25 Sep 2024 14:55:02 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsuYf073375; Wed, 25 Sep 2024 09:54:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276096; bh=6kNy+oF+7IH4TdlM7HPfJbKXYAWCEdbMeGLixnsPAxc=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=bAVQuBylmq89/IXa1ie+8ftRNXj01PsrpOl/CwAtE/GlCzKSKpekabhGhNrRJ1Pjg PaeAEEspzYZMThk6QHdrqziyzLUmQDiWkL7v9/oWyRzLxpNP5iO0Y3Jg0uhQQFI7Oo 1vCTrfF2BjX1dKauiVEhEcAVub5lFx6i7rkGhjqk= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEsufj019355 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:54:56 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:54:56 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:54:55 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCl110564; Wed, 25 Sep 2024 09:54:52 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:18 +0530 Subject: [PATCH v6 4/6] arm64: dts: ti: k3-am62p5-sk: add 1.4ghz opp entry MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-4-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=1070; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=J2V9iMpCezlqmgozhrln6pQnlfb3x2eF+J3i+JcTGx0=; b=ia9CW9/0ztWYQ+kII9d3XGkREIhnseM8u/xF9AuocdCAwMoZbrecJZ9dCbDOuDaC2Ab95EDfX RLjZ7sm3mqDBcDI7qB9dZvAxqziVfLEW0+vKgZ7JLzH+Z4cLW/N8TdQ X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240925_075500_744320_6DA20139 X-CRM114-Status: GOOD ( 11.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Bryan Brattlof The AM62Px reference board is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 6.6 of the SoC's data sheet[0] . Append the 1.4Ghz entry to the OPP table to enable this frequency [0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf Signed-off-by: Bryan Brattlof --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 3efa12bb72546291e2fda79695edf577bbb134a1..7f3dc39e12bc9ca4a746ff092f946b84a36404b3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -128,6 +128,15 @@ led-0 { }; }; + opp-table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock"; From patchwork Wed Sep 25 14:54:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13812145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7CE8CF9C7B for ; Wed, 25 Sep 2024 15:02:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=zLhShaVN27E261VkbondnBJqweCJB7QrnU+MuM8Qq0E=; b=nPiMafA0IF4rdjiVpvocbOxJXR HbQziKhVrUA7hqCLRTyt29a4Nv6nStTRMY1pHAIjsESMvm63Y4WgP5C8Q0TbEJ1yUwzx6N/Rdslw9 hvhdPk7Zb8CP7bCvo2+9xsIDmZlNoF+ombvHLqM+tljRMc4Q0WTo2KJ1UdXgUn1ouLUM0RYZAK8h7 ROfeK3O6uOBAlq5USlI5/YYQ+VdYPMiprE+Jo0gb0AtcxE8KKZegVV6DHus0Z0WFxD2+/Hwi1WuHm jb2tu6vOQnapTbBZDA5V6FOtC4p0zHoVdo9rAThGzkl6ypx9Th+QllJazgPbjXSStPMIDORtleTdW 2iPSrl1Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1stTWj-00000005lDC-0Xd0; Wed, 25 Sep 2024 15:02:01 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1stTPz-00000005j7C-38GQ for linux-arm-kernel@lists.infradead.org; Wed, 25 Sep 2024 14:55:05 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEt04b019912; Wed, 25 Sep 2024 09:55:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276100; bh=zLhShaVN27E261VkbondnBJqweCJB7QrnU+MuM8Qq0E=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=bEdQdSYQSmod1tr4TH/FieCAdOVIDlZLq7bdimmysaTSctFtmecjo1zHnXKc9FcvS irYtSuC9riarZKaoNXEwRiF1j7D3Lenmkhg9aLukmdbCHMNRF+c8k8XUgSpwqll78A IDg/oXw65kBM4p041Lxhe1Yh7zhcL/+yxRtfAcBI= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEt0Gh101484 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:55:00 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:55:00 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:55:00 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCm110564; Wed, 25 Sep 2024 09:54:56 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:19 +0530 Subject: [PATCH v6 5/6] arm64: dts: ti: k3-am62: use opp_efuse_table for opp-table syscon MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-5-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=2062; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=gmxyRsRvrN/GW7kRQnE8u/bLH36aFbd2B6dpmrkb7U4=; b=87TQHfsigrFfETDy4MqE4neoK+ZwlIhOIs4Bir7A21iSSdRZHCvrRIklJJH880ajHN1oFToft 9shylYjNDXZCGuRJnDWb4HTw/9ZhoyKXOxieL/YhUrlxvTm3bD5lWIe X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240925_075503_889359_0B3A4608 X-CRM114-Status: GOOD ( 14.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add another entry in the wkup_conf for the syscon node, and then use that for the syscon in opp-table. Marking entire wkup_conf as "syscon", "simple-mfd" is wrong and needs to be addressed similar to how other child-nodes in wkup_conf are implemented in the same file. Also, rename syscon to bus and drop reg = <>; Signed-off-by: Dhruva Gole --- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 10 +++++++--- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 +- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index e0afafd532a5c63f29ca0dabc541ffa22dde609b..9933bb55b00532fbd5ea74fc90036ab0eadd50bc 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -8,10 +8,9 @@ #include &cbass_wakeup { - wkup_conf: syscon@43000000 { + wkup_conf: bus@43000000 { bootph-all; - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x43000000 0x00 0x20000>; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x43000000 0x20000>; @@ -22,6 +21,11 @@ chipid: chipid@14 { reg = <0x14 0x4>; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x200 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index c3d1db47dc9f351d217721c0b9e46a0c68995838..c249883a8a8d846aa21092c4c341fd443cfcec15 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -108,7 +108,7 @@ cpu3: cpu@3 { a53_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; opp-shared; - syscon = <&wkup_conf>; + syscon = <&opp_efuse_table>; opp-200000000 { opp-hz = /bits/ 64 <200000000>; From patchwork Wed Sep 25 14:54:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 13812146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66597CF9C7A for ; Wed, 25 Sep 2024 15:03:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SoE3frTgrrAbkkW+0hWzW5YqidptuOBpjGiZMGx02Ew=; b=N3GOoKQ2oUlVwZWmOiOVauzDmv d6N16Y0pgB/NCH4MdLA6gG8HnRWgAnlE38ge1tqbVHuL5bmq1iXdIBhmRqPFshkYfgII8/VEFPXB0 UOmCM0Wg/jrIlqwqRoZqAsECiOKuWVcFaMmXTsvHynAWVbCqvJY6bkNkJXniVm4b7rlydLlStJ9UC b6NQsv2x9iKyolx1acNz4SPwbJ8XFnPao3AzaibfR0LKFMM5ke7daVIf7tX+RhxuKZFq1gOW5cn6Y Nh3soggx+ZRw9SkN17ulKGQcD+LFFqiMT7mUqMFuVJ6No/akNHESVDLQILFW3XiIxyxwoHBPKYYBv VwzxIOYQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1stTXx-00000005lmx-31lq; Wed, 25 Sep 2024 15:03:17 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1stTQ3-00000005j8i-2rY1 for linux-arm-kernel@lists.infradead.org; Wed, 25 Sep 2024 14:55:09 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 48PEt4j0062997; Wed, 25 Sep 2024 09:55:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1727276104; bh=SoE3frTgrrAbkkW+0hWzW5YqidptuOBpjGiZMGx02Ew=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=CDvtJlodjAiDT7Nhnkp/7jYUbnMMzvkawKosGqASR/HqCJ1dsLuM6sWKATA2dHRnY oy2cqf05zgXHk4P8vbvNUGlgpYww7nNURikWbXxltfgF80lIvro4Bg2K5KtsQcAneo MzNGEktsZCQ/ks2QZwAXroZCZ4OmRZP5G0g7ofTo= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 48PEt4D3092264 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Sep 2024 09:55:04 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 25 Sep 2024 09:55:04 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 25 Sep 2024 09:55:04 -0500 Received: from [127.0.1.1] (lcpd911.dhcp.ti.com [172.24.227.226]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 48PEsYCn110564; Wed, 25 Sep 2024 09:55:00 -0500 From: Dhruva Gole Date: Wed, 25 Sep 2024 20:24:20 +0530 Subject: [PATCH v6 6/6] cpufreq: ti-cpufreq: Update efuse/rev offsets in AM62 family MIME-Version: 1.0 Message-ID: <20240925-ti-cpufreq-fixes-v5-v6-6-46f41a903e01@ti.com> References: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> In-Reply-To: <20240925-ti-cpufreq-fixes-v5-v6-0-46f41a903e01@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar CC: , , , , Andrew Davis , Bryan Brattlof , Dhruva Gole X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1727276075; l=2875; i=d-gole@ti.com; s=20240919; h=from:subject:message-id; bh=xdbK3sX33TuJDpUjLbXTCDI0D2SFxjFhg9r0p9JHT54=; b=NmSRfzqh6TLYqUwObdIiSB6IE4akueqjdw/lEC4Fha1Jn88KcxDq7HkAmiVYRgZFBN5G6+uWR jR+3L1vtZzvDViVVX6hXPF+4Cc+vwrPq8p8x5/NQfUR3hut2Ojara8K X-Developer-Key: i=d-gole@ti.com; a=ed25519; pk=k8NnY4RbxVqeqGsYfTHeVn4hPOHkjg7Mii0Ixs4rghM= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240925_075507_879194_C0884E0E X-CRM114-Status: GOOD ( 19.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org With the Silicon revision being taken directly from socinfo, there's no longer any need for reading any SOC register for revision from this driver. Hence, we do not require any rev_offset for AM62 family of devices. The efuse offset should be 0x0 for AM625 as well, as the syscon register being used from DT refers to the efuse_offset directly. However, to maintain the backward compatibility with old devicetree, also add condition to handle the case where we have the wrong offset and add the older efuse_offset value there such that we don't end up reading the wrong register offset. Signed-off-by: Dhruva Gole --- drivers/cpufreq/ti-cpufreq.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index ba621ce1cdda694c98867422dbb7f10c0df2afef..8a97b95b4c44a76b12cab76ddc0f9a5b8ae73f84 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -313,10 +313,9 @@ static const struct soc_device_attribute k3_cpufreq_soc[] = { static struct ti_cpufreq_soc_data am625_soc_data = { .efuse_xlate = am625_efuse_xlate, - .efuse_offset = 0x0018, + .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -325,7 +324,6 @@ static struct ti_cpufreq_soc_data am62a7_soc_data = { .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -334,7 +332,6 @@ static struct ti_cpufreq_soc_data am62p5_soc_data = { .efuse_offset = 0x0, .efuse_mask = 0x07c0, .efuse_shift = 0x6, - .rev_offset = 0x0014, .multi_regulator = false, }; @@ -349,11 +346,25 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, u32 *efuse_value) { struct device *dev = opp_data->cpu_dev; + struct device_node *np = opp_data->opp_node; u32 efuse; int ret; - ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, - &efuse); + /* + * The following check is used as a way to check if this is an older devicetree + * being used where the entire wkup_conf node was marked as "syscon", + * "simple-mfd". + * Since this bug only affects AM625, make sure it enters this condition + * only for that SoC. + */ + if (of_device_is_compatible(np, "simple-mfd") && + of_device_is_compatible(np, "ti,am625")) { + ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset + 0x0018, + &efuse); + } else { + ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, + &efuse); + } if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) { /* not a syscon register! */ void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +