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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e0b6c4bc3bsm49136a91.2.2024.09.26.07.25.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 07:25:12 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id A847E802C9; Thu, 26 Sep 2024 22:32:59 +0800 (CST) From: AlvinZhou To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org Cc: chengminglin@mxic.com.tw, leoyu@mxic.com.tw, AlvinZhou , JaimeLiao Subject: [PATCH v10 1/6] mtd: spi-nor: add Octal DTR support for Macronix flash Date: Thu, 26 Sep 2024 22:19:51 +0800 Message-Id: <20240926141956.2386374-2-alvinzhou.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> References: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: AlvinZhou Create Macronix specify method for enable Octal DTR mode and set 20 dummy cycles to allow running at the maximum supported frequency for Macronix Octal flash. Use number of dummy cycles which is parse by SFDP then convert it to bit pattern and set in CR2 register. Set CR2 register for enable octal DTR mode. Use Read ID to confirm that enabling/disabling octal DTR mode was successful. Macronix ID format is A-A-B-B-C-C in octal DTR mode. To ensure the successful enablement of octal DTR mode, confirm that the 6-byte data is entirely correct. Co-developed-by: Tudor Ambarus Signed-off-by: Tudor Ambarus Signed-off-by: JaimeLiao Signed-off-by: AlvinZhou --- drivers/mtd/spi-nor/macronix.c | 91 ++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index ea6be95e75a5..f039819a5252 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -8,6 +8,24 @@ #include "core.h" +#define MXIC_NOR_OP_RD_CR2 0x71 /* Read configuration register 2 opcode */ +#define MXIC_NOR_OP_WR_CR2 0x72 /* Write configuration register 2 opcode */ +#define MXIC_NOR_ADDR_CR2_MODE 0x00000000 /* CR2 address for setting spi/sopi/dopi mode */ +#define MXIC_NOR_ADDR_CR2_DC 0x00000300 /* CR2 address for setting dummy cycles */ +#define MXIC_NOR_REG_DOPI_EN 0x2 /* Enable Octal DTR */ +#define MXIC_NOR_REG_SPI_EN 0x0 /* Enable SPI */ + +/* Convert dummy cycles to bit pattern */ +#define MXIC_NOR_REG_DC(p) \ + ((20 - (p)) >> 1) + +/* Macronix write CR2 operations */ +#define MXIC_NOR_WR_CR2(addr, ndata, buf) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(MXIC_NOR_OP_WR_CR2, 0), \ + SPI_MEM_OP_ADDR(4, addr, 0), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) + static int mx25l25635_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, @@ -185,6 +203,78 @@ static const struct flash_info macronix_nor_parts[] = { } }; +static int macronix_nor_octal_dtr_en(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf = nor->bouncebuf, i; + int ret; + + /* Use dummy cycles which is parse by SFDP and convert to bit pattern. */ + buf[0] = MXIC_NOR_REG_DC(nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].num_wait_states); + op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_DC, 1, buf); + ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + /* Set the octal and DTR enable bits. */ + buf[0] = MXIC_NOR_REG_DOPI_EN; + op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_MODE, 1, buf); + ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + /* Read flash ID to make sure the switch was successful. */ + ret = spi_nor_read_id(nor, 4, 4, buf, SNOR_PROTO_8_8_8_DTR); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); + return ret; + } + + /* Macronix SPI-NOR flash 8D-8D-8D read ID would get 6 bytes data A-A-B-B-C-C */ + for (i = 0; i < nor->info->id->len; i++) + if (buf[i * 2] != buf[(i * 2) + 1] || buf[i * 2] != nor->info->id->bytes[i]) + return -EINVAL; + + return 0; +} + +static int macronix_nor_octal_dtr_dis(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 *buf = nor->bouncebuf; + int ret; + + /* + * The register is 1-byte wide, but 1-byte transactions are not + * allowed in 8D-8D-8D mode. Since there is no register at the + * next location, just initialize the value to 0 and let the + * transaction go on. + */ + buf[0] = MXIC_NOR_REG_SPI_EN; + buf[1] = 0x0; + op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_MODE, 2, buf); + ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); + if (ret) + return ret; + + /* Read flash ID to make sure the switch was successful. */ + ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); + if (ret) { + dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); + return ret; + } + + if (memcmp(buf, nor->info->id->bytes, nor->info->id->len)) + return -EINVAL; + + return 0; +} + +static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable) +{ + return enable ? macronix_nor_octal_dtr_en(nor) : macronix_nor_octal_dtr_dis(nor); +} + static void macronix_nor_default_init(struct spi_nor *nor) { nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; @@ -194,6 +284,7 @@ static int macronix_nor_late_init(struct spi_nor *nor) { if (!nor->params->set_4byte_addr_mode) nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b; + nor->params->set_octal_dtr = macronix_nor_set_octal_dtr; return 0; } From patchwork Thu Sep 26 14:19:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhou X-Patchwork-Id: 13813415 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CBC11531F9; Thu, 26 Sep 2024 14:25:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727360716; cv=none; b=galnVrf4C+DXbOCQfbSSOkrLgSXUuBVdZODtYTGA3Hx+TE4sVTxLKemqj2oyHaTVaXtuX36CbB5t8zEtKiGgrVEPyFtMxuPJtLxiXBV0OIon/GQKaNH4uyAm/X/2i3aHfsKf4+mV1N+Pe3/6RFjjo1tUAyB6rzz0Z+lOjTHyGag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727360716; 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7e6b7c732c8sm4360707a12.71.2024.09.26.07.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 07:25:14 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 2374780529; Thu, 26 Sep 2024 22:33:01 +0800 (CST) From: AlvinZhou To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org Cc: chengminglin@mxic.com.tw, leoyu@mxic.com.tw, AlvinZhou , JaimeLiao Subject: [PATCH v10 2/6] spi: spi-mem: Allow specifying the byte order in Octal DTR mode Date: Thu, 26 Sep 2024 22:19:52 +0800 Message-Id: <20240926141956.2386374-3-alvinzhou.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> References: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: AlvinZhou From: Tudor Ambarus There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary when configured in Octal DTR mode. The byte order of 16-bit words is swapped when read or written in Octal Double Transfer Rate (DTR) mode compared to Single Transfer Rate (STR) modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2. Swapping the bytes may introduce some endianness problems. It can affect the boot sequence if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1 mode. Therefore, it is necessary to swap the bytes back to ensure the same byte order as in STR modes. Fortunately there are controllers that could swap the bytes back at runtime, addressing the flash's endianness requirements. Provide a way for the upper layers to specify the byte order in Octal DTR mode. Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Suggested-by: Michael Walle Signed-off-by: Tudor Ambarus Signed-off-by: JaimeLiao Signed-off-by: AlvinZhou Acked-by: Mark Brown --- drivers/spi/spi-mem.c | 3 +++ include/linux/spi/spi-mem.h | 8 +++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 17b8baf749e6..abc6792e738c 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -172,6 +172,9 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, if (!spi_mem_controller_is_capable(ctlr, dtr)) return false; + if (op->data.swap16 && !spi_mem_controller_is_capable(ctlr, swap16)) + return false; + if (op->cmd.nbytes != 2) return false; } else { diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index f866d5c8ed32..c46d2b8029be 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -90,6 +90,8 @@ enum spi_mem_data_dir { * @data.buswidth: number of IO lanes used to send/receive the data * @data.dtr: whether the data should be sent in DTR mode or not * @data.ecc: whether error correction is required or not + * @data.swap16: whether the byte order of 16-bit words is swapped when read + * or written in Octal DTR mode compared to STR mode. * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the * operation does not involve transferring data @@ -124,7 +126,8 @@ struct spi_mem_op { u8 buswidth; u8 dtr : 1; u8 ecc : 1; - u8 __pad : 6; + u8 swap16 : 1; + u8 __pad : 5; enum spi_mem_data_dir dir; unsigned int nbytes; union { @@ -297,10 +300,13 @@ struct spi_controller_mem_ops { * struct spi_controller_mem_caps - SPI memory controller capabilities * @dtr: Supports DTR operations * @ecc: Supports operations with error correction + * @swap16: Supports swapping bytes on a 16 bit boundary when configured in + * Octal DTR */ struct spi_controller_mem_caps { bool dtr; bool ecc; + bool swap16; }; #define spi_mem_controller_is_capable(ctlr, cap) \ From patchwork Thu Sep 26 14:19:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhou X-Patchwork-Id: 13813414 Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BF731531ED; Thu, 26 Sep 2024 14:25:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727360716; cv=none; b=tsJ9PGsYI0Ax+M9VwYtY3ywDuSFDSHRn4MXSI9b8bC32TjmYIMFR+W3yEOcpDXoFUcz1E2S02TIFBM5OT/Ym3CoAKqVCH5tTXPfzsrhfXyIo8KuyQjas3jmEjz9veTR+jHLrf9wraaQgXleK91PU2tHDtuchPIYFUHUSUmz/bbk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727360716; c=relaxed/simple; bh=YfVErJFWvQAjc+YAokwbZxUEeqlwW35HO2SBJoUvN7c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pfUzeBGpeCyotQgJ35llfpUxRYguqMnsEkIC5mUZYKB2bn45LTc6lfbvL6EJ+PE71vNBnJ2iwiYpqv0+bMQCSu7bdqmJEDR0EcJBYniKoOXFym04QOkrnN+oc+X64+WhH+Yk8SAbBeui2OaSB9JOvfHd32FJ8dz37DaGBZ8PjMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TvbdpTKC; arc=none smtp.client-ip=209.85.215.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TvbdpTKC" Received: by mail-pg1-f180.google.com with SMTP id 41be03b00d2f7-7ae3d7222d4so832523a12.3; Thu, 26 Sep 2024 07:25:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727360715; x=1727965515; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RGxTXo990ti5lAyVI8ZehxzUFXPwz6MqQx7qAzjMfhw=; b=TvbdpTKCrcPDXzVhaxTAvTmVjsQZWtx7+F7wKBLdz1BMCXMy6H/pyWDKVACOlP/IKD 7uO95OJPDIT1H3C8jEjQKD7M6IAeO0VBg9cr6ZIxRyorP6oDUzeNa4XZTzVx4xMfBRCL jxz5HaqbP48TIHRgo0AB5JDVcyGXInbVOVvFsZn8t8rzzrYNqAZBRgvPOZdNjBX+fu+T EBK7Kp//REjR97mIuiQPpTJBWWPgW5LRi0KHGcmc9M+007YPLFVKT66kgI9PkU16RgIU n/Gww0xu7kqiZ8l9aGQEInVeu18Jo65+OxrpegphxEjF9WwxY8GLWOEnHwkIiV8Ie4Ks TIWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727360715; x=1727965515; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RGxTXo990ti5lAyVI8ZehxzUFXPwz6MqQx7qAzjMfhw=; b=m37TQeuCa9LiPMke2bKzi1KWP0vPrxcH0k9HRVBa6GK2gofOLjsJl8PsEBYAl8NpGJ qzXGoacb5EdDN38EHIMrzu8+vSESOMH5bkjAlTVP4ppfWj9TCVZUcPjETx68N68QljTv imrGmnqsdcGoojCt/ul/+sUglOuWRytI6QAW/eXA0I8vOBWFihw3w2qA9zBCwk53sfk5 juvSF2w4qMLdXxqlQw4pZqKYxejW0U7YN1WVw8aVRaWxqSIrzrDh8yxCZpPHgM90vZJb zUv5sbbtnEJBjby9vOCDZFR/g/7uYZ/qPb/1fOrZM2Rvbg/RxvTtat5SiZAoN2Ake35U z4TA== X-Forwarded-Encrypted: i=1; AJvYcCWI/DJD2HUFwRqAzqSB+LzRnmEMlRQW8xVJr53u3Hq7yZkMsdyusuUzFrFEQ9zeLg0Vj0b/5HCmyE2Au1w=@vger.kernel.org, AJvYcCXAAvMgCcQyks/iH25kh5EI9F3XCH2oXXSeem1ID3VweMlcowk0ODYsrDYIdCLY4SIcWliwDyNKNJAJ@vger.kernel.org X-Gm-Message-State: AOJu0Yy06hO4QFQHzqP37efjbWtC4mbqIi9TGjTtDY7LCV+f0dVNaTkS rNSJDnFKWuTl0cf/9AlonY5XKO2MOH7bQcn4Y2y+DQ9ojEB1IhFp X-Google-Smtp-Source: AGHT+IGJwQwDCJBexl9tEe801nzR8/z6arvXHTxHSnx3fsr9XAE3/M0h4vZLwCeKudo7PtJWcCWLpw== X-Received: by 2002:a05:6a21:78e:b0:1d2:e1cc:649c with SMTP id adf61e73a8af0-1d4d4aaf073mr8517160637.15.1727360714640; Thu, 26 Sep 2024 07:25:14 -0700 (PDT) Received: from twhmp6px (mxsmtp211.mxic.com.tw. [211.75.127.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71afc985c99sm4374462b3a.180.2024.09.26.07.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 07:25:14 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 0432080580; Thu, 26 Sep 2024 22:33:02 +0800 (CST) From: AlvinZhou To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org Cc: chengminglin@mxic.com.tw, leoyu@mxic.com.tw, AlvinZhou , JaimeLiao Subject: [PATCH v10 3/6] mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode Date: Thu, 26 Sep 2024 22:19:53 +0800 Message-Id: <20240926141956.2386374-4-alvinzhou.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> References: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: AlvinZhou From: Tudor Ambarus Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or written in 8D-8D-8D mode compared to STR modes. Allow operations to specify the byte order in DTR mode, so that controllers can swap the bytes back at run-time to address the flash's endianness requirements, if they are capable. If the controller is not capable of swapping the bytes, the protocol is downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the bytes is always done regardless if it's a data or register access, so that it comply with the JESD216 requirements: "Byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1". Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Suggested-by: Michael Walle Signed-off-by: Tudor Ambarus Signed-off-by: JaimeLiao Signed-off-by: AlvinZhou --- drivers/mtd/spi-nor/core.c | 4 ++++ drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 028514c6996f..31f57b17023f 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -113,6 +113,10 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, op->cmd.opcode = (op->cmd.opcode << 8) | ext; op->cmd.nbytes = 2; } + + /* SWAP16 is only applicable when Octal DTR mode */ + if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16) + op->data.swap16 = true; } /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 442786685515..baf6c4b5912b 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -140,6 +140,7 @@ enum spi_nor_option_flags { SNOR_F_RWW = BIT(14), SNOR_F_ECC = BIT(15), SNOR_F_NO_WP = BIT(16), + SNOR_F_SWAP16 = BIT(17), }; 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20af1856f27sm39332645ad.262.2024.09.26.07.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 07:25:16 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id BA021802C9; Thu, 26 Sep 2024 22:33:03 +0800 (CST) From: AlvinZhou To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org Cc: chengminglin@mxic.com.tw, leoyu@mxic.com.tw, AlvinZhou , JaimeLiao Subject: [PATCH v10 4/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Date: Thu, 26 Sep 2024 22:19:54 +0800 Message-Id: <20240926141956.2386374-5-alvinzhou.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> References: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: AlvinZhou From: Tudor Ambarus Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode. This info flag will be used as a basis to determine whether there is byte swapping of data for SPI NOR flash in octal DTR mode. The controller driver will check whether byte swapping is supported to determine whether the corresponding operation are supported, thus avoiding the generation of unexpected data order. Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Reviewed-by: Michael Walle Signed-off-by: Tudor Ambarus Signed-off-by: JaimeLiao Signed-off-by: AlvinZhou --- drivers/mtd/spi-nor/sfdp.c | 4 ++++ drivers/mtd/spi-nor/sfdp.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 5b1117265bd2..21727f9a4ac6 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -671,6 +671,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, return -EOPNOTSUPP; } + /* Byte order in 8D-8D-8D mode */ + if (bfpt.dwords[SFDP_DWORD(18)] & BFPT_DWORD18_BYTE_ORDER_SWAPPED) + nor->flags |= SNOR_F_SWAP16; + return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt); } diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h index da0fe5aa9bb0..d90cbd7331f7 100644 --- a/drivers/mtd/spi-nor/sfdp.h +++ b/drivers/mtd/spi-nor/sfdp.h @@ -130,6 +130,7 @@ struct sfdp_bfpt { #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */ #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */ +#define BFPT_DWORD18_BYTE_ORDER_SWAPPED BIT(31) /* Byte sawp of 16-bit in 8D-8D-8D mode */ struct sfdp_parameter_header { u8 id_lsb; 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20af17e2db1sm39450795ad.178.2024.09.26.07.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 07:25:17 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 44A7A80529; Thu, 26 Sep 2024 22:33:05 +0800 (CST) From: AlvinZhou To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org Cc: chengminglin@mxic.com.tw, leoyu@mxic.com.tw, AlvinZhou , JaimeLiao Subject: [PATCH v10 5/6] spi: mxic: Add support for swapping byte Date: Thu, 26 Sep 2024 22:19:55 +0800 Message-Id: <20240926141956.2386374-6-alvinzhou.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> References: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: AlvinZhou Some SPI-NOR flash swap the bytes on a 16-bit boundary when configured in Octal DTR mode. It means data format D0 D1 D2 D3 would be swapped to D1 D0 D3 D2. So that whether controller support swapping bytes should be checked before enable Octal DTR mode. Add swap byte support on a 16-bit boundary when configured in Octal DTR mode for Macronix xSPI host controller driver. According dtr_swab in operation to enable/disable Macronix xSPI host controller swap byte feature. To make sure swap byte feature is working well, program data in 1S-1S-1S mode then read back and compare read data in 8D-8D-8D mode. This feature have been validated on byte-swap flash and non-byte-swap flash. Macronix xSPI host controller bit "HC_CFG_DATA_PASS" determine the byte swap feature disabled/enabled and swap byte feature is working on 8D-8D-8D mode only. Suggested-by: Michael Walle Signed-off-by: JaimeLiao Signed-off-by: AlvinZhou Acked-by: Mark Brown --- drivers/spi/spi-mxic.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c index 6156d691630a..a669ffa27b65 100644 --- a/drivers/spi/spi-mxic.c +++ b/drivers/spi/spi-mxic.c @@ -294,7 +294,8 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) mxic->regs + HC_CFG); } -static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) +static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags, + bool swap16) { int nio = 1; @@ -305,6 +306,11 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) nio = 2; + if (swap16) + flags &= ~HC_CFG_DATA_PASS; + else + flags |= HC_CFG_DATA_PASS; + return flags | HC_CFG_NIO(nio) | HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) | HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1); @@ -397,7 +403,8 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) return -EINVAL; - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16), + mxic->regs + HC_CFG); writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), mxic->regs + LRD_CFG); @@ -441,7 +448,8 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) return -EINVAL; - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16), + mxic->regs + HC_CFG); writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len), mxic->regs + LWR_CFG); @@ -518,7 +526,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, if (ret) return ret; - writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN), + writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16), mxic->regs + HC_CFG); writel(HC_EN_BIT, mxic->regs + HC_EN); @@ -573,6 +581,7 @@ static const struct spi_controller_mem_ops mxic_spi_mem_ops = { static const struct spi_controller_mem_caps mxic_spi_mem_caps = { .dtr = true, .ecc = true, + .swap16 = true, }; static void mxic_spi_set_cs(struct spi_device *spi, bool lvl) From patchwork Thu Sep 26 14:19:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhou X-Patchwork-Id: 13813418 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53720152E0C; Thu, 26 Sep 2024 14:25:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727360721; cv=none; b=F6mVA2852MeTzANHUpGp8hQ4fOkYkn7x+FpyeJr8qQ6vBeI8KWpuPzhmuA/n0v6cVY8BTpEMD5bfdqGO4G/ZvSXPD0bPqFdIvEyY+0zGxMehW8VGL8fUalk4c2Nb2D/5hIgjaxP7DEyaOKz19/xl1ZYXd2zwJ9DKhLJiU5/8Jnk= ARC-Message-Signature: i=1; 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e085341490sm2751779a91.21.2024.09.26.07.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 07:25:19 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id CB751802C9; Thu, 26 Sep 2024 22:33:06 +0800 (CST) From: AlvinZhou To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org Cc: chengminglin@mxic.com.tw, leoyu@mxic.com.tw, AlvinZhou , JaimeLiao Subject: [PATCH v10 6/6] mtd: spi-nor: add support for Macronix Octal flash Date: Thu, 26 Sep 2024 22:19:56 +0800 Message-Id: <20240926141956.2386374-7-alvinzhou.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> References: <20240926141956.2386374-1-alvinzhou.tw@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: AlvinZhou Adding manufacturer ID 0xC2 at the end of ID table to allow manufacturer fixup to be applied for any Macronix flashes instead of needing to list each flash ID in the ID table. Such as macronix_nor_set_octal_dtr function in the manufacturer fixup can be applied to any Macronix Octal Flashes without the need to add the specific ID in the ID table. Suggested-by: Michael Walle Signed-off-by: JaimeLiao Signed-off-by: AlvinZhou --- drivers/mtd/spi-nor/macronix.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index f039819a5252..1a8ccebdfe0e 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -200,7 +200,9 @@ static const struct flash_info macronix_nor_parts[] = { .name = "mx25l3255e", .size = SZ_4M, .no_sfdp_flags = SECT_4K, - } + }, + /* Need the manufacturer fixups, Keep this last */ + { .id = SNOR_ID(0xc2) } }; static int macronix_nor_octal_dtr_en(struct spi_nor *nor)