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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5389fd5e333sm259724e87.76.2024.09.27.03.32.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2024 03:32:16 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Jagadeesh Kona Cc: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/3] arm64: dts: qcom: sm8550: Change camcc power domain from MMCX to MXC Date: Fri, 27 Sep 2024 13:32:10 +0300 Message-ID: <20240927103212.4154273-2-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240927103212.4154273-1-vladimir.zapolskiy@linaro.org> References: <20240927103212.4154273-1-vladimir.zapolskiy@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Any attempt to enable titan_top_gdsc on SM8550-QRD fails and produces an error message that the gdsc is stuck at 'off' state, this can be easily verified just by setting cci0 status on: cam_cc_titan_top_gdsc status stuck at 'off' WARNING: CPU: 6 PID: 89 at drivers/clk/qcom/gdsc.c:178 gdsc_toggle_logic+0x154/0x168 However if MMCX power domain is replaced by MXC one, it allows to turn titan_top_gdsc on successfully, even if MMCX is remained off according to /sys/kernel/debug/pm_genpd/pm_genpd_summary report. Fixes: e271b59e39a6 ("arm64: dts: qcom: sm8550: Add camera clock controller") Signed-off-by: Vladimir Zapolskiy --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9dc0ee3eb98f..5c07d1b35615 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2846,7 +2846,7 @@ camcc: clock-controller@ade0000 { <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd SM8550_MXC>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; From patchwork Fri Sep 27 10:32:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 13814105 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A8DB156864 for ; Fri, 27 Sep 2024 10:32:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727433141; cv=none; b=gVEF5fhCUPCAHuFDuBe0hJTqwaE5QeI3QXyvfmhPh4s68+HwGyDPZ4uIiRF4apxkDG8vVbs9eDh0iBvCbjG/gI0FZ1QeBIeB7J0Q12+an1Sk8WNV5w7TCihyKzBM9+h50HhQ/B1FiSi2Rn4De59RmWP6zg4sXx62vOVGZX9/WI4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727433141; c=relaxed/simple; bh=5Q3cmv5EQmEMsB47Dt0/46SxxuBAOTXYPTZ6B+4yiFE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=U6GWlE79xUGM369F8MRN/VSIkwdJ42hWa6D0fAXY5lIHxyHBnEYHSHcucxUaJ1hlj9w/Ye1SMgN05egMImZowZqRwnHvZ0uC1isfSDLg84Efc9BHEaRIpEwFJg7mHJibNvqQRhoOswbsv0c0f06bzvAILLNhI2zWikrR7CISl3g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=pEdJHcSl; arc=none smtp.client-ip=209.85.208.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pEdJHcSl" Received: by mail-lj1-f172.google.com with SMTP id 38308e7fff4ca-2f75d0441a8so1256141fa.0 for ; Fri, 27 Sep 2024 03:32:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727433138; x=1728037938; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=52wlC560kwOQzivXvwj4mN7rE9VozvLwChFkY3NipRg=; b=pEdJHcSloeIA2nNjUUZqdJXtydxoTHlc1Vkhi/GLrsYHgO2rN+CCYZbyNoMbmMS/KG sgmlz9Y1mOWlU/rpZO6pVQ3ZIso4cadUphaWsceLawiEf2xtIRv9R8zC9EtzeOeIcpyO P8eI3EM7oBGcJY8NdmndmdW4x+eSnjYfd2AFOPHgCDLgjaV2H62mkdqbMzgISTDhrsBg LU5Ck9v1ggoyNcECqig59ebk8GBZK+0oQMi7u61h0IacuN/r108wwKSdbaNbDEU53mFW PYBZK5MPQ/SNUwqcQV4Drp1aRNe0ZwWGy0X191G5XhmDYp2CySauzTWc+ya7Ji2P7DLM vXtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727433138; x=1728037938; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=52wlC560kwOQzivXvwj4mN7rE9VozvLwChFkY3NipRg=; b=QXbU5ne5MyTWV2Lu3VFQSbjakN0S3QVOFM5LfYhrlzkz8Fn1EacvaxYW5kwYiJnLg3 tif4Ot0TtZrvqPmc0i+3Zi/zywH6J3T6X66GFJF7PdRuLqOBf3d6xIMu18kemEi6b5qe 6KQLcdo8FRartIkRomHABs4kILMIH4U80NKg5S4BZXH55am7b2yfgyHjMqDRhuPSMSaZ /lOAPPDpDDZSLFgONByD9PirZUNZzz9h3nLtffT+bjTiRrxD1eyfy2AsyyNivDiQin+t OT8ecD8uGwi78RW9ognBm1P/ji0DlUDzjGfp4jh1CYVl3fw28RB7u4SzVP7Vqfutf7q0 u6Eg== X-Forwarded-Encrypted: i=1; AJvYcCX7dsd5TbRSjptTfu7r7V/AnJB7K/t7Aq66RsxuZzmdvzucjn1ojlGiYBobX7kf+ucIIVBRpQa99AHtZzND@vger.kernel.org X-Gm-Message-State: AOJu0YzY+jK6QWzjkSvAawzVJ+jNNPKXt8DuKnYfOdmXFi4150XtlzUS 9bcgzt00fssbngoRFbeWBseP8Ox/gzJ1JKgsDdrTw2yZYqdURw6mHqF2nJQaSV4= X-Google-Smtp-Source: AGHT+IEuem5Ukvnh7hEKUSiof3sC+jX4FK3/GktzYOT5D48aCARk19ZzL5cPvnEJ5OxdISqq4g0xGQ== X-Received: by 2002:a05:6512:3e0c:b0:536:9efb:bb19 with SMTP id 2adb3069b0e04-5389fc399b0mr443073e87.3.1727433138192; Fri, 27 Sep 2024 03:32:18 -0700 (PDT) Received: from localhost.localdomain (88-112-131-206.elisa-laajakaista.fi. [88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5389fd5e333sm259724e87.76.2024.09.27.03.32.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2024 03:32:17 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Jagadeesh Kona Cc: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/3] dt-bindings: clock: qcom,sm8450-camcc: do not restrict power domain to MMCX Date: Fri, 27 Sep 2024 13:32:11 +0300 Message-ID: <20240927103212.4154273-3-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240927103212.4154273-1-vladimir.zapolskiy@linaro.org> References: <20240927103212.4154273-1-vladimir.zapolskiy@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 It was unveiled that Qualcomm SM8550 Camera clock controller is attached to MXC power domain, therefore it has to be reflected and generalized in the device tree bindings description. Signed-off-by: Vladimir Zapolskiy --- .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 26afbbe65511..9ef967523987 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -40,12 +40,12 @@ properties: power-domains: maxItems: 1 description: - A phandle and PM domain specifier for the MMCX power domain. + A phandle and PM domain specifier for the supplying power domain. required-opps: maxItems: 1 description: - A phandle to an OPP node describing required MMCX performance point. + A phandle to an OPP node describing the power domain's performance point. reg: maxItems: 1 From patchwork Fri Sep 27 10:32:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Zapolskiy X-Patchwork-Id: 13814107 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BAB2189BA3 for ; Fri, 27 Sep 2024 10:32:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727433145; cv=none; b=nWq6Z8VG0vACrEB4rauFt3RB4X4RtqUfsgzJnDf5JhesthyQjKVNTPHvGmis6HzQmp1yFxk/jgIaS2RGMqMvA1KcSfLOOd9gSM3lG1US07oCeT9l/SiiamRvAoS5qmAOY9EEzhdDxnc6H8aJ1lPTjsuwdFOzpJhcQh3FLsWterw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727433145; c=relaxed/simple; bh=0A1LQywnK3IEs/dJCQF/pjVGz9ROfKsL66sFCOAtKr0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J/t2voEMLiNavj3JqBVeKtuBYlb6f9RDiKK4wWTi5fuUB8TEcaE9pWq8Uj+6mFOI70IDPofPa1jQmgTxxj9YNSxVcrP6taWT6Agqngbl3izvoTIHrz+sVJjKGj4Yta3T9A5xUSNJS35Tlt/37jKUXvG1UzmUluk9yD/WSLhRLn4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hvmdSrbV; arc=none smtp.client-ip=209.85.208.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hvmdSrbV" Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2f75d9833aaso654701fa.3 for ; Fri, 27 Sep 2024 03:32:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727433140; x=1728037940; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M3x4RQzAfiGs4G4EtS1NlPhVbjDckiadnHMOCI+hhBk=; b=hvmdSrbVavR/D5Uwn05ChnzyKCDsJJt1rxFYy8LSJ39KJtPq17IMFU2O3FTnO81+Kz 7lhVOFKaghfp5uHRX4soDoZ4W3jX2ttlyiHJ19oxaVbnIugefegC85vXF0vw9kcdlv6c hNI33AKZTpGmuj1cJ5R0bm0UeC/MXoAvuHKlafhWTjlTQ8CqxS//AcDgeVRDXOt+bIpu wyFJaamSP1HSviCd4Vzl70rnFjQXVACOP1l5lPOFQ8nfVwvoCEtBLCW7MV19HgCjI4OJ zng1cfAGED1I/D5RfC2rU2FN5dhmQe+5sxxaIkbwoxZswFARcdnDGDxfIEToOhhRl1yy WBQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727433140; x=1728037940; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M3x4RQzAfiGs4G4EtS1NlPhVbjDckiadnHMOCI+hhBk=; b=B+SquNwyJyZ8Jamyws16RA3R5/NUxjN95lwUPmj3pbP++2l7yIePLrZbL/2qtmLUJq +D3vzwDnlAsqzca8pa9QCHv7yHULRNUn5qvIdk1X+CXuD0XGNAbdhjxr6jPhMpi0EN1r BNCp0vP+TWJqES9ytDNj0bnsouCAmbHCriBfDmcEOpPpSk6T+MP2mVTWGnr3lJmf/ARx ViAsOkM1B7Anp2FecA+HqGDFXOlZerUWLdTnuI0RJut1/jKwRa4LRpjbVAtQcsYtAksT 4VaJgfV9BFF/vfCwojAlRQ3tI1bQhMQHFDCt9Y0OOrvdCWRma/Bz1sI8T9+NGRBceE8G MSjQ== X-Forwarded-Encrypted: i=1; AJvYcCXewSD4SPfRmL6hs0vwT0xBtJEexHbjfORyd65+0a5Bwhjz89ARrXMpZGy+QW1M6SP8U3CE2CAKFCsgk7nJ@vger.kernel.org X-Gm-Message-State: AOJu0YwAOECbeKiVdOS1hogRMbBSYYyiMbWhFnytrPVp06C0SyUGklN8 XZddlWgwOhp3LURgEhE/XXS31ia4LEQYqcJXnRV8ZbbAdbfxN6EShksJS2dYpGU= X-Google-Smtp-Source: AGHT+IEv9j6EshoAauBGgGokdQ8POVQu/cEHbHUPQhJmCoBBGkI2ZoztPJMY+IG05HKEcAcaQgtUVg== X-Received: by 2002:a05:651c:516:b0:2ef:27fa:1fc4 with SMTP id 38308e7fff4ca-2f9d3e37874mr5383221fa.1.1727433140345; Fri, 27 Sep 2024 03:32:20 -0700 (PDT) Received: from localhost.localdomain (88-112-131-206.elisa-laajakaista.fi. [88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5389fd5e333sm259724e87.76.2024.09.27.03.32.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2024 03:32:18 -0700 (PDT) From: Vladimir Zapolskiy To: Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Jagadeesh Kona Cc: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/3] dt-bindings: clock: qcom,sm8450-camcc: generalize title and description Date: Fri, 27 Sep 2024 13:32:12 +0300 Message-ID: <20240927103212.4154273-4-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240927103212.4154273-1-vladimir.zapolskiy@linaro.org> References: <20240927103212.4154273-1-vladimir.zapolskiy@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently the qcom,sm8450-camcc.yaml IP documentation serves as a description of camera clock controllers of Qualcomm SC8280xp, SM8450, SM8550, SM8650 and X1E80100 SoCs, and there is a room for more controllers to be supported by this device tree bindings documentation in future. Generalize the title and description in the documentation file similarly to a number of other Qualcomm clock controller documentation files. Signed-off-by: Vladimir Zapolskiy Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 9ef967523987..11febb5937f3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Camera Clock & Reset Controller on SM8450 +title: Qualcomm Camera Clock & Reset Controller maintainers: - Vladimir Zapolskiy @@ -12,7 +12,7 @@ maintainers: description: | Qualcomm camera clock control module provides the clocks, resets and power - domains on SM8450. + domains on Qualcomm SoCs. See also: include/dt-bindings/clock/qcom,sc8280xp-camcc.h