From patchwork Fri Sep 27 14:16:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13814367 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC8F813BAE2; Fri, 27 Sep 2024 14:21:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446887; cv=none; b=uUrCaKAoDgpMX3M0GtC9kzNKqyx2bvjzwMfTeNddEi7JKadVb5Bdl9xgsoBjn+hWVJZJd5Yb/fD8OZr+KfvIWEiwKgiOP++yXROkxmvGVutmUQpTyNquhgUntjd1/lCrIX7Sai0q8hkY0wSn1mfyT/wZ1UtznpMNLv3n3wW0XEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446887; c=relaxed/simple; bh=Esi3LywVgXAkX9q5mkmMPV9lH5AHWqgn85hQw1zVPpA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X65KH/ODoIGxqxO4QAPFlBebT9CIGLmtQP1VfylqbUVaZJOYnDyM7AD413VYfNBOOeJl4W1/ZFX553JsL+hjvnceHsseYGBZUBOWASlzSiHQbOj1z65GG2ve910FSs93l9jfhQ+whLk8NaD+QI0PV2LFJgNzckaWIbZMwPHWe4w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 19D3DC4CECD; Fri, 27 Sep 2024 14:21:26 +0000 (UTC) From: Dave Jiang To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org Cc: rafael@kernel.org, bp@alien8.de, dan.j.williams@intel.com, tony.luck@intel.com, dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, ira.weiny@intel.com Subject: [RFC PATCH 1/6] ACPICA: actbl1.h: Add extended linear address mode to MSCIS Date: Fri, 27 Sep 2024 07:16:53 -0700 Message-ID: <20240927142108.1156362-2-dave.jiang@intel.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240927142108.1156362-1-dave.jiang@intel.com> References: <20240927142108.1156362-1-dave.jiang@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 ECN for "Extended-linear" addressing for direct-mapped memory-side caches adds a field in the SRAT Memory Side CAche Information Structure to indicate the address mode at the previously reserved bytes at offset 28. The field is described as: When Address Mode is 1 'Extended-Linear' it indicates that the associated address range (SRAT.MemoryAffinityStructure.Length) is comprised of the backing store capacity extended by the cache capacity. It is arranged such that there are N directly addressable aliases of a given cacheline where N is an integer ratio of target memory proximity domain size and the memory side cache size. Where the N aliased addresses for a given cacheline all share the same result for the operation 'address modulo cache size'. This setting is only allowed when 'Cache Associativity' is 'Direct Map'." Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/ Link: https://github.com/acpica/acpica/pull/961 Signed-off-by: Dave Jiang --- include/acpi/actbl1.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 841ef9f22795..95ddc858a0c3 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1791,7 +1791,7 @@ struct acpi_hmat_cache { u32 reserved1; u64 cache_size; u32 cache_attributes; - u16 reserved2; + u16 address_mode; u16 number_of_SMBIOShandles; }; @@ -1803,6 +1803,9 @@ struct acpi_hmat_cache { #define ACPI_HMAT_WRITE_POLICY (0x0000F000) #define ACPI_HMAT_CACHE_LINE_SIZE (0xFFFF0000) +#define ACPI_HMAT_CACHE_MODE_UNKNOWN (0) +#define ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR (1) + /* Values for cache associativity flag */ #define ACPI_HMAT_CA_NONE (0) From patchwork Fri Sep 27 14:16:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13814368 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DB8413BAE2; Fri, 27 Sep 2024 14:21:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446888; cv=none; b=PxaHX2ztwMeQdO2X9hmh16MgyIq249Uq9if7Py7fEjj0yFtIM8kNY77o47n91JINwws4u3XI/yxElb0JpExU2S7/SMJfA/4Qix0bHu3EBO9FvDLZqhi1BmrVFVdG/BBuufQjrWjLF3daSoDlssZ2orTq/xeeuDNKzpTIsfr+4YQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446888; c=relaxed/simple; bh=M5wmaOSVmFqYER+AYdFD/zdHq9k63cGay2sdlIqNpQA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LgEf7t5i3cOxuJDE9Tij/U5SNAO8TOGNv4neoZklgd0Ebpww/uBZF4YdDJqok5QXyhvmhqRvfKyrKHj/KEja2uhPV41x9LI5TxOtd7XMAWE9Va11IePToKBV9ro/ua8O7L1rLy3F/cPgQZWiGcUu5SB/uERJGxmQ0zok+RYsOCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id A84F8C4CEC6; Fri, 27 Sep 2024 14:21:27 +0000 (UTC) From: Dave Jiang To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org Cc: rafael@kernel.org, bp@alien8.de, dan.j.williams@intel.com, tony.luck@intel.com, dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, ira.weiny@intel.com Subject: [RFC PATCH 2/6] acpi: numa: Add support to enumerate and store extended linear address mode Date: Fri, 27 Sep 2024 07:16:54 -0700 Message-ID: <20240927142108.1156362-3-dave.jiang@intel.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240927142108.1156362-1-dave.jiang@intel.com> References: <20240927142108.1156362-1-dave.jiang@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Store the address mode as part of the cache attriutes. Export the mode attribute to sysfs as all other cache attributes. Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/ Signed-off-by: Dave Jiang --- Documentation/ABI/stable/sysfs-devices-node | 7 +++++++ drivers/acpi/numa/hmat.c | 3 +++ drivers/base/node.c | 2 ++ include/linux/node.h | 7 +++++++ 4 files changed, 19 insertions(+) diff --git a/Documentation/ABI/stable/sysfs-devices-node b/Documentation/ABI/stable/sysfs-devices-node index 402af4b2b905..9016cc4f027c 100644 --- a/Documentation/ABI/stable/sysfs-devices-node +++ b/Documentation/ABI/stable/sysfs-devices-node @@ -177,6 +177,13 @@ Description: The cache write policy: 0 for write-back, 1 for write-through, other or unknown. +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/mode +Date: September 2024 +Contact: Dave Jiang +Description: + The address mode: 0 for reserved, 1 for extended-lniear, + other unknown. + What: /sys/devices/system/node/nodeX/x86/sgx_total_bytes Date: November 2021 Contact: Jarkko Sakkinen diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c index 1a902a02390f..39524f36be5b 100644 --- a/drivers/acpi/numa/hmat.c +++ b/drivers/acpi/numa/hmat.c @@ -506,6 +506,9 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, switch ((attrs & ACPI_HMAT_CACHE_ASSOCIATIVITY) >> 8) { case ACPI_HMAT_CA_DIRECT_MAPPED: tcache->cache_attrs.indexing = NODE_CACHE_DIRECT_MAP; + /* Extended Linear mode is only valid if cache is direct mapped */ + if (cache->address_mode == ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR) + tcache->cache_attrs.mode = NODE_CACHE_MODE_EXTENDED_LINEAR; break; case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING: tcache->cache_attrs.indexing = NODE_CACHE_INDEXED; diff --git a/drivers/base/node.c b/drivers/base/node.c index eb72580288e6..744be5470728 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -244,12 +244,14 @@ CACHE_ATTR(size, "%llu") CACHE_ATTR(line_size, "%u") CACHE_ATTR(indexing, "%u") CACHE_ATTR(write_policy, "%u") +CACHE_ATTR(mode, "%u") static struct attribute *cache_attrs[] = { &dev_attr_indexing.attr, &dev_attr_size.attr, &dev_attr_line_size.attr, &dev_attr_write_policy.attr, + &dev_attr_mode.attr, NULL, }; ATTRIBUTE_GROUPS(cache); diff --git a/include/linux/node.h b/include/linux/node.h index 9a881c2208b3..589951c5e36f 100644 --- a/include/linux/node.h +++ b/include/linux/node.h @@ -57,6 +57,11 @@ enum cache_write_policy { NODE_CACHE_WRITE_OTHER, }; +enum cache_mode { + NODE_CACHE_MODE_UNKOWN, + NODE_CACHE_MODE_EXTENDED_LINEAR, +}; + /** * struct node_cache_attrs - system memory caching attributes * @@ -65,6 +70,7 @@ enum cache_write_policy { * @size: Total size of cache in bytes * @line_size: Number of bytes fetched on a cache miss * @level: The cache hierarchy level + * @mode: The address mode */ struct node_cache_attrs { enum cache_indexing indexing; @@ -72,6 +78,7 @@ struct node_cache_attrs { u64 size; u16 line_size; u8 level; + u16 mode; }; #ifdef CONFIG_HMEM_REPORTING From patchwork Fri Sep 27 14:16:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13814369 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EBEA143C41; Fri, 27 Sep 2024 14:21:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446889; cv=none; b=CiHYHlHerNvSzKGxGFcdFZ8HA40nKekP9XnBIgSsSnWoLMToBDtR0hX83wyvPbRmhSKe8ySmDCxdTEvDPN6QfpXbL5YBhOigyNStQwJsda9ioYwBqAvZMBtlHnIQqWNdogCAltZO+sApPL/YIDLlT+656CgKbZiAkG3At3Xxf4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446889; c=relaxed/simple; bh=JR+boErfx6HXPEBQqZPJG07E0KCfZi2RTSJxp/+ITcI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NXj2durZR/SI9JxPMQM4gw29DjQeX/Jsb+qqS8R+EFcN8Kr+v0QD/KhLPEKbvqMK0c9GUA+a1sZFsg0HPZF1Gkv2CtOG2CA1i8HEdYE5ePfKYpTsQ/1jhRnZYQxNTclgn+SibJBYoHey/yZzIxuFOKmTDjXTgU/IpXLsbQ545IU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2EF93C4CEC4; Fri, 27 Sep 2024 14:21:29 +0000 (UTC) From: Dave Jiang To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org Cc: rafael@kernel.org, bp@alien8.de, dan.j.williams@intel.com, tony.luck@intel.com, dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, ira.weiny@intel.com Subject: [RFC PATCH 3/6] acpi/hmat / cxl: Add extended linear cache support for CXL Date: Fri, 27 Sep 2024 07:16:55 -0700 Message-ID: <20240927142108.1156362-4-dave.jiang@intel.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240927142108.1156362-1-dave.jiang@intel.com> References: <20240927142108.1156362-1-dave.jiang@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The current cxl region size only indicates the size of the CXL memory region without accounting for the extended linear cache size. Retrieve the cache size from HMAT and append that to the cxl region size for the cxl region range that matches the SRAT range that has extended linear cache enabled. The SRAT defines the whole memory range that inclues the extended linear cache and the CXL memory region. The new HMAT update to the Memory Side Cache Information Structure defines the size of the extended linear cache size and matches to the SRAT Memory Affinity Structure by the memory proxmity domain. Add a helper to match the cxl range to the SRAT memory range in order to retrieve the cache size. There are several places that checks the cxl region range against the decoder range. Use new helper to check between the two ranges and address the new cache size. Signed-off-by: Dave Jiang --- drivers/acpi/numa/hmat.c | 44 +++++++++++++++++++++++++++++++++ drivers/cxl/core/Makefile | 1 + drivers/cxl/core/acpi.c | 11 +++++++++ drivers/cxl/core/core.h | 3 +++ drivers/cxl/core/region.c | 51 ++++++++++++++++++++++++++++++++++++--- drivers/cxl/cxl.h | 2 ++ include/linux/acpi.h | 8 ++++++ tools/testing/cxl/Kbuild | 1 + 8 files changed, 117 insertions(+), 4 deletions(-) create mode 100644 drivers/cxl/core/acpi.c diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c index 39524f36be5b..d299f8d7af8c 100644 --- a/drivers/acpi/numa/hmat.c +++ b/drivers/acpi/numa/hmat.c @@ -108,6 +108,50 @@ static struct memory_target *find_mem_target(unsigned int mem_pxm) return NULL; } +/** + * hmat_get_extended_linear_cache_size - Retrieve the extended linear cache size + * @backing_res: resource from the backing media + * @nid: node id for the memory region + * @cache_size: (Output) size of extended linear cache. + * + * Return: 0 on success. Errno on failure. + * + */ +int hmat_get_extended_linear_cache_size(struct resource *backing_res, int nid, + resource_size_t *cache_size) +{ + unsigned int pxm = node_to_pxm(nid); + struct memory_target *target; + struct target_cache *tcache; + bool cache_found = false; + struct resource *res; + + target = find_mem_target(pxm); + if (!target) + return -ENOENT; + + list_for_each_entry(tcache, &target->caches, node) { + if (tcache->cache_attrs.mode == NODE_CACHE_MODE_EXTENDED_LINEAR) { + cache_found = true; + break; + } + } + + if (!cache_found) { + *cache_size = 0; + return 0; + } + + res = &target->memregions; + if (!resource_contains(res, backing_res)) + return -ENOENT; + + *cache_size = tcache->cache_attrs.size; + + return 0; +} +EXPORT_SYMBOL_NS_GPL(hmat_get_extended_linear_cache_size, CXL); + static struct memory_target *acpi_find_genport_target(u32 uid) { struct memory_target *target; diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 9259bcc6773c..1a0c9c6ca818 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -14,5 +14,6 @@ cxl_core-y += pci.o cxl_core-y += hdm.o cxl_core-y += pmu.o cxl_core-y += cdat.o +cxl_core-y += acpi.o cxl_core-$(CONFIG_TRACING) += trace.o cxl_core-$(CONFIG_CXL_REGION) += region.o diff --git a/drivers/cxl/core/acpi.c b/drivers/cxl/core/acpi.c new file mode 100644 index 000000000000..f13b4dae6ac5 --- /dev/null +++ b/drivers/cxl/core/acpi.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2024 Intel Corporation. All rights reserved. */ +#include +#include "cxl.h" +#include "core.h" + +int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res, + int nid, resource_size_t *size) +{ + return hmat_get_extended_linear_cache_size(backing_res, nid, size); +} diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 72a506c9dbd0..dd586c76c773 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -108,4 +108,7 @@ int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr, enum access_coordinate_class access); bool cxl_need_node_perf_attrs_update(int nid); +int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res, + int nid, resource_size_t *size); + #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 21ad5f242875..ddfb1e1a8909 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -816,6 +816,17 @@ static int match_free_decoder(struct device *dev, void *data) return 0; } +static bool region_res_match_range(struct cxl_region_params *p, + struct range *range) +{ + if (p->res && + p->res->start + p->cache_size == range->start && + p->res->end == range->end) + return true; + + return false; +} + static int match_auto_decoder(struct device *dev, void *data) { struct cxl_region_params *p = data; @@ -828,7 +839,7 @@ static int match_auto_decoder(struct device *dev, void *data) cxld = to_cxl_decoder(dev); r = &cxld->hpa_range; - if (p->res && p->res->start == r->start && p->res->end == r->end) + if (region_res_match_range(p, r)) return 1; return 0; @@ -1406,8 +1417,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) { if (cxld->interleave_ways != iw || cxld->interleave_granularity != ig || - cxld->hpa_range.start != p->res->start || - cxld->hpa_range.end != p->res->end || + !region_res_match_range(p, &cxld->hpa_range) || ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)) { dev_err(&cxlr->dev, "%s:%s %s expected iw: %d ig: %d %pr\n", @@ -1931,7 +1941,7 @@ static int cxl_region_attach(struct cxl_region *cxlr, return -ENXIO; } - if (resource_size(cxled->dpa_res) * p->interleave_ways != + if (resource_size(cxled->dpa_res) * p->interleave_ways + p->cache_size != resource_size(p->res)) { dev_dbg(&cxlr->dev, "%s:%s: decoder-size-%#llx * ways-%d != region-size-%#llx\n", @@ -3226,6 +3236,34 @@ static int match_region_by_range(struct device *dev, void *data) return rc; } +static int cxl_extended_linear_cache_resize(struct cxl_region_params *p, + struct resource *res) +{ + int nid = phys_to_target_node(res->start); + resource_size_t size, cache_size; + int rc; + + size = resource_size(res); + if (!size) + return -EINVAL; + + rc = cxl_acpi_get_extended_linear_cache_size(res, nid, &cache_size); + if (rc) + return rc; + + if (!cache_size) + return 0; + + if (size != cache_size) + return -EINVAL; + + res->start -= cache_size; + p->cache_size = cache_size; + + return 0; +} + + /* Establish an empty region covering the given HPA range */ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, struct cxl_endpoint_decoder *cxled) @@ -3272,6 +3310,11 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, *res = DEFINE_RES_MEM_NAMED(hpa->start, range_len(hpa), dev_name(&cxlr->dev)); + + rc = cxl_extended_linear_cache_resize(p, res); + if (rc) + goto err; + rc = insert_resource(cxlrd->res, res); if (rc) { /* diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 9afb407d438f..d8d715090779 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -483,6 +483,7 @@ enum cxl_config_state { * @res: allocated iomem capacity for this region * @targets: active ordered targets in current decoder configuration * @nr_targets: number of targets + * @cache_size: extended linear cache size, if exists * * State transitions are protected by the cxl_region_rwsem */ @@ -494,6 +495,7 @@ struct cxl_region_params { struct resource *res; struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE]; int nr_targets; + resource_size_t cache_size; }; /* diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 0687a442fec7..8ed72d431dca 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -435,12 +435,20 @@ int thermal_acpi_critical_trip_temp(struct acpi_device *adev, int *ret_temp); #ifdef CONFIG_ACPI_HMAT int acpi_get_genport_coordinates(u32 uid, struct access_coordinate *coord); +int hmat_get_extended_linear_cache_size(struct resource *backing_res, int nid, + resource_size_t *size); #else static inline int acpi_get_genport_coordinates(u32 uid, struct access_coordinate *coord) { return -EOPNOTSUPP; } + +static inline int hmat_get_extended_linear_cache_size(struct resource *backing_res, + int nid, resource_size_t *size) +{ + return -EOPNOTSUPP; +} #endif #ifdef CONFIG_ACPI_NUMA diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 3d1ca9e38b1f..c687ef56717d 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -61,6 +61,7 @@ cxl_core-y += $(CXL_CORE_SRC)/pci.o cxl_core-y += $(CXL_CORE_SRC)/hdm.o cxl_core-y += $(CXL_CORE_SRC)/pmu.o cxl_core-y += $(CXL_CORE_SRC)/cdat.o +cxl_core-y += $(CXL_CORE_SRC)/acpi.o cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o cxl_core-y += config_check.o From patchwork Fri Sep 27 14:16:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13814370 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AD75136663; Fri, 27 Sep 2024 14:21:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446891; cv=none; b=FJm8eX+JkFEFo2BNl2kPqLfNd8cFgPZW6CcJXm3TcnWuvSmS6o3bNBlSCzEUt+TOjLQVr5fm+rfZX4abze+gYVyvMxAWARiGJHvgosjgGvu2FQfL22vdJGLeTjPEtnx+zHtI2fml0J9BQztDSFEpEjLQW49ew+vwYBbRAI/3PWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446891; c=relaxed/simple; bh=+wJblkzFJhX4Kh4BgSUg6zKsdPlDfLrf6cLrqJxyKvc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OIvHlzqJd6hydOy6UxyawdQaw9KBPmlgiczwmfO/KhLUmTo4kzLnbUNaRUe1w1tMzZmFNxREqCYhpgGNYD2e5M+E56CvamW93kwiU/JdmFMDeMZq8YSl9ezFBfTnTgl+oEggcV2oFoKRd1H/8vYiqkNKs5nFSWXfkVEpO3qBLvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id B67C3C4CECE; Fri, 27 Sep 2024 14:21:30 +0000 (UTC) From: Dave Jiang To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org Cc: rafael@kernel.org, bp@alien8.de, dan.j.williams@intel.com, tony.luck@intel.com, dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, ira.weiny@intel.com Subject: [RFC PATCH 4/6] acpi/hmat: Add helper functions to provide extended linear cache translation Date: Fri, 27 Sep 2024 07:16:56 -0700 Message-ID: <20240927142108.1156362-5-dave.jiang@intel.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240927142108.1156362-1-dave.jiang@intel.com> References: <20240927142108.1156362-1-dave.jiang@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add helper functions to help do address translation for either the address of the extended linear cache or its alias address. The translation function attempt to detect an I/O hole in the proximity domain and adjusts the address if the hole impacts the aliasing of the address. The range of the I/O hole is retrieved by walking through the associated memory target resources. Signed-off-by: Dave Jiang --- drivers/acpi/numa/hmat.c | 136 +++++++++++++++++++++++++++++++++++++++ include/linux/acpi.h | 14 ++++ 2 files changed, 150 insertions(+) diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c index d299f8d7af8c..834314582f4c 100644 --- a/drivers/acpi/numa/hmat.c +++ b/drivers/acpi/numa/hmat.c @@ -152,6 +152,142 @@ int hmat_get_extended_linear_cache_size(struct resource *backing_res, int nid, } EXPORT_SYMBOL_NS_GPL(hmat_get_extended_linear_cache_size, CXL); +static int alias_address_find_iohole(struct memory_target *target, + u64 address, u64 alias, struct range *hole) +{ + struct resource *alias_res = NULL; + struct resource *res, *prev; + + *hole = (struct range) { + .start = 0, + .end = -1, + }; + + /* First find the resource that the address is in */ + prev = target->memregions.child; + for (res = target->memregions.child; res; res = res->sibling) { + if (alias >= res->start && alias <= res->end) { + alias_res = res; + break; + } + prev = res; + } + if (!alias_res) + return -EINVAL; + + /* No memory hole */ + if (alias_res == prev) + return 0; + + /* If address is within the current resource, no need to deal with memory hole */ + if (address >= alias_res->start) + return 0; + + *hole = (struct range) { + .start = prev->end + 1, + .end = alias_res->start - 1, + }; + + return 0; +} + +int hmat_extended_linear_cache_alias_xlat(u64 address, u64 *alias, int nid) +{ + unsigned int pxm = node_to_pxm(nid); + struct memory_target *target; + struct range iohole; + int rc; + + target = find_mem_target(pxm); + if (!target) + return -EINVAL; + + rc = alias_address_find_iohole(target, address, *alias, &iohole); + if (rc) + return rc; + + if (!range_len(&iohole)) + return 0; + + if (address < iohole.start) { + if (*alias > iohole.start) { + *alias = *alias + range_len(&iohole); + return 0; + } + } + + return 0; +} +EXPORT_SYMBOL_NS_GPL(hmat_extended_linear_cache_alias_xlat, CXL); + +static int target_address_find_iohole(struct memory_target *target, + u64 address, u64 alias, + struct range *hole) +{ + struct resource *addr_res = NULL; + struct resource *res, *next; + + *hole = (struct range) { + .start = 0, + .end = -1, + }; + + /* First find the resource that the address is in */ + for (res = target->memregions.child; res; res = res->sibling) { + if (address >= res->start && address <= res->end) { + addr_res = res; + break; + } + } + if (!addr_res) + return -EINVAL; + + next = res->sibling; + /* No memory hole after the region */ + if (!next) + return 0; + + /* If alias is within the current resource, no need to deal with memory hole */ + if (alias <= addr_res->end) + return 0; + + *hole = (struct range) { + .start = addr_res->end + 1, + .end = next->start - 1, + }; + + return 0; +} + +int hmat_extended_linear_cache_address_xlat(u64 *address, u64 alias, int nid) +{ + unsigned int pxm = node_to_pxm(nid); + struct memory_target *target; + struct range iohole; + int rc; + + target = find_mem_target(pxm); + if (!target) + return -EINVAL; + + rc = target_address_find_iohole(target, *address, alias, &iohole); + if (rc) + return rc; + + if (!range_len(&iohole)) + return 0; + + if (alias > iohole.end) { + if (*address < iohole.end) { + *address = *address - range_len(&iohole); + return 0; + } + } + + return 0; +} +EXPORT_SYMBOL_NS_GPL(hmat_extended_linear_cache_address_xlat, CXL); + static struct memory_target *acpi_find_genport_target(u32 uid) { struct memory_target *target; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 8ed72d431dca..704bdfc79f85 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -437,6 +437,8 @@ int thermal_acpi_critical_trip_temp(struct acpi_device *adev, int *ret_temp); int acpi_get_genport_coordinates(u32 uid, struct access_coordinate *coord); int hmat_get_extended_linear_cache_size(struct resource *backing_res, int nid, resource_size_t *size); +int hmat_extended_linear_cache_alias_xlat(u64 address, u64 *alias, int nid); +int hmat_extended_linear_cache_address_xlat(u64 *address, u64 alias, int nid); #else static inline int acpi_get_genport_coordinates(u32 uid, struct access_coordinate *coord) @@ -449,6 +451,18 @@ static inline int hmat_get_extended_linear_cache_size(struct resource *backing_r { return -EOPNOTSUPP; } + +static inline int hmat_extended_linear_cache_alias_xlat(u64 address, + u64 *alias, int nid) +{ + return -EOPNOTSUPP; +} + +static inline int hmat_extended_linear_cache_address_xlat(u64 *address, + u64 alias, int nid) +{ + return -EOPNOTSUPP; +} #endif #ifdef CONFIG_ACPI_NUMA From patchwork Fri Sep 27 14:16:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13814371 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9E0F136E37; Fri, 27 Sep 2024 14:21:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446892; cv=none; b=uelEwWDBOoQFF8g/BC6Jy2ZPfKvapgalegXLO8dGJ6IJWjgO5CmjZ+78vqwj/JZY2uuIwvPrtf6kGWOgmuKPWSUjqr0NgUL3djLHcaxaQdi6eU/pGKeZxO377adllBKd+XUsiNzqSNfjMmDLa6DBrcc6Bvd+3mqNF6AkWmr1KbU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446892; c=relaxed/simple; bh=MC3hXDH8Z2YLy0PkBiaSQSFMohdBFEpD1oj0/nxPJo0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rdkYph3gux1aMt1XZgIllYBu4ZTOvoZraYm2qkx/FGtNIKT3l+R7v9OTVI7t1Ao/I88/ai2U59I6exlQHC5d3PyHOciksLYz5bJjiEynyANV2wPyljN5ZxbOyDltJk0DD+ML4MnYyxNoZamPO2uHbqPaftnSLBYNBMK9isfubcY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3D1BFC4CEC4; Fri, 27 Sep 2024 14:21:32 +0000 (UTC) From: Dave Jiang To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org Cc: rafael@kernel.org, bp@alien8.de, dan.j.williams@intel.com, tony.luck@intel.com, dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, ira.weiny@intel.com Subject: [RFC PATCH 5/6] cxl: Add extended linear cache address alias emission for cxl events Date: Fri, 27 Sep 2024 07:16:57 -0700 Message-ID: <20240927142108.1156362-6-dave.jiang@intel.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240927142108.1156362-1-dave.jiang@intel.com> References: <20240927142108.1156362-1-dave.jiang@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the aliased address of exteneded linear cache when emitting event trace for DRAM and general media of CXL events. Signed-off-by: Dave Jiang --- drivers/cxl/core/acpi.c | 10 ++++++++++ drivers/cxl/core/core.h | 7 +++++++ drivers/cxl/core/mbox.c | 42 ++++++++++++++++++++++++++++++++++++--- drivers/cxl/core/region.c | 2 +- drivers/cxl/core/trace.h | 24 ++++++++++++++-------- 5 files changed, 73 insertions(+), 12 deletions(-) diff --git a/drivers/cxl/core/acpi.c b/drivers/cxl/core/acpi.c index f13b4dae6ac5..f74136320fc3 100644 --- a/drivers/cxl/core/acpi.c +++ b/drivers/cxl/core/acpi.c @@ -9,3 +9,13 @@ int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res, { return hmat_get_extended_linear_cache_size(backing_res, nid, size); } + +int cxl_acpi_extended_linear_cache_address_xlat(u64 *address, u64 alias, int nid) +{ + return hmat_extended_linear_cache_address_xlat(address, alias, nid); +} + +int cxl_acpi_extended_linear_cache_alias_xlat(u64 address, u64 *alias, int nid) +{ + return hmat_extended_linear_cache_alias_xlat(address, alias, nid); +} diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index dd586c76c773..f23bff1b38a6 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -30,8 +30,13 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port); struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa); u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, u64 dpa); +int cxl_region_nid(struct cxl_region *cxlr); #else +static inline int cxl_region_nid(struct cxl_region *cxlr) +{ + return NUMA_NO_NODE; +} static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, u64 dpa) { @@ -110,5 +115,7 @@ bool cxl_need_node_perf_attrs_update(int nid); int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res, int nid, resource_size_t *size); +int cxl_acpi_extended_linear_cache_address_xlat(u64 *address, u64 alias, int nid); +int cxl_acpi_extended_linear_cache_alias_xlat(u64 address, u64 *alias, int nid); #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index e5cdeafdf76e..ac170fd85a1a 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -849,6 +849,39 @@ int cxl_enumerate_cmds(struct cxl_memdev_state *mds) } EXPORT_SYMBOL_NS_GPL(cxl_enumerate_cmds, CXL); +static u64 cxlr_hpa_cache_alias(struct cxl_region *cxlr, u64 hpa) +{ + struct cxl_region_params *p = &cxlr->params; + u64 alias, address; + int nid, rc; + + if (!p->cache_size) + return ~0ULL; + + nid = cxl_region_nid(cxlr); + if (nid == NUMA_NO_NODE) + nid = 0; + + if (hpa >= p->res->start + p->cache_size) { + address = hpa - p->cache_size; + alias = hpa; + rc = cxl_acpi_extended_linear_cache_address_xlat(&address, + alias, nid); + if (rc) + return rc; + + return address; + } + + address = hpa; + alias = hpa + p->cache_size; + rc = cxl_acpi_extended_linear_cache_alias_xlat(address, &alias, nid); + if (rc) + return rc; + + return alias; +} + void cxl_event_trace_record(const struct cxl_memdev *cxlmd, enum cxl_event_log_type type, enum cxl_event_type event_type, @@ -864,7 +897,7 @@ void cxl_event_trace_record(const struct cxl_memdev *cxlmd, } if (trace_cxl_general_media_enabled() || trace_cxl_dram_enabled()) { - u64 dpa, hpa = ULLONG_MAX; + u64 dpa, hpa = ULLONG_MAX, hpa_alias; struct cxl_region *cxlr; /* @@ -880,11 +913,14 @@ void cxl_event_trace_record(const struct cxl_memdev *cxlmd, if (cxlr) hpa = cxl_dpa_to_hpa(cxlr, cxlmd, dpa); + hpa_alias = cxlr_hpa_cache_alias(cxlr, hpa); + if (event_type == CXL_CPER_EVENT_GEN_MEDIA) trace_cxl_general_media(cxlmd, type, cxlr, hpa, - &evt->gen_media); + hpa_alias, &evt->gen_media); else if (event_type == CXL_CPER_EVENT_DRAM) - trace_cxl_dram(cxlmd, type, cxlr, hpa, &evt->dram); + trace_cxl_dram(cxlmd, type, cxlr, hpa, hpa_alias, + &evt->dram); } } EXPORT_SYMBOL_NS_GPL(cxl_event_trace_record, CXL); diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index ddfb1e1a8909..c19bbbf8079d 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -2401,7 +2401,7 @@ static bool cxl_region_update_coordinates(struct cxl_region *cxlr, int nid) return true; } -static int cxl_region_nid(struct cxl_region *cxlr) +int cxl_region_nid(struct cxl_region *cxlr) { struct cxl_region_params *p = &cxlr->params; struct resource *res; diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index 9167cfba7f59..79bee3fd7d25 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -316,9 +316,10 @@ TRACE_EVENT(cxl_generic_event, TRACE_EVENT(cxl_general_media, TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, - struct cxl_region *cxlr, u64 hpa, struct cxl_event_gen_media *rec), + struct cxl_region *cxlr, u64 hpa, u64 hpa_alias, + struct cxl_event_gen_media *rec), - TP_ARGS(cxlmd, log, cxlr, hpa, rec), + TP_ARGS(cxlmd, log, cxlr, hpa, hpa_alias, rec), TP_STRUCT__entry( CXL_EVT_TP_entry @@ -332,6 +333,7 @@ TRACE_EVENT(cxl_general_media, __array(u8, comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE) /* Following are out of order to pack trace record */ __field(u64, hpa) + __field(u64, hpa_alias) __field_struct(uuid_t, region_uuid) __field(u16, validity_flags) __field(u8, rank) @@ -358,6 +360,7 @@ TRACE_EVENT(cxl_general_media, CXL_EVENT_GEN_MED_COMP_ID_SIZE); __entry->validity_flags = get_unaligned_le16(&rec->media_hdr.validity_flags); __entry->hpa = hpa; + __entry->hpa_alias = hpa_alias; if (cxlr) { __assign_str(region_name); uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); @@ -370,7 +373,7 @@ TRACE_EVENT(cxl_general_media, CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \ "descriptor='%s' type='%s' transaction_type='%s' channel=%u rank=%u " \ "device=%x comp_id=%s validity_flags='%s' " \ - "hpa=%llx region=%s region_uuid=%pUb", + "hpa=%llx hpa_alias=%llx region=%s region_uuid=%pUb", __entry->dpa, show_dpa_flags(__entry->dpa_flags), show_event_desc_flags(__entry->descriptor), show_mem_event_type(__entry->type), @@ -378,7 +381,8 @@ TRACE_EVENT(cxl_general_media, __entry->channel, __entry->rank, __entry->device, __print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE), show_valid_flags(__entry->validity_flags), - __entry->hpa, __get_str(region_name), &__entry->region_uuid + __entry->hpa, __entry->hpa_alias, __get_str(region_name), + &__entry->region_uuid ) ); @@ -413,9 +417,10 @@ TRACE_EVENT(cxl_general_media, TRACE_EVENT(cxl_dram, TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, - struct cxl_region *cxlr, u64 hpa, struct cxl_event_dram *rec), + struct cxl_region *cxlr, u64 hpa, u64 hpa_alias, + struct cxl_event_dram *rec), - TP_ARGS(cxlmd, log, cxlr, hpa, rec), + TP_ARGS(cxlmd, log, cxlr, hpa, hpa_alias, rec), TP_STRUCT__entry( CXL_EVT_TP_entry @@ -431,6 +436,7 @@ TRACE_EVENT(cxl_dram, __field(u32, row) __array(u8, cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE) __field(u64, hpa) + __field(u64, hpa_alias) __field_struct(uuid_t, region_uuid) __field(u8, rank) /* Out of order to pack trace record */ __field(u8, bank_group) /* Out of order to pack trace record */ @@ -461,6 +467,7 @@ TRACE_EVENT(cxl_dram, memcpy(__entry->cor_mask, &rec->correction_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE); __entry->hpa = hpa; + __entry->hpa_alias = hpa_alias; if (cxlr) { __assign_str(region_name); uuid_copy(&__entry->region_uuid, &cxlr->params.uuid); @@ -474,7 +481,7 @@ TRACE_EVENT(cxl_dram, "transaction_type='%s' channel=%u rank=%u nibble_mask=%x " \ "bank_group=%u bank=%u row=%u column=%u cor_mask=%s " \ "validity_flags='%s' " \ - "hpa=%llx region=%s region_uuid=%pUb", + "hpa=%llx hpa_alias=%llx region=%s region_uuid=%pUb", __entry->dpa, show_dpa_flags(__entry->dpa_flags), show_event_desc_flags(__entry->descriptor), show_mem_event_type(__entry->type), @@ -484,7 +491,8 @@ TRACE_EVENT(cxl_dram, __entry->row, __entry->column, __print_hex(__entry->cor_mask, CXL_EVENT_DER_CORRECTION_MASK_SIZE), show_dram_valid_flags(__entry->validity_flags), - __entry->hpa, __get_str(region_name), &__entry->region_uuid + __entry->hpa_alias, __entry->hpa, __get_str(region_name), + &__entry->region_uuid ) ); From patchwork Fri Sep 27 14:16:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13814372 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F78E13635C; Fri, 27 Sep 2024 14:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446895; cv=none; b=TOVV/yk0bFeDsgFRn49SXPbgp+PRSsZZB1Bfe2xP1GGK9DazqL9ylVcyIN+B5j8skxcgczvH+n2iDRVAl+YhFXWU4h/t/29svRKVp03Xm4accDFs1Z7rDPMOynQZVxn+SX3OxXRvuNqcojkDjiLeTJzl+DJOpMLOotrLgj5eDw4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727446895; c=relaxed/simple; bh=Tj7g9Qz2+m9XOubxNkSKkbchbcNiJ9Ze8iorf5CIJ1k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rPC0M/TwX27hIoEwOkPQB67dQYAqm+8zHzTHCpJ6hCsFv3C8W7adh+OrZ4NHrTm+2zWJ+VJ23nScmizAD8oovvCAiWeicCt/Xc3/oggJ+FZtRiuWXVldXsRpz0qROSCCiEcX4+WSUV8GjRrPu8AsPrWVEq1CiQNgGe9t/8j7za4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6682C4CEC4; Fri, 27 Sep 2024 14:21:33 +0000 (UTC) From: Dave Jiang To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org Cc: rafael@kernel.org, bp@alien8.de, dan.j.williams@intel.com, tony.luck@intel.com, dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, ira.weiny@intel.com Subject: [RFC PATCH 6/6] cxl: Add mce notifier to emit aliased address for extended linear cache Date: Fri, 27 Sep 2024 07:16:58 -0700 Message-ID: <20240927142108.1156362-7-dave.jiang@intel.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: <20240927142108.1156362-1-dave.jiang@intel.com> References: <20240927142108.1156362-1-dave.jiang@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Below is a setup with extended linear cache configuration with an example layout of of memory region shown below presented as a single memory region consists of 256G memory where there's 128G of DRAM and 128G of CXL memory. The kernel sees a region of total 256G of system memory. 128G DRAM 128G CXL memory |-----------------------------------|-------------------------------------| Data resides in either DRAM or far memory (FM) with no replication. Hot data is swapped into DRAM by the hardware behind the scenes. When error is detected in one location, it is possible that error also resides in the aliased location. Therefore when a memory location that is flagged by MCE is part of the special region, the aliased memory location needs to be offlined as well. Add an mce notify callback to identify if the MCE address location is part of an extended linear cache region and handle accordingly. Added symbol export to set_mce_nospec() in x86 code in order to call set_mce_nospec() from the CXL MCE notify callback. Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/ Signed-off-by: Dave Jiang --- arch/x86/include/asm/mce.h | 1 + arch/x86/mm/pat/set_memory.c | 1 + drivers/cxl/core/mbox.c | 45 ++++++++++++++++++++++++++++++++++++ drivers/cxl/core/region.c | 25 ++++++++++++++++++++ drivers/cxl/cxl.h | 6 +++++ drivers/cxl/cxlmem.h | 2 ++ 6 files changed, 80 insertions(+) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 3ad29b128943..5da45e870858 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -182,6 +182,7 @@ enum mce_notifier_prios { MCE_PRIO_NFIT, MCE_PRIO_EXTLOG, MCE_PRIO_UC, + MCE_PRIO_CXL, MCE_PRIO_EARLY, MCE_PRIO_CEC, MCE_PRIO_HIGHEST = MCE_PRIO_CEC diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 44f7b2ea6a07..1f85c29e118e 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -2083,6 +2083,7 @@ int set_mce_nospec(unsigned long pfn) pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn); return rc; } +EXPORT_SYMBOL_GPL(set_mce_nospec); /* Restore full speculative operation to the pfn. */ int clear_mce_nospec(unsigned long pfn) diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index ac170fd85a1a..4488f30abc64 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -4,6 +4,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -1444,6 +1447,44 @@ int cxl_poison_state_init(struct cxl_memdev_state *mds) } EXPORT_SYMBOL_NS_GPL(cxl_poison_state_init, CXL); +static int cxl_handle_mce(struct notifier_block *nb, unsigned long val, + void *data) +{ + struct cxl_memdev_state *mds = container_of(nb, struct cxl_memdev_state, + mce_notifier); + struct cxl_memdev *cxlmd = mds->cxlds.cxlmd; + struct cxl_port *endpoint = cxlmd->endpoint; + struct mce *mce = (struct mce *)data; + u64 spa, spa_alias; + unsigned long pfn; + + if (!mce || !mce_usable_address(mce)) + return NOTIFY_DONE; + + spa = mce->addr & MCI_ADDR_PHYSADDR; + + pfn = spa >> PAGE_SHIFT; + if (!pfn_valid(pfn)) + return NOTIFY_DONE; + + spa_alias = cxl_port_get_spa_cache_alias(endpoint, spa); + if (!spa_alias) + return NOTIFY_DONE; + + pfn = spa_alias >> PAGE_SHIFT; + + /* + * Take down the aliased memory page. The original memory page flagged + * by the MCE will be taken cared of by the standard MCE handler. + */ + dev_emerg(mds->cxlds.dev, "Offlining aliased SPA address: %#llx\n", + spa_alias); + if (!memory_failure(pfn, 0)) + set_mce_nospec(pfn); + + return NOTIFY_OK; +} + struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev) { struct cxl_memdev_state *mds; @@ -1463,6 +1504,10 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev) mds->ram_perf.qos_class = CXL_QOS_CLASS_INVALID; mds->pmem_perf.qos_class = CXL_QOS_CLASS_INVALID; + mds->mce_notifier.notifier_call = cxl_handle_mce; + mds->mce_notifier.priority = MCE_PRIO_CXL; + mce_register_decode_chain(&mds->mce_notifier); + return mds; } EXPORT_SYMBOL_NS_GPL(cxl_memdev_state_create, CXL); diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index c19bbbf8079d..a60af9763a95 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3420,6 +3420,31 @@ int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled) } EXPORT_SYMBOL_NS_GPL(cxl_add_to_region, CXL); +u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa) +{ + struct cxl_region_ref *iter; + unsigned long index; + + guard(rwsem_write)(&cxl_region_rwsem); + + xa_for_each(&endpoint->regions, index, iter) { + struct cxl_region_params *p = &iter->region->params; + + if (p->res->start <= spa && spa <= p->res->end) { + if (!p->cache_size) + return 0; + + if (spa > p->res->start + p->cache_size) + return spa - p->cache_size; + + return spa + p->cache_size; + } + } + + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_port_get_spa_cache_alias, CXL); + static int is_system_ram(struct resource *res, void *arg) { struct cxl_region *cxlr = arg; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index d8d715090779..8516f6da620c 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -864,6 +864,7 @@ struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled); struct cxl_dax_region *to_cxl_dax_region(struct device *dev); +u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, u64 spa); #else static inline bool is_cxl_pmem_region(struct device *dev) { @@ -882,6 +883,11 @@ static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev) { return NULL; } +static inline u64 cxl_port_get_spa_cache_alias(struct cxl_port *endpoint, + u64 spa) +{ + return 0; +} #endif void cxl_endpoint_parse_cdat(struct cxl_port *port); diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index afb53d058d62..46515d2a49cb 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -470,6 +470,7 @@ struct cxl_dev_state { * @poison: poison driver state info * @security: security driver state info * @fw: firmware upload / activation state + * @mce_notifier: MCE notifier * @mbox_wait: RCU wait for mbox send completely * @mbox_send: @dev specific transport for transmitting mailbox commands * @@ -500,6 +501,7 @@ struct cxl_memdev_state { struct cxl_poison_state poison; struct cxl_security_state security; struct cxl_fw_state fw; + struct notifier_block mce_notifier; struct rcuwait mbox_wait; int (*mbox_send)(struct cxl_memdev_state *mds,