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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f57debe5csm94870215e9.24.2024.09.30.00.35.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 01/13] qemu/bswap: Introduce ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:38 +0200 Message-ID: <20240930073450.33195-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=philmd@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce the ld/st_endian_p() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_p() methods. Signed-off-by: Philippe Mathieu-Daudé --- TODO: Update docstring regexp --- include/qemu/bswap.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index ad22910a5d..ec813a756d 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -433,4 +433,23 @@ DO_STN_LDN_P(be) #undef le_bswaps #undef be_bswaps +#define lduw_endian_p(big_endian, p) \ + (big_endian) ? lduw_be_p(p) : lduw_le_p(p) +#define ldsw_endian_p(big_endian, p) \ + (big_endian) ? ldsw_be_p(p) : ldsw_be_p(p) +#define ldl_endian_p(big_endian, p) \ + (big_endian) ? ldl_be_p(p) : ldl_le_p(p) +#define ldq_endian_p(big_endian, p) \ + (big_endian) ? ldq_be_p(p) : ldq_le_p(p) +#define stw_endian_p(big_endian, p, v) \ + (big_endian) ? stw_be_p(p, v) : stw_le_p(p, v) +#define stl_endian_p(big_endian, p, v) \ + (big_endian) ? stl_be_p(p, v) : stl_le_p(p, v) +#define stq_endian_p(big_endian, p, v) \ + (big_endian) ? stq_be_p(p, v) : stq_le_p(p, v) +#define ldn_endian_p(big_endian, p, sz) \ + (big_endian) ? ldn_be_p(p, sz) : ldn_le_p(p, sz) +#define stn_endian_p(big_endian, p, sz, v) \ + (big_endian) ? stn_be_p(p, sz, v) : stn_le_p(p, sz, v) + #endif /* BSWAP_H */ From patchwork Mon Sep 30 07:34:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9AFDBCF6497 for ; Mon, 30 Sep 2024 08:02:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svBMp-0003f4-5v; Mon, 30 Sep 2024 04:02:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svBMe-00035X-T6 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:02:42 -0400 Received: from mail-lj1-x232.google.com ([2a00:1450:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svBMd-0003rQ-49 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:02:40 -0400 Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2f75c56f16aso48037901fa.0 for ; Mon, 30 Sep 2024 01:02:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727683356; x=1728288156; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yXipE1vCqUL/2GGIC/pfDOg0/7HE+1Efkqb3qV24aq0=; b=tx5YoGJWFUckrveB3VdNhtiMFf8LVpRUmQRun9jJ/lC67d8QYi4SMyMMbXBnljtpoj wkyN5usEcONB4tKJsCPpFy1CdBoBoONoZ0aZEmdrxNKBGskQWB0TtVJ3DKAXESyUpQMP h9s4KMYR5TtNb0MsYMpCKxhJwZ26hMokWHvFSeU31dYxC8REpQOr39Siiy+/DS1tzmwi Dr6+2Z7eDCJZSxl/wDviY5tM3bRno+IGXisK1nQLxJyvUlO7qvwxqHXV08VaCWdkED2b 4oNM+xmKYbPs9SnVIZtw2L1VinsJdC23dVvjA+mym0hShxbnDk2ywXG2diGM49+OVN2m iLEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727683356; x=1728288156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yXipE1vCqUL/2GGIC/pfDOg0/7HE+1Efkqb3qV24aq0=; b=bqbv1owSjADILEY7McaMNYqeVYV0Qm6hf6IQuiJTh9dwiXzbZ6hBARlsKLg6MQT+FG b4lCpbqkp8udT2JOKnMeCNDBvRwRWbU2+zHOs9ujTvlB2vny1T8xrQDqy0GTR5rfoRcm AnErrliHxR8QziJ5ygxt6OMiuJxy2H+IhtuCbrm9UoEvdNcwjZ+j7rYVjgCAn+udrtr8 R2BXhGZOoqqn1gvq0Yt5FUEdkYENkVwqRcNswLZtK+sHy1loE4kuYNLLulgDu5v9IxMI bNl/bofMIirqqAaChi+jcpz6Pg0BfS6d0LefGJSLsNfCMI/AeQchqWa6Qucg+QfPDPL8 xeKw== X-Gm-Message-State: AOJu0YxWdxrHdF4xDnoXYgesAUTitpLqeqHPp0/a2sVO4J8m6HWR777D 1NOoBRBlARvm6lK4I2DuEn+RaMX9yJYKhcp8Gyb4LnQg28oEgQZjsu4pVKS9Axqsjd5AbaU2zTB ngyo= X-Google-Smtp-Source: AGHT+IE8wS4WpCF0/bxJggWg+4eccixi5G2yV44Nj13zqRqQ7E/h8vxjwxEQnrMTjigRWr4M/8ssTA== X-Received: by 2002:a05:600c:4f86:b0:42c:bae0:f066 with SMTP id 5b1f17b1804b1-42f58434768mr72915825e9.13.1727681712926; Mon, 30 Sep 2024 00:35:12 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 02/13] hw/virtio/virtio-access: Use the ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:39 +0200 Message-ID: <20240930073450.33195-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=philmd@linaro.org; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Refactor to use the recently introduced ld/st_endian_p() API No logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/virtio/virtio-access.h | 36 ++++++------------------------- 1 file changed, 6 insertions(+), 30 deletions(-) diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-access.h index 07aae69042..b920874be8 100644 --- a/include/hw/virtio/virtio-access.h +++ b/include/hw/virtio/virtio-access.h @@ -95,56 +95,32 @@ static inline void virtio_stl_phys(VirtIODevice *vdev, hwaddr pa, static inline void virtio_stw_p(VirtIODevice *vdev, void *ptr, uint16_t v) { - if (virtio_access_is_big_endian(vdev)) { - stw_be_p(ptr, v); - } else { - stw_le_p(ptr, v); - } + stw_endian_p(virtio_access_is_big_endian(vdev), ptr, v); } static inline void virtio_stl_p(VirtIODevice *vdev, void *ptr, uint32_t v) { - if (virtio_access_is_big_endian(vdev)) { - stl_be_p(ptr, v); - } else { - stl_le_p(ptr, v); - } + stl_endian_p(virtio_access_is_big_endian(vdev), ptr, v); } static inline void virtio_stq_p(VirtIODevice *vdev, void *ptr, uint64_t v) { - if (virtio_access_is_big_endian(vdev)) { - stq_be_p(ptr, v); - } else { - stq_le_p(ptr, v); - } + stq_endian_p(virtio_access_is_big_endian(vdev), ptr, v); } static inline int virtio_lduw_p(VirtIODevice *vdev, const void *ptr) { - if (virtio_access_is_big_endian(vdev)) { - return lduw_be_p(ptr); - } else { - return lduw_le_p(ptr); - } + return lduw_endian_p(virtio_access_is_big_endian(vdev), ptr); } static inline int virtio_ldl_p(VirtIODevice *vdev, const void *ptr) { - if (virtio_access_is_big_endian(vdev)) { - return ldl_be_p(ptr); - } else { - return ldl_le_p(ptr); - } + return ldl_endian_p(virtio_access_is_big_endian(vdev), ptr); } static inline uint64_t virtio_ldq_p(VirtIODevice *vdev, const void *ptr) { - if (virtio_access_is_big_endian(vdev)) { - return ldq_be_p(ptr); - } else { - return ldq_le_p(ptr); - } + return ldq_endian_p(virtio_access_is_big_endian(vdev), ptr); } static inline uint16_t virtio_tswap16(VirtIODevice *vdev, uint16_t s) From patchwork Mon Sep 30 07:34:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD126CF649D for ; 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd5742a23sm8324073f8f.105.2024.09.30.00.35.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 03/13] target/arm/ptw: Use the ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:40 +0200 Message-ID: <20240930073450.33195-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Refactor to use the recently introduced ld/st_endian_p() API No logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/ptw.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index defd6b84de..a1a6b1fec3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -699,11 +699,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, data = le64_to_cpu(data); } #else - if (ptw->out_be) { - data = ldq_be_p(host); - } else { - data = ldq_le_p(host); - } + data = ldq_endian_p(ptw->out_be, host); #endif } else { /* Page tables are in MMIO. */ @@ -860,16 +856,9 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, if (!locked) { bql_lock(); } - if (ptw->out_be) { - cur_val = ldq_be_p(host); - if (cur_val == old_val) { - stq_be_p(host, new_val); - } - } else { - cur_val = ldq_le_p(host); - if (cur_val == old_val) { - stq_le_p(host, new_val); - } + cur_val = ldq_endian_p(ptw->out_be, host); + if (cur_val == old_val) { + stq_endian_p(ptw->out_be, host, new_val); } if (!locked) { bql_unlock(); From patchwork Mon Sep 30 07:34:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D5A3CF6491 for ; Mon, 30 Sep 2024 07:59:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svAzG-00049A-1M; Mon, 30 Sep 2024 03:38:32 -0400 Received: from [2001:470:142:3::10] (helo=eggs.gnu.org) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svAz3-00040e-Rn for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:23 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svAxu-0008Kw-3b for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:37:56 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3770320574aso2669508f8f.2 for ; Mon, 30 Sep 2024 00:35:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727681730; x=1728286530; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xlB7TER95AHLu1cUEZk4SLXmuphORdTbB9q557qt3nU=; b=PWmyRjTl1in3uOo5+rUIdtFWCnFTaeK84ZLkDvCJLcC/hrk2jgdVNpIO9ixzXqXYlt XDs+xgzkHLRVj7fsKhKpT8ndb7j0959UwqZXM9d5yiKXjC9FCGk2PXyfuj6T3RN7QCDh 6T8piSXNrd9povM/OdrrwvdCzgKxasaz2HQoNsLvz8V+6wVRohp0G5ByZQPi3wJpoYpy 2BV/lCVpqTcOWqamdWACiXEZb1/zPi+10Ta/9n3klNyVEv8aaXAlve8DZaiY2yDsAfaU 9wJM1t0qdm6T3InrdOZaHGmExqfoyNVeSMhZ958W17GIG8OKIAIkWB/pNoISIybrXUaA xHTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727681730; x=1728286530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xlB7TER95AHLu1cUEZk4SLXmuphORdTbB9q557qt3nU=; b=BZ+DOsepytB8nWdr5aVev+X5ZmempUKYutCiaB+0bLQh2ZikVnBzmXscaWMvZ/AlJ7 tgr2HW3rBnNKizl5RwNg+4zQcY5PeuM/iTJlKWXzKFFoyC8vdGaPdfUFBILVD6uePRlx 9NnEhPyjPUtIynVw0ea2IEh2mR0KflOj+cpoL3HBQVqwFjiJ0zjE122PgEpAfg45ToK/ dBEyVvlmw49Z5WFLBClOAOXNEs7SI1GwIMN0MVIbMs1N4eLa2ionhWjjteeemkoq8EuK sZul6GlgC4AhnUVHaEwNnvz4kr+I4LSq009Vr6bDI9o1aoBaszI238/K7D3dPtup0t2l RYPA== X-Gm-Message-State: AOJu0Yx7DuRuq3GRQVmIoJ375KF/GWxQntoHQ2fM+cTqilJTjrHi0O0O yAPQbpthLd3QwhJf17nsoiEz7bg3ecIah53pKWT+6reQFfQ8sbkZD34zQ/i+c/WbYsf+thTMUa4 RRbI= X-Google-Smtp-Source: AGHT+IEZ8g5gwHNeatvdEZTutoqFSh6yvDtTZN8q8xHzxZX5itZN8D5DVFr7TZeVgEpeEEf+jqHVXQ== X-Received: by 2002:adf:fc4d:0:b0:37c:ca11:c08d with SMTP id ffacd0b85a97d-37cd5a833c7mr6070303f8f.24.1727681729610; Mon, 30 Sep 2024 00:35:29 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. [88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd575dfd2sm8301463f8f.117.2024.09.30.00.35.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 04/13] hw/mips: Pass BlCpuCfg argument to bootloader API Date: Mon, 30 Sep 2024 09:34:41 +0200 Message-ID: <20240930073450.33195-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In preparation to pass endianness and target word size to the bootloader API, introduce an empty BlCpuCfg structure and propagate it to the MIPS bootloader methods. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 17 +++-- hw/mips/bootloader.c | 142 +++++++++++++++++++---------------- hw/mips/boston.c | 9 ++- hw/mips/fuloong2e.c | 3 +- hw/mips/malta.c | 21 +++--- 5 files changed, 109 insertions(+), 83 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index c32f6c2835..744eb11d0e 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -10,17 +10,24 @@ #define HW_MIPS_BOOTLOADER_H #include "exec/cpu-defs.h" +#include "exec/target_long.h" -void bl_gen_jump_to(void **ptr, target_ulong jump_addr); -void bl_gen_jump_kernel(void **ptr, +typedef struct bl_cpu_cfg { +} BlCpuCfg; + +void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr); +void bl_gen_jump_kernel(const BlCpuCfg *cfg, void **ptr, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, bool set_a2, target_ulong a2, bool set_a3, target_ulong a3, target_ulong kernel_addr); -void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val); -void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val); -void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val); +void bl_gen_write_ulong(const BlCpuCfg *cfg, void **ptr, + target_ulong addr, target_ulong val); +void bl_gen_write_u32(const BlCpuCfg *cfg, void **ptr, + target_ulong addr, uint32_t val); +void bl_gen_write_u64(const BlCpuCfg *cfg, void **ptr, + target_ulong addr, uint64_t val); #endif diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 1dd6ef2096..ee1a1c4f20 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -54,7 +54,7 @@ static bool bootcpu_supports_isa(uint64_t isa_mask) return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); } -static void st_nm32_p(void **ptr, uint32_t insn) +static void st_nm32_p(const BlCpuCfg *cfg, void **ptr, uint32_t insn) { uint16_t *p = *ptr; @@ -67,10 +67,10 @@ static void st_nm32_p(void **ptr, uint32_t insn) } /* Base types */ -static void bl_gen_nop(void **ptr) +static void bl_gen_nop(const BlCpuCfg *cfg, void **ptr) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { - st_nm32_p(ptr, 0x8000c000); + st_nm32_p(cfg, ptr, 0x8000c000); } else { uint32_t *p = *ptr; @@ -80,7 +80,8 @@ static void bl_gen_nop(void **ptr) } } -static void bl_gen_r_type(void **ptr, uint8_t opcode, +static void bl_gen_r_type(const BlCpuCfg *cfg, + void **ptr, uint8_t opcode, bl_reg rs, bl_reg rt, bl_reg rd, uint8_t shift, uint8_t funct) { @@ -100,7 +101,8 @@ static void bl_gen_r_type(void **ptr, uint8_t opcode, *ptr = p; } -static void bl_gen_i_type(void **ptr, uint8_t opcode, +static void bl_gen_i_type(const BlCpuCfg *cfg, + void **ptr, uint8_t opcode, bl_reg rs, bl_reg rt, uint16_t imm) { uint32_t *p = *ptr; @@ -118,16 +120,17 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode, } /* Single instructions */ -static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa) +static void bl_gen_dsll(const BlCpuCfg *cfg, void **p, + bl_reg rd, bl_reg rt, uint8_t sa) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); + bl_gen_r_type(cfg, p, 0, 0, rt, rd, sa, 0x38); } else { g_assert_not_reached(); /* unsupported */ } } -static void bl_gen_jalr(void **p, bl_reg rs) +static void bl_gen_jalr(const BlCpuCfg *cfg, void **p, bl_reg rs) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { uint32_t insn = 0; @@ -136,13 +139,14 @@ static void bl_gen_jalr(void **p, bl_reg rs) insn = deposit32(insn, 21, 5, BL_REG_RA); insn = deposit32(insn, 16, 5, rs); - st_nm32_p(p, insn); + st_nm32_p(cfg, p, insn); } else { - bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09); + bl_gen_r_type(cfg, p, 0, rs, 0, BL_REG_RA, 0, 0x09); } } -static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20) +static void bl_gen_lui_nm(const BlCpuCfg *cfg, void **ptr, + bl_reg rt, uint32_t imm20) { uint32_t insn = 0; @@ -153,16 +157,18 @@ static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20) insn = deposit32(insn, 2, 10, extract32(imm20, 9, 10)); insn = deposit32(insn, 0, 1, sextract32(imm20, 19, 1)); - st_nm32_p(ptr, insn); + st_nm32_p(cfg, ptr, insn); } -static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm) +static void bl_gen_lui(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint16_t imm) { /* R6: It's a alias of AUI with RS = 0 */ - bl_gen_i_type(p, 0x0f, 0, rt, imm); + bl_gen_i_type(cfg, p, 0x0f, 0, rt, imm); } -static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12) +static void bl_gen_ori_nm(const BlCpuCfg *cfg, void **ptr, + bl_reg rt, bl_reg rs, uint16_t imm12) { uint32_t insn = 0; @@ -172,15 +178,17 @@ static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12) insn = deposit32(insn, 16, 5, rs); insn = deposit32(insn, 0, 12, imm12); - st_nm32_p(ptr, insn); + st_nm32_p(cfg, ptr, insn); } -static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm) +static void bl_gen_ori(const BlCpuCfg *cfg, void **p, + bl_reg rt, bl_reg rs, uint16_t imm) { - bl_gen_i_type(p, 0x0d, rs, rt, imm); + bl_gen_i_type(cfg, p, 0x0d, rs, rt, imm); } -static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) +static void bl_gen_sw_nm(const BlCpuCfg *cfg, void **ptr, + bl_reg rt, uint8_t rs, uint16_t ofs12) { uint32_t insn = 0; @@ -191,66 +199,71 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12) insn = deposit32(insn, 12, 4, 0b1001); insn = deposit32(insn, 0, 12, ofs12); - st_nm32_p(ptr, insn); + st_nm32_p(cfg, ptr, insn); } -static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sw(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { - bl_gen_sw_nm(p, rt, base, offset); + bl_gen_sw_nm(cfg, p, rt, base, offset); } else { - bl_gen_i_type(p, 0x2b, base, rt, offset); + bl_gen_i_type(cfg, p, 0x2b, base, rt, offset); } } -static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset) +static void bl_gen_sd(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint8_t base, uint16_t offset) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_i_type(p, 0x3f, base, rt, offset); + bl_gen_i_type(cfg, p, 0x3f, base, rt, offset); } else { g_assert_not_reached(); /* unsupported */ } } /* Pseudo instructions */ -static void bl_gen_li(void **p, bl_reg rt, uint32_t imm) +static void bl_gen_li(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint32_t imm) { if (bootcpu_supports_isa(ISA_NANOMIPS32)) { - bl_gen_lui_nm(p, rt, extract32(imm, 12, 20)); - bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12)); + bl_gen_lui_nm(cfg, p, rt, extract32(imm, 12, 20)); + bl_gen_ori_nm(cfg, p, rt, rt, extract32(imm, 0, 12)); } else { - bl_gen_lui(p, rt, extract32(imm, 16, 16)); - bl_gen_ori(p, rt, rt, extract32(imm, 0, 16)); + bl_gen_lui(cfg, p, rt, extract32(imm, 16, 16)); + bl_gen_ori(cfg, p, rt, rt, extract32(imm, 0, 16)); } } -static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm) +static void bl_gen_dli(const BlCpuCfg *cfg, void **p, + bl_reg rt, uint64_t imm) { - bl_gen_li(p, rt, extract64(imm, 32, 32)); - bl_gen_dsll(p, rt, rt, 16); - bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); - bl_gen_dsll(p, rt, rt, 16); - bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); + bl_gen_li(cfg, p, rt, extract64(imm, 32, 32)); + bl_gen_dsll(cfg, p, rt, rt, 16); + bl_gen_ori(cfg, p, rt, rt, extract64(imm, 16, 16)); + bl_gen_dsll(cfg, p, rt, rt, 16); + bl_gen_ori(cfg, p, rt, rt, extract64(imm, 0, 16)); } -static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm) +static void bl_gen_load_ulong(const BlCpuCfg *cfg, void **p, + bl_reg rt, target_ulong imm) { if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_dli(p, rt, imm); /* 64bit */ + bl_gen_dli(cfg, p, rt, imm); /* 64bit */ } else { - bl_gen_li(p, rt, imm); /* 32bit */ + bl_gen_li(cfg, p, rt, imm); /* 32bit */ } } /* Helpers */ -void bl_gen_jump_to(void **p, target_ulong jump_addr) +void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr) { - bl_gen_load_ulong(p, BL_REG_T9, jump_addr); - bl_gen_jalr(p, BL_REG_T9); - bl_gen_nop(p); /* delay slot */ + bl_gen_load_ulong(cfg, p, BL_REG_T9, jump_addr); + bl_gen_jalr(cfg, p, BL_REG_T9); + bl_gen_nop(cfg, p); /* delay slot */ } -void bl_gen_jump_kernel(void **p, +void bl_gen_jump_kernel(const BlCpuCfg *cfg, void **p, bool set_sp, target_ulong sp, bool set_a0, target_ulong a0, bool set_a1, target_ulong a1, @@ -259,45 +272,48 @@ void bl_gen_jump_kernel(void **p, target_ulong kernel_addr) { if (set_sp) { - bl_gen_load_ulong(p, BL_REG_SP, sp); + bl_gen_load_ulong(cfg, p, BL_REG_SP, sp); } if (set_a0) { - bl_gen_load_ulong(p, BL_REG_A0, a0); + bl_gen_load_ulong(cfg, p, BL_REG_A0, a0); } if (set_a1) { - bl_gen_load_ulong(p, BL_REG_A1, a1); + bl_gen_load_ulong(cfg, p, BL_REG_A1, a1); } if (set_a2) { - bl_gen_load_ulong(p, BL_REG_A2, a2); + bl_gen_load_ulong(cfg, p, BL_REG_A2, a2); } if (set_a3) { - bl_gen_load_ulong(p, BL_REG_A3, a3); + bl_gen_load_ulong(cfg, p, BL_REG_A3, a3); } - bl_gen_jump_to(p, kernel_addr); + bl_gen_jump_to(cfg, p, kernel_addr); } -void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val) +void bl_gen_write_ulong(const BlCpuCfg *cfg, void **p, + target_ulong addr, target_ulong val) { - bl_gen_load_ulong(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_load_ulong(cfg, p, BL_REG_K0, val); + bl_gen_load_ulong(cfg, p, BL_REG_K1, addr); if (bootcpu_supports_isa(ISA_MIPS3)) { - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sd(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } else { - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_sw(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } } -void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val) +void bl_gen_write_u32(const BlCpuCfg *cfg, void **p, + target_ulong addr, uint32_t val) { - bl_gen_li(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); - bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_li(cfg, p, BL_REG_K0, val); + bl_gen_load_ulong(cfg, p, BL_REG_K1, addr); + bl_gen_sw(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } -void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val) +void bl_gen_write_u64(const BlCpuCfg *cfg, void **p, + target_ulong addr, uint64_t val) { - bl_gen_dli(p, BL_REG_K0, val); - bl_gen_load_ulong(p, BL_REG_K1, addr); - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + bl_gen_dli(cfg, p, BL_REG_K0, val); + bl_gen_load_ulong(cfg, p, BL_REG_K1, addr); + bl_gen_sd(cfg, p, BL_REG_K0, BL_REG_K1, 0x0); } diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 1b44fb354c..8e210876e1 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -325,23 +325,24 @@ type_init(boston_register_types) static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) { + const BlCpuCfg bl_cfg = { }; uint64_t regaddr; /* Move CM GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, + bl_gen_write_ulong(&bl_cfg, &p, regaddr, boston_memmap[BOSTON_CM].base); /* Move & enable GIC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_GIC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, + bl_gen_write_ulong(&bl_cfg, &p, regaddr, boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK); /* Move & enable CPC GCRs */ regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base + GCR_CPC_BASE_OFS), - bl_gen_write_ulong(&p, regaddr, + bl_gen_write_ulong(&bl_cfg, &p, regaddr, boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK); /* @@ -352,7 +353,7 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) * a2/$6 = 0 * a3/$7 = 0 */ - bl_gen_jump_kernel(&p, + bl_gen_jump_kernel(&bl_cfg, &p, true, 0, true, (int32_t)-2, true, fdt_addr, true, 0, true, 0, kernel_entry); diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 6e4303ba47..a989637d3b 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -165,6 +165,7 @@ static uint64_t load_kernel(MIPSCPU *cpu) static void write_bootloader(CPUMIPSState *env, uint8_t *base, uint64_t kernel_addr) { + const BlCpuCfg bl_cfg = { }; uint32_t *p; /* Small bootloader */ @@ -178,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base, /* Second part of the bootloader */ p = (uint32_t *)(base + 0x040); - bl_gen_jump_kernel((void **)&p, + bl_gen_jump_kernel(&bl_cfg, (void **)&p, true, ENVP_VADDR - 64, true, 2, true, ENVP_VADDR, true, ENVP_VADDR + 8, diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 664a2ae0a9..fc485cc884 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -624,6 +624,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, static const char pci_pins_cfg[PCI_NUM_PINS] = { 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; + const BlCpuCfg bl_cfg = { }; /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN @@ -635,29 +636,29 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, /* setup MEM-to-PCI0 mapping as done by YAMON */ /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - bl_gen_write_u32(p, /* GT_ISD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_ISD */ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68), cpu_to_gt32(0x1be00000 << 3)); /* setup PCI0 io window to 0x18000000-0x181fffff */ - bl_gen_write_u32(p, /* GT_PCI0IOLD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0IOLD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), cpu_to_gt32(0x18000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0IOHD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0IOHD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), cpu_to_gt32(0x08000000 << 3)); /* setup PCI0 mem windows */ - bl_gen_write_u32(p, /* GT_PCI0M0LD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M0LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58), cpu_to_gt32(0x10000000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M0HD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M0HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60), cpu_to_gt32(0x07e00000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1LD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M1LD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80), cpu_to_gt32(0x18200000 << 3)); - bl_gen_write_u32(p, /* GT_PCI0M1HD */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0M1HD */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88), cpu_to_gt32(0x0bc00000 << 3)); @@ -668,16 +669,16 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, * Load the PIIX IRQC[A:D] routing config address, then * write routing configuration to the config data register. */ - bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0_CFGADDR */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), tswap32((1 << 31) /* ConfigEn */ | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 | PIIX_PIRQCA)); - bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ + bl_gen_write_u32(&bl_cfg, p, /* GT_PCI0_CFGDATA */ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), tswap32(ldl_be_p(pci_pins_cfg))); - bl_gen_jump_kernel(p, + bl_gen_jump_kernel(&bl_cfg, p, true, ENVP_VADDR - 64, /* * If semihosting is used, arguments have already From patchwork Mon Sep 30 07:34:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20F86CF6491 for ; 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd564d331sm8359558f8f.10.2024.09.30.00.35.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 05/13] hw/mips: Add cpu_is_bigendian field to BlCpuCfg structure Date: Mon, 30 Sep 2024 09:34:42 +0200 Message-ID: <20240930073450.33195-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the BlCpuCfg::cpu_is_bigendian field, initialize it in machine code. Bootloader API use the ld/st_endian_p() to dispatch to target endianness. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/mips/bootloader.h | 1 + hw/mips/bootloader.c | 10 +++++----- hw/mips/boston.c | 2 +- hw/mips/fuloong2e.c | 2 +- hw/mips/malta.c | 2 +- 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h index 744eb11d0e..ef778a38d0 100644 --- a/include/hw/mips/bootloader.h +++ b/include/hw/mips/bootloader.h @@ -13,6 +13,7 @@ #include "exec/target_long.h" typedef struct bl_cpu_cfg { + bool cpu_is_bigendian; } BlCpuCfg; void bl_gen_jump_to(const BlCpuCfg *cfg, void **p, target_ulong jump_addr); diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index ee1a1c4f20..258cc5d8c8 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -58,9 +58,9 @@ static void st_nm32_p(const BlCpuCfg *cfg, void **ptr, uint32_t insn) { uint16_t *p = *ptr; - stw_p(p, insn >> 16); + stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 16); p++; - stw_p(p, insn >> 0); + stw_endian_p(cfg->cpu_is_bigendian, p, insn >> 0); p++; *ptr = p; @@ -74,7 +74,7 @@ static void bl_gen_nop(const BlCpuCfg *cfg, void **ptr) } else { uint32_t *p = *ptr; - stl_p(p, 0); + stl_endian_p(cfg->cpu_is_bigendian, p, 0); p++; *ptr = p; } @@ -95,7 +95,7 @@ static void bl_gen_r_type(const BlCpuCfg *cfg, insn = deposit32(insn, 6, 5, shift); insn = deposit32(insn, 0, 6, funct); - stl_p(p, insn); + stl_endian_p(cfg->cpu_is_bigendian, p, insn); p++; *ptr = p; @@ -113,7 +113,7 @@ static void bl_gen_i_type(const BlCpuCfg *cfg, insn = deposit32(insn, 16, 5, rt); insn = deposit32(insn, 0, 16, imm); - stl_p(p, insn); + stl_endian_p(cfg->cpu_is_bigendian, p, insn); p++; *ptr = p; diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 8e210876e1..d4dd242d0d 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -325,7 +325,7 @@ type_init(boston_register_types) static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr) { - const BlCpuCfg bl_cfg = { }; + const BlCpuCfg bl_cfg = { .cpu_is_bigendian = TARGET_BIG_ENDIAN }; uint64_t regaddr; /* Move CM GCRs */ diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index a989637d3b..4fe5108845 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -165,7 +165,7 @@ static uint64_t load_kernel(MIPSCPU *cpu) static void write_bootloader(CPUMIPSState *env, uint8_t *base, uint64_t kernel_addr) { - const BlCpuCfg bl_cfg = { }; + const BlCpuCfg bl_cfg = { .cpu_is_bigendian = false }; uint32_t *p; /* Small bootloader */ diff --git a/hw/mips/malta.c b/hw/mips/malta.c index fc485cc884..6e73c896ff 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -624,7 +624,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, static const char pci_pins_cfg[PCI_NUM_PINS] = { 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; - const BlCpuCfg bl_cfg = { }; + const BlCpuCfg bl_cfg = { .cpu_is_bigendian = TARGET_BIG_ENDIAN }; /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN From patchwork Mon Sep 30 07:34:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6ADB8CF6491 for ; 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 06/13] tests/tcg/plugins: Use the ld/st_endian_p() API Date: Mon, 30 Sep 2024 09:34:43 +0200 Message-ID: <20240930073450.33195-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Refactor to use the recently introduced ld/st_endian_p() API No logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- tests/tcg/plugins/mem.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/tests/tcg/plugins/mem.c b/tests/tcg/plugins/mem.c index b0fa8a9f27..3586d05587 100644 --- a/tests/tcg/plugins/mem.c +++ b/tests/tcg/plugins/mem.c @@ -163,13 +163,9 @@ static void update_region_info(uint64_t region, uint64_t offset, { uint16_t *p = (uint16_t *) &ri->data[offset]; if (is_store) { - if (be) { - stw_be_p(p, value.data.u16); - } else { - stw_le_p(p, value.data.u16); - } + stw_endian_p(be, p, value.data.u16); } else { - uint16_t val = be ? lduw_be_p(p) : lduw_le_p(p); + uint16_t val = lduw_endian_p(be, p); unseen_data = val != value.data.u16; } break; @@ -178,13 +174,9 @@ static void update_region_info(uint64_t region, uint64_t offset, { uint32_t *p = (uint32_t *) &ri->data[offset]; if (is_store) { - if (be) { - stl_be_p(p, value.data.u32); - } else { - stl_le_p(p, value.data.u32); - } + stl_endian_p(be, p, value.data.u32); } else { - uint32_t val = be ? ldl_be_p(p) : ldl_le_p(p); + uint32_t val = ldl_endian_p(be, p); unseen_data = val != value.data.u32; } break; @@ -193,13 +185,9 @@ static void update_region_info(uint64_t region, uint64_t offset, { uint64_t *p = (uint64_t *) &ri->data[offset]; if (is_store) { - if (be) { - stq_be_p(p, value.data.u64); - } else { - stq_le_p(p, value.data.u64); - } + stq_endian_p(be, p, value.data.u64); } else { - uint64_t val = be ? ldq_be_p(p) : ldq_le_p(p); + uint64_t val = ldq_endian_p(be, p); unseen_data = val != value.data.u64; } break; From patchwork Mon Sep 30 07:34:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815496 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C79DCF6497 for ; Mon, 30 Sep 2024 07:48:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svAzc-0004Dy-OC; Mon, 30 Sep 2024 03:38:54 -0400 Received: from eggs.gnu.org ([209.51.188.92]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svAz9-00043M-Qr for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:25 -0400 Received: from [2a00:1450:4864:20::32e] (helo=mail-wm1-x32e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svAyA-00008z-99 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:10 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-42cb1758e41so29051145e9.1 for ; Mon, 30 Sep 2024 00:36:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727681754; x=1728286554; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PTheN6LnDYE/7gHrhVuAVd6VlwGt/9Pb92gg++hmAlc=; b=X3JHrWqG2618uAi578fJOJrrORQXtjJvRhi3DdxN4wFJe1K30fYU51IewhSI4B1Cu3 jVB3Uziw7UzvftRvQ1AmGKme8Gazdfb7cSGZmOcf96W3sVnJXO/QlwuIfrux5wCFglxD sHtJjXdh0V3z6R0tEntMC0zFsCrwVui3nB6PQJmfu9LMn5BmIO9JcSNlDStPJMJ5j3ch 56ejsiSze7Nb8lI8SE4aT8D5Ba34M88S5/Lch9HRgka8iBK+H4S8t1MbHEzvFb3YEwe6 KrAmGwLxY7p4qhotGpuaxpE/1x9WhiQNseU/wD0l5KhSi8YYYwA3TAJpiX4WX0BTuVZR 6AbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727681754; x=1728286554; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PTheN6LnDYE/7gHrhVuAVd6VlwGt/9Pb92gg++hmAlc=; b=Elmfka85yKZ43VbSFMqebBUnv3PbSG4VMrlKOvVGXqfaXYnKsDV338CIVdhJGFdoAq Q8C7rlcZrsrGBxTppspkJzrSny/rktOXczEwfwQXwfFyJwYSgy92j3fR4+8/ScXPGKNz kBmJwqc7apjZRCrpQ3KLhaxSgdxrN5vvqvj9DnC2Pf2VhRRIT6G8Mwz6mOtHCbyDRDrj 9LYPWdLw24r4HLFW4GTqzI8RIH70/NnJEVcINGp2tkvILAvxj22HzZ9AhHrF/Pbpe1Pp A8fk74s+gy7L3YlnlNydsgiXn9ZwJzwfxzFPKDB1rygyLTDztmK/PoQXhnmBwTRHgN5r znOg== X-Gm-Message-State: AOJu0YyC5TRz1/Q3amoBwzftY0pmPDsgzYHv97tHlhkTWMcthmgJFmQ3 OcfrA5bQHeV8pOyTk/5jCPal9HUQwn7ABvJVIq3KcRTRBGQUM3zHiBq3eQYFMl80jtp+AQiMnGO RstQ= X-Google-Smtp-Source: AGHT+IHEXr3aLIhI9JyM7H/sQJVL2/m/6ZOv4bKIitsJ0XgxUNKM1k7r/JUO4/aOFSZATCirYAHKaA== X-Received: by 2002:a05:600c:3c9e:b0:426:6edf:6597 with SMTP id 5b1f17b1804b1-42f58440cefmr66722995e9.19.1727681754341; Mon, 30 Sep 2024 00:35:54 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. [88.28.13.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e969ffce1sm142805165e9.28.2024.09.30.00.35.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:35:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 07/13] hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry Date: Mon, 30 Sep 2024 09:34:44 +0200 Message-ID: <20240930073450.33195-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (deferred) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RDNS_NONE=0.793, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move code evaluation from preprocessor to compiler so both if() ladders are processed. Mostly style change. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- hw/xtensa/xtfpga.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 955e8867a3..228f00b045 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -415,8 +415,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) } } if (entry_point != env->pc) { - uint8_t boot[] = { -#if TARGET_BIG_ENDIAN + uint8_t boot_be[] = { 0x60, 0x00, 0x08, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ @@ -425,7 +424,8 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 0x0a, 0x00, 0x00, /* jx a0 */ -#else + }; + uint8_t boot_le[] = { 0x06, 0x02, 0x00, /* j 1f */ 0x00, /* .literal_position */ 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ @@ -434,14 +434,16 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 0xa0, 0x00, 0x00, /* jx a0 */ -#endif }; + const size_t boot_sz = TARGET_BIG_ENDIAN ? sizeof(boot_be) + : sizeof(boot_le); + uint8_t *boot = TARGET_BIG_ENDIAN ? boot_be : boot_le; uint32_t entry_pc = tswap32(entry_point); uint32_t entry_a2 = tswap32(tagptr); memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); - cpu_physical_memory_write(env->pc, boot, sizeof(boot)); + cpu_physical_memory_write(env->pc, boot, boot_sz); } } else { if (flash) { From patchwork Mon Sep 30 07:34:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA94CCF6497 for ; Mon, 30 Sep 2024 08:45:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svAzl-0004Ra-Oe; Mon, 30 Sep 2024 03:39:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svAzG-0004Av-8J for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:32 -0400 Received: from [2a00:1450:4864:20::436] (helo=mail-wr1-x436.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svAyV-00009T-5d for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:38:19 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-37cdac05af9so2062353f8f.0 for ; Mon, 30 Sep 2024 00:36:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727681762; x=1728286562; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zn1QOBKpxwHC7pwp1nDkwIemv7qUJthxbF0WBocU5ZE=; b=vbqqrfJsm9kB5r/lSvVVwyyqRkJpsM4GtfPs4XpiHI1pmBjjZsQae8l8q8nLZSTPFE L0PwIn4O097hCvRm0KzpZY2ZGbTeCu2WmXBo6RzEvU9cX+z7Z3DKo7PqjKwtOtEJWfjo Iuhwg7X1NtJiTe+LPmMMeL82cUFZIvWmxcS4RBa58QVSixjlycgzRr5fo+rzo/5i00WE CWKJaShmXxDuP4AjFe/KEKE9XfjOVG8e9nxPhpgFfdXCYOti9PO18TuhRSPW+a2lrD0o MgVyyrUZvOnzUYPF4DKj2M8N54HHMqrT+K1lzKJcbzsKnENJJLP5d+n8iIWzDCQhih/E hbVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727681762; x=1728286562; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zn1QOBKpxwHC7pwp1nDkwIemv7qUJthxbF0WBocU5ZE=; b=CPKlBAIo+bzZsd+7EFaqqvBKAXhahijdThC6wMzDpjnsEx/KQHs4wstaQ18E7rTClv RhK/js2Xu/s/snQnuWLe6jzCrChWm1VHSTbz/35fyj8gZQabqyBIwZxbR91WiglBYJDQ 4GAg9iAIBkj3fwnXprAeDQwvl2giVZRuF8yVbhpIB0L28YnWVK0L9DkcwvxqJAOwIjH/ SioRpsNqRRru9j2dOKs56rI0xaEiW7jRdZVTzahqsowbTfZLVmgMuWSb338k556ea3EU xEbN5LnF6D0MNroSVsRCXZYk35QC13L6OrEuANDMRzDRMDHHeZH2+tplbGghYYee4RkB fQGQ== X-Gm-Message-State: AOJu0YyeOmM3n1JNdjWfNbDMWH1J9QjhIpyngfljJktaMEWGHHJ6LnAL Qaetq9xBxJZafen6iISs7bA827hlFtfyxMqgqTIzbTZQfcUfm80fOa0hNcDuOpA3FZPKdJzJPWi DnMY= X-Google-Smtp-Source: AGHT+IF/2ju8dp/hlgQNQQYphCSWWra4wcESmtISLsZng/9+YCPMt/FRqGKyK9eINYIKLWFa++fX7A== X-Received: by 2002:a5d:414c:0:b0:37c:cfbb:d357 with SMTP id ffacd0b85a97d-37cd5aa681cmr10399551f8f.30.1727681762102; Mon, 30 Sep 2024 00:36:02 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. [88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd565e881sm8323063f8f.44.2024.09.30.00.35.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 08/13] hw/xtensa/xtfpga: Replace memcpy()+tswap32() by stl_endian_p() Date: Mon, 30 Sep 2024 09:34:45 +0200 Message-ID: <20240930073450.33195-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::436 (deferred) Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RDNS_NONE=0.793, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace a pair of memcpy() + tswap32() by stl_endian_p(), which also swap the value using target endianness. Signed-off-by: Philippe Mathieu-Daudé --- hw/xtensa/xtfpga.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 228f00b045..521fe84b01 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -438,11 +438,9 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) const size_t boot_sz = TARGET_BIG_ENDIAN ? sizeof(boot_be) : sizeof(boot_le); uint8_t *boot = TARGET_BIG_ENDIAN ? boot_be : boot_le; - uint32_t entry_pc = tswap32(entry_point); - uint32_t entry_a2 = tswap32(tagptr); - memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); - memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); + stl_endian_p(TARGET_BIG_ENDIAN, boot + 4, entry_point); + stl_endian_p(TARGET_BIG_ENDIAN, boot + 8, tagptr); cpu_physical_memory_write(env->pc, boot, boot_sz); } } else { From patchwork Mon Sep 30 07:34:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A457CCF6497 for ; Mon, 30 Sep 2024 08:07:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svBQW-0000Yt-Gy; Mon, 30 Sep 2024 04:06:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svBQS-0000Kk-Sy for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:06:37 -0400 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svBQR-0004Wi-6R for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:06:36 -0400 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-5c42e7adbddso5870466a12.2 for ; Mon, 30 Sep 2024 01:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727683593; x=1728288393; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RyfJ60ZwiZ7J7acEGIws/WvnHoIJtgQD50MT+DOE6Vo=; b=Iw0cw9jhyQwNqBFrpvhQ77Dxdt+3h42LsCxDc+IX7f0c/GPASvAfsjk4kaFnhcCeD3 GnEavYHO8gfNS1MyrcRrBc87Er3pWS7bbhdxrDvhIWTM7OeUtFQeS5AtYYYIqhxgJqDr l6fqpC+ARHTVUxVUQcm1iZpoj1zCWZYJSJQc2ia+H4Ml1Yn5wZSeTt1IbjqpyspLsd30 5ObOwj6TBtzbHu5aETkGbPisxZcAZnKnDp0YyMdW6wrm8hRZ0ZFvdf4W/p4N3e9ZS+Yp oE2WBWWNaQDNHjQgRojaAjzUEWjQYWRMQQDogSK5r15nhxcWSVDvstjnfcgc/6A5FXJr EY2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727683593; x=1728288393; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RyfJ60ZwiZ7J7acEGIws/WvnHoIJtgQD50MT+DOE6Vo=; b=KLh/E/mcesqWcx266+Iu/eCWQr7ZunnDlZYsUqVWPopRahQHJdUcNVolQERUBx638t hRHQ/SvQIPoimpzmNTOjg8/MSiLvMB7FOiUxeglFVxtoZ/JSCkDjYV4TLAh6vKyNBGQY mrPIso3R7UfH1dVVhEl8pA52U3teaKLxwagR+OiDBGFD6Cev2WeG0mbegxJMmcfkXXEH IgH6APZFr1ofd/FXssB96SROfy2gPwwCh1kxx0DooEIOhC+IG0p8Ew67E5DoiuHA0NuO fVdc0BjEKXl+kJWPyX8SfwZDmL+bE6+jXQv2BPA9fjBxD1BczKycrpwYP29S8FoC1px0 MhsQ== X-Gm-Message-State: AOJu0YwiBa+FKfcbUmioPRGnGbAtRWO4O992qpnTYzpXy4P7leglapez 8duLVD0VO8cumw5gn0lsRjCsM+yRF5Ulw782koGmFtY7PS2WYtaFFAGo7Xqq9tEEW70ZF+1gjwT vhiM= X-Google-Smtp-Source: AGHT+IG2gsv4mq4+t28yXE71qvp6d8mpB4wSDB4DPNTelRdnOp6bYuTIvq+usLJM1DB/dwuL1E7PwA== X-Received: by 2002:a05:600c:45c9:b0:426:63b4:73b0 with SMTP id 5b1f17b1804b1-42f5849731fmr76872605e9.34.1727681770017; Mon, 30 Sep 2024 00:36:10 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. [88.28.13.186]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e96a52308sm141836745e9.43.2024.09.30.00.36.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 09/13] exec/memory_ldst_phys: Introduce ld/st_endian_phys() API Date: Mon, 30 Sep 2024 09:34:46 +0200 Message-ID: <20240930073450.33195-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce the ld/st_endian_phys() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_phys() methods. Signed-off-by: Philippe Mathieu-Daudé --- TODO: Update docstring regexp --- include/exec/memory_ldst_phys.h.inc | 66 +++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst_phys.h.inc index ecd678610d..8ea162b40d 100644 --- a/include/exec/memory_ldst_phys.h.inc +++ b/include/exec/memory_ldst_phys.h.inc @@ -74,6 +74,16 @@ static inline uint16_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) MEMTXATTRS_UNSPECIFIED, NULL); } +static inline uint16_t glue(lduw_endian_phys, SUFFIX)(bool big_endian, + ARG1_DECL, hwaddr addr) +{ + return big_endian + ? glue(address_space_lduw_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL) + : glue(address_space_lduw_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + static inline uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_ldl_le, SUFFIX)(ARG1, addr, @@ -86,6 +96,16 @@ static inline uint32_t glue(ldl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) MEMTXATTRS_UNSPECIFIED, NULL); } +static inline uint32_t glue(ldl_endian_phys, SUFFIX)(bool big_endian, + ARG1_DECL, hwaddr addr) +{ + return big_endian + ? glue(address_space_ldl_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL) + : glue(address_space_ldl_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + static inline uint64_t glue(ldq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_ldq_le, SUFFIX)(ARG1, addr, @@ -98,6 +118,16 @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr) MEMTXATTRS_UNSPECIFIED, NULL); } +static inline uint32_t glue(ldq_endian_phys, SUFFIX)(bool big_endian, + ARG1_DECL, hwaddr addr) +{ + return big_endian + ? glue(address_space_ldq_le, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL) + : glue(address_space_ldq_be, SUFFIX)(ARG1, addr, + MEMTXATTRS_UNSPECIFIED, NULL); +} + static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val) { glue(address_space_stb, SUFFIX)(ARG1, addr, val, @@ -116,6 +146,18 @@ static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t va MEMTXATTRS_UNSPECIFIED, NULL); } +static inline void glue(stw_endian_phys, SUFFIX)(bool big_endian, ARG1_DECL, + hwaddr addr, uint16_t val) +{ + if (big_endian) { + glue(address_space_stw_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } else { + glue(address_space_stw_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } +} + static inline void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val) { glue(address_space_stl_le, SUFFIX)(ARG1, addr, val, @@ -128,6 +170,18 @@ static inline void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t va MEMTXATTRS_UNSPECIFIED, NULL); } +static inline void glue(stl_endian_phys, SUFFIX)(bool big_endian, ARG1_DECL, + hwaddr addr, uint32_t val) +{ + if (big_endian) { + glue(address_space_stl_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } else { + glue(address_space_stl_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } +} + static inline void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val) { glue(address_space_stq_le, SUFFIX)(ARG1, addr, val, @@ -139,6 +193,18 @@ static inline void glue(stq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t va glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } + +static inline void glue(stq_endian_phys, SUFFIX)(bool big_endian, ARG1_DECL, + hwaddr addr, uint64_t val) +{ + if (big_endian) { + glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } else { + glue(address_space_stq_le, SUFFIX)(ARG1, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); + } +} #endif #undef ARG1_DECL From patchwork Mon Sep 30 07:34:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4919FCF6491 for ; Mon, 30 Sep 2024 08:05:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svBOj-0001dA-US; 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 10/13] hw/virtio/virtio-access: Use ld/st_endian_phys() API Date: Mon, 30 Sep 2024 09:34:47 +0200 Message-ID: <20240930073450.33195-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=philmd@linaro.org; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Refactor to use the recently introduced ld/st_endian_phys() API. No logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/virtio/virtio-access.h | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-access.h index b920874be8..37a42407ea 100644 --- a/include/hw/virtio/virtio-access.h +++ b/include/hw/virtio/virtio-access.h @@ -43,30 +43,21 @@ static inline uint16_t virtio_lduw_phys(VirtIODevice *vdev, hwaddr pa) { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - return lduw_be_phys(dma_as, pa); - } - return lduw_le_phys(dma_as, pa); + return lduw_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa); } static inline uint32_t virtio_ldl_phys(VirtIODevice *vdev, hwaddr pa) { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - return ldl_be_phys(dma_as, pa); - } - return ldl_le_phys(dma_as, pa); + return ldl_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa); } static inline uint64_t virtio_ldq_phys(VirtIODevice *vdev, hwaddr pa) { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - return ldq_be_phys(dma_as, pa); - } - return ldq_le_phys(dma_as, pa); + return ldq_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa); } static inline void virtio_stw_phys(VirtIODevice *vdev, hwaddr pa, @@ -74,11 +65,7 @@ static inline void virtio_stw_phys(VirtIODevice *vdev, hwaddr pa, { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - stw_be_phys(dma_as, pa, value); - } else { - stw_le_phys(dma_as, pa, value); - } + stw_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa, value); } static inline void virtio_stl_phys(VirtIODevice *vdev, hwaddr pa, @@ -86,11 +73,7 @@ static inline void virtio_stl_phys(VirtIODevice *vdev, hwaddr pa, { AddressSpace *dma_as = vdev->dma_as; - if (virtio_access_is_big_endian(vdev)) { - stl_be_phys(dma_as, pa, value); - } else { - stl_le_phys(dma_as, pa, value); - } + stl_endian_phys(virtio_access_is_big_endian(vdev), dma_as, pa, value); } static inline void virtio_stw_p(VirtIODevice *vdev, void *ptr, uint16_t v) From patchwork Mon Sep 30 07:34:48 2024 Content-Type: text/plain; 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[88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd56e6665sm8343859f8f.54.2024.09.30.00.36.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 11/13] hw/pci/pci_device: Add PCI_DMA_DEFINE_LDST_END() macro Date: Mon, 30 Sep 2024 09:34:48 +0200 Message-ID: <20240930073450.33195-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Define both endianness variants with a single macro. Useful to add yet other endian specific definitions in the next commit. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci_device.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index 91df40f989..ff619241a4 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -298,13 +298,14 @@ static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \ } +#define PCI_DMA_DEFINE_LDST_END(_l, _s, _bits) \ + PCI_DMA_DEFINE_LDST(_l##_le, _s##_le, _bits) \ + PCI_DMA_DEFINE_LDST(_l##_be, _s##_be, _bits) + PCI_DMA_DEFINE_LDST(ub, b, 8); -PCI_DMA_DEFINE_LDST(uw_le, w_le, 16) -PCI_DMA_DEFINE_LDST(l_le, l_le, 32); -PCI_DMA_DEFINE_LDST(q_le, q_le, 64); -PCI_DMA_DEFINE_LDST(uw_be, w_be, 16) -PCI_DMA_DEFINE_LDST(l_be, l_be, 32); -PCI_DMA_DEFINE_LDST(q_be, q_be, 64); +PCI_DMA_DEFINE_LDST_END(uw, w, 16) +PCI_DMA_DEFINE_LDST_END(l, l, 32) +PCI_DMA_DEFINE_LDST_END(q, q, 64) #undef PCI_DMA_DEFINE_LDST From patchwork Mon Sep 30 07:34:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD8CFCF649E for ; Mon, 30 Sep 2024 07:48:36 +0000 (UTC) Received: from [::1] (helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svB5i-0006no-VS; Mon, 30 Sep 2024 03:45:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svB58-0006ha-DP for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:44:52 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svB4D-0000X2-Au for qemu-devel@nongnu.org; Mon, 30 Sep 2024 03:44:20 -0400 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5c87c7d6ad4so3757393a12.3 for ; Mon, 30 Sep 2024 00:42:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727682143; x=1728286943; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J3QK0sGMtG8TI1HL5/V5FwLZQoUZnlZNYr8FgmUN/RY=; b=gmg7saSjmuJPt+O7T36M1yCxWkLpwIUlEGmprRhXN8JUGQa2oj1NQO5ZQYYktuMCLz /CAKbT/Qd+b/tUm3G6+gmTearftvZXk46Q6A4lPrOUoLZIyFue78acxJe524U1Rt4eCV 6kP91RJUbYIiAOOuIIzbKgnzu5uTSSAMCG7Csev8T1/L2UGXE1yHOZLOLM1ba9LYuMC2 SJoec0iUCzl3tLaHLm/u60JdNY+szQwQm5zMVjKoslYheK0vMRJs5SxurxjRFjvMScTG XqQVHVON6CDj2UIM/EBomP1eBlDB4QRJEnLkkM7fL5ocgbY7hh8cgyqvM6zUunvAnE8o VKug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727682143; x=1728286943; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J3QK0sGMtG8TI1HL5/V5FwLZQoUZnlZNYr8FgmUN/RY=; b=AmM8QIJW3cPAA200KWmB/rzwnPedoVmo0ziXWwlmKciZiTUp9CpFwsD8Uk27v+K4EQ JUUFKBzZhiPQNiEJb+8mXAExHCHGOMTcpgtVtTGxZlj0XJBKWlSTG6noaLrfgRyqutHz TvjaQ4WkBOCOL4Ll4J5ET3N/Zj2EQOqlSf58ldVG7VoUeOY67vNhvUMmbQF5nEakCbjI QpLEMIqGhJ13qVpQhyVPOnM4/YzvRneYoftfMCYKp8zA0osdycuOMC9Xq/evlrP5Zay/ 6QJdd3Z8TrknSdGOgKyxNlUc7bBE9pQupMt7fVBM8oDfk+1ZnwKlPwPriOqEgjKlVVzC K5bw== X-Gm-Message-State: AOJu0YxjlyabFC6CrJv6mzmQ1ddGXrYjVTgFdBEY+ciSNIGgyN8quR4J Bispflsh6SmNoUpd1P7Ys1kPcXXuPoI/jlXhZdPTNDa5F25BhtsHMS/l3Z3PLorjqCXV7E/ZCYY 1CAs= X-Google-Smtp-Source: AGHT+IHfyb7T2OKPtc/aN3zF39s8yY/HEtBknVQ7wiGAPxn0Lopn0hpb6weLKhFtYxrMG/LxHKBT4A== X-Received: by 2002:a5d:630c:0:b0:37c:d1fb:82fb with SMTP id ffacd0b85a97d-37cd5b3172dmr5782965f8f.36.1727681794106; Mon, 30 Sep 2024 00:36:34 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. 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Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 12/13] hw/pci/pci_device: Introduce ld/st_endian_pci_dma() API Date: Mon, 30 Sep 2024 09:34:49 +0200 Message-ID: <20240930073450.33195-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Introduce the ld/st_endian_pci_dma() API, which takes an extra boolean argument to dispatch to ld/st_{be,le}_pci_dma() methods. Signed-off-by: Philippe Mathieu-Daudé --- TODO: Update docstring regexp --- include/hw/pci/pci_device.h | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/include/hw/pci/pci_device.h b/include/hw/pci/pci_device.h index ff619241a4..dc9b17dded 100644 --- a/include/hw/pci/pci_device.h +++ b/include/hw/pci/pci_device.h @@ -300,7 +300,29 @@ static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr, #define PCI_DMA_DEFINE_LDST_END(_l, _s, _bits) \ PCI_DMA_DEFINE_LDST(_l##_le, _s##_le, _bits) \ - PCI_DMA_DEFINE_LDST(_l##_be, _s##_be, _bits) + PCI_DMA_DEFINE_LDST(_l##_be, _s##_be, _bits) \ + static inline MemTxResult ld##_l##_endian_pci_dma(bool is_big_endian, \ + PCIDevice *dev, \ + dma_addr_t addr, \ + uint##_bits##_t *val, \ + MemTxAttrs attrs) \ + { \ + AddressSpace *pci_as = pci_get_address_space(dev); \ + return is_big_endian \ + ? ld##_l##_be_dma(pci_as, addr, val, attrs) \ + : ld##_l##_le_dma(pci_as, addr, val, attrs); \ + } \ + static inline MemTxResult st##_s##_endian_pci_dma(bool is_big_endian, \ + PCIDevice *dev, \ + dma_addr_t addr, \ + uint##_bits##_t val, \ + MemTxAttrs attrs) \ + { \ + AddressSpace *pci_as = pci_get_address_space(dev); \ + return is_big_endian \ + ? st##_s##_be_dma(pci_as, addr, val, attrs) \ + : st##_s##_le_dma(pci_as, addr, val, attrs); \ + } PCI_DMA_DEFINE_LDST(ub, b, 8); PCI_DMA_DEFINE_LDST_END(uw, w, 16) From patchwork Mon Sep 30 07:34:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13815514 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2158ECF6491 for ; Mon, 30 Sep 2024 08:02:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1svBLf-0006Y7-2D; Mon, 30 Sep 2024 04:01:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1svBLO-0006A2-U0 for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:01:33 -0400 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1svBLN-0003i2-AH for qemu-devel@nongnu.org; Mon, 30 Sep 2024 04:01:22 -0400 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-5398e53ca28so1296609e87.3 for ; Mon, 30 Sep 2024 01:01:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727683279; x=1728288079; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qgFNx5loGg07bkVRCAPUaZ+t66SDahiEcwbYBeR9pKk=; b=OcrhSLLdI4UVTTegTKcFLkH0S9eazbZxrXRy5HY1H1dHikwJ6dyfEssgYEmmGLroA7 fGzoUJwWP1L+QG/mkERMnA6l+O+FU+zq8Ux4/fCq56Y5m+aazUaSVVMy8+u6kE8PKBA9 qn6qNrsRbaIXkd8at07+uGWqzFqeS+VapKWX3vIf75kRs1YbFIwHiEz/ORi/x4dqMvDp okNse1YW0LJKq3PG5V6kj+sb754EeKnZcH6zZXoOk0r1kjALfq1X4lb+CZyoG1gwFfRY 5TPx3RdXIT4HQgl1X8gPtjxXpLFt19ES7lEo/KPFi48RP7wAl9AHanx9qwa0qF1ge3vQ vXTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727683279; x=1728288079; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qgFNx5loGg07bkVRCAPUaZ+t66SDahiEcwbYBeR9pKk=; b=fTh9ExoiIZSSy4AhEfMbtc1vNVXBf2Ek6gp3Vft4DhJDaw60RBjfG4Qpp77iAGWcUp UU0sRfeg0d0dBE2HoqDWlbuMC52a5obvA/jg1MtpUGYhgRO7kO/wSiTL17RGcaF3ATy7 OSWkeZawis8aypo8P4VNjZ512evFaLQszlbU5aBNVkYEiUOJnEJxB/B+AC6bF+80cBah E4ZVOYmHdw2Ppqp8oVwByaBcaD2kNO7i6RrBVs2VxpUVZNDJGpTmaRYHGmzAmS9FMG/8 oGDDvSn9HpnkDs4gDi5Q/nGxhQSLEDLgu9aB9ANp/CdaMxbBRsVJIArC9T1Aq77Kq87b eZbQ== X-Gm-Message-State: AOJu0Yx+MJ4eZC6YOhPoqNLobRpCZmWeiJNrMCY96WupR+tKwcgbr/KZ auAOzT6fejY7TSMWFtc155HngEMzHlqzzemP9QgndJ6CZLKyfozvuvNS1c7VVxa07LZIrcV56nN C8ys= X-Google-Smtp-Source: AGHT+IFvV+g71WyrICzKtY9MUw0GkbE1ssnGCcVYI5UdtoKHuB2gzrZM3sxXfntbw5eYtIk8XvapDw== X-Received: by 2002:adf:8bd3:0:b0:37c:cd0d:3433 with SMTP id ffacd0b85a97d-37cd5a9e0f3mr6507614f8f.29.1727681802055; Mon, 30 Sep 2024 00:36:42 -0700 (PDT) Received: from localhost.localdomain (186.red-88-28-13.dynamicip.rima-tde.net. [88.28.13.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd57427c6sm8356329f8f.96.2024.09.30.00.36.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 30 Sep 2024 00:36:41 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mahmoud Mandour , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Jason Wang , Aleksandar Rikalo , Anton Johansson , Peter Maydell , Huacai Chen , "Michael S. Tsirkin" , Sven Schnelle , Jiaxun Yang , qemu-arm@nongnu.org, Aurelien Jarno , Pierrick Bouvier , Max Filippov , Paul Burton Subject: [PATCH 13/13] hw/net/tulip: Use ld/st_endian_pci_dma() API Date: Mon, 30 Sep 2024 09:34:50 +0200 Message-ID: <20240930073450.33195-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930073450.33195-1-philmd@linaro.org> References: <20240930073450.33195-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Refactor to use the recently introduced ld/st_endian_pci_dma() API. No logical change intended. Signed-off-by: Philippe Mathieu-Daudé --- hw/net/tulip.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/hw/net/tulip.c b/hw/net/tulip.c index 9df3e17162..6c67958da7 100644 --- a/hw/net/tulip.c +++ b/hw/net/tulip.c @@ -71,36 +71,24 @@ static void tulip_desc_read(TULIPState *s, hwaddr p, struct tulip_descriptor *desc) { const MemTxAttrs attrs = { .memory = true }; + bool use_big_endian = s->csr[0] & CSR0_DBO; - if (s->csr[0] & CSR0_DBO) { - ldl_be_pci_dma(&s->dev, p, &desc->status, attrs); - ldl_be_pci_dma(&s->dev, p + 4, &desc->control, attrs); - ldl_be_pci_dma(&s->dev, p + 8, &desc->buf_addr1, attrs); - ldl_be_pci_dma(&s->dev, p + 12, &desc->buf_addr2, attrs); - } else { - ldl_le_pci_dma(&s->dev, p, &desc->status, attrs); - ldl_le_pci_dma(&s->dev, p + 4, &desc->control, attrs); - ldl_le_pci_dma(&s->dev, p + 8, &desc->buf_addr1, attrs); - ldl_le_pci_dma(&s->dev, p + 12, &desc->buf_addr2, attrs); - } + ldl_endian_pci_dma(use_big_endian, &s->dev, p, &desc->status, attrs); + ldl_endian_pci_dma(use_big_endian, &s->dev, p + 4, &desc->control, attrs); + ldl_endian_pci_dma(use_big_endian, &s->dev, p + 8, &desc->buf_addr1, attrs); + ldl_endian_pci_dma(use_big_endian, &s->dev, p + 12, &desc->buf_addr2, attrs); } static void tulip_desc_write(TULIPState *s, hwaddr p, struct tulip_descriptor *desc) { const MemTxAttrs attrs = { .memory = true }; + bool use_big_endian = s->csr[0] & CSR0_DBO; - if (s->csr[0] & CSR0_DBO) { - stl_be_pci_dma(&s->dev, p, desc->status, attrs); - stl_be_pci_dma(&s->dev, p + 4, desc->control, attrs); - stl_be_pci_dma(&s->dev, p + 8, desc->buf_addr1, attrs); - stl_be_pci_dma(&s->dev, p + 12, desc->buf_addr2, attrs); - } else { - stl_le_pci_dma(&s->dev, p, desc->status, attrs); - stl_le_pci_dma(&s->dev, p + 4, desc->control, attrs); - stl_le_pci_dma(&s->dev, p + 8, desc->buf_addr1, attrs); - stl_le_pci_dma(&s->dev, p + 12, desc->buf_addr2, attrs); - } + stl_endian_pci_dma(use_big_endian, &s->dev, p, desc->status, attrs); + stl_endian_pci_dma(use_big_endian, &s->dev, p + 4, desc->control, attrs); + stl_endian_pci_dma(use_big_endian, &s->dev, p + 8, desc->buf_addr1, attrs); + stl_endian_pci_dma(use_big_endian, &s->dev, p + 12, desc->buf_addr2, attrs); } static void tulip_update_int(TULIPState *s)