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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2024 00:53:23.9435 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0cd7445-2970-4754-b11a-08dce1b373f8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6172 In preparation to add tracepoint support, move protocol error UUID definition to a common location and make CXL RAS capability struct global for use across different modules. Signed-off-by: Smita Koralahalli Reviewed-by: Dave Jiang Reviewed-by: Alison Schofield Reviewed-by: Jonathan Cameron Reviewed-by: Dan Williams Acked-by: Ard Biesheuvel --- v2: No functional change. CXL RAS Capability struct is now in include/cxl/event.h instead of include/linux/cxl-event.h --- drivers/firmware/efi/cper_cxl.c | 11 ----------- drivers/firmware/efi/cper_cxl.h | 7 ++----- include/cxl/event.h | 11 +++++++++++ include/linux/cper.h | 4 ++++ 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cxl.c index a55771b99a97..4fd8d783993e 100644 --- a/drivers/firmware/efi/cper_cxl.c +++ b/drivers/firmware/efi/cper_cxl.c @@ -18,17 +18,6 @@ #define PROT_ERR_VALID_DVSEC BIT_ULL(5) #define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6) -/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */ -struct cxl_ras_capability_regs { - u32 uncor_status; - u32 uncor_mask; - u32 uncor_severity; - u32 cor_status; - u32 cor_mask; - u32 cap_control; - u32 header_log[16]; -}; - static const char * const prot_err_agent_type_strs[] = { "Restricted CXL Device", "Restricted CXL Host Downstream Port", diff --git a/drivers/firmware/efi/cper_cxl.h b/drivers/firmware/efi/cper_cxl.h index 86bfcf7909ec..0d248ad888a1 100644 --- a/drivers/firmware/efi/cper_cxl.h +++ b/drivers/firmware/efi/cper_cxl.h @@ -7,14 +7,11 @@ * Author: Smita Koralahalli */ +#include + #ifndef LINUX_CPER_CXL_H #define LINUX_CPER_CXL_H -/* CXL Protocol Error Section */ -#define CPER_SEC_CXL_PROT_ERR \ - GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78, \ - 0x4B, 0x77, 0x10, 0x48) - #pragma pack(1) /* Compute Express Link Protocol Error Section, UEFI v2.10 sec N.2.13 */ diff --git a/include/cxl/event.h b/include/cxl/event.h index 0bea1afbd747..57b4630568f6 100644 --- a/include/cxl/event.h +++ b/include/cxl/event.h @@ -147,6 +147,17 @@ struct cxl_cper_event_rec { union cxl_event event; } __packed; +/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */ +struct cxl_ras_capability_regs { + u32 uncor_status; + u32 uncor_mask; + u32 uncor_severity; + u32 cor_status; + u32 cor_mask; + u32 cap_control; + u32 header_log[16]; +}; + struct cxl_cper_work_data { enum cxl_event_type event_type; struct cxl_cper_event_rec rec; diff --git a/include/linux/cper.h b/include/linux/cper.h index 265b0f8fc0b3..5c6d4d5b9975 100644 --- a/include/linux/cper.h +++ b/include/linux/cper.h @@ -89,6 +89,10 @@ enum { #define CPER_NOTIFY_DMAR \ GUID_INIT(0x667DD791, 0xC6B3, 0x4c27, 0x8A, 0x6B, 0x0F, 0x8E, \ 0x72, 0x2D, 0xEB, 0x41) +/* CXL Protocol Error Section */ +#define CPER_SEC_CXL_PROT_ERR \ + GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78, \ + 0x4B, 0x77, 0x10, 0x48) /* CXL Event record UUIDs are formatted as GUIDs and reported in section type */ /* From patchwork Tue Oct 1 00:52:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 13817305 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2063.outbound.protection.outlook.com [40.107.100.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DADA61C693; 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Mon, 30 Sep 2024 19:53:21 -0500 From: Smita Koralahalli To: , , CC: Ard Biesheuvel , Alison Schofield , Vishal Verma , "Ira Weiny" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Bowman Terry Subject: [PATCH v2 2/4] cxl/pci: Define a common function get_cxl_devstate() Date: Tue, 1 Oct 2024 00:52:32 +0000 Message-ID: <20241001005234.61409-3-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241001005234.61409-1-Smita.KoralahalliChannabasappa@amd.com> References: <20241001005234.61409-1-Smita.KoralahalliChannabasappa@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F5:EE_|LV8PR12MB9360:EE_ X-MS-Office365-Filtering-Correlation-Id: 038b02c9-fa2e-4b78-635e-08dce1b375a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2024 00:53:26.7530 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 038b02c9-fa2e-4b78-635e-08dce1b375a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9360 Refactor computation of cxlds to a common function get_cxl_devstate(). The above function could then be reused in both FW-First Component and Protocol error reporting and handling. Signed-off-by: Smita Koralahalli --- v2: Refactor before adding trace support. get_cxl_dev() -> get_cxl_devstate(). Cleaned up get_cxl_devstate(). --- drivers/cxl/pci.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 37164174b5fb..915102f5113f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1021,32 +1021,38 @@ static struct pci_driver cxl_pci_driver = { }, }; +static struct cxl_dev_state *get_cxl_devstate(u16 segment, u8 bus, + u8 device, u8 function) +{ + unsigned int devfn = PCI_DEVFN(device, function); + struct pci_dev *pdev __free(pci_dev_put) = + pci_get_domain_bus_and_slot(segment, bus, devfn); + + if (!pdev) + return NULL; + + guard(device)(&pdev->dev); + if (pdev->driver != &cxl_pci_driver) + return NULL; + + return pci_get_drvdata(pdev); +} + #define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0) static void cxl_handle_cper_event(enum cxl_event_type ev_type, struct cxl_cper_event_rec *rec) { struct cper_cxl_event_devid *device_id = &rec->hdr.device_id; - struct pci_dev *pdev __free(pci_dev_put) = NULL; enum cxl_event_log_type log_type; struct cxl_dev_state *cxlds; - unsigned int devfn; u32 hdr_flags; pr_debug("CPER event %d for device %u:%u:%u.%u\n", ev_type, device_id->segment_num, device_id->bus_num, device_id->device_num, device_id->func_num); - devfn = PCI_DEVFN(device_id->device_num, device_id->func_num); - pdev = pci_get_domain_bus_and_slot(device_id->segment_num, - device_id->bus_num, devfn); - if (!pdev) - return; - - guard(device)(&pdev->dev); - if (pdev->driver != &cxl_pci_driver) - return; - - cxlds = pci_get_drvdata(pdev); + cxlds = get_cxl_devstate(device_id->segment_num, device_id->bus_num, + device_id->device_num, device_id->func_num); if (!cxlds) return; From patchwork Tue Oct 1 00:52:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smita Koralahalli X-Patchwork-Id: 13817304 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2064.outbound.protection.outlook.com [40.107.93.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDA9D134C4; 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Mon, 30 Sep 2024 19:53:21 -0500 From: Smita Koralahalli To: , , CC: Ard Biesheuvel , Alison Schofield , Vishal Verma , "Ira Weiny" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Bowman Terry Subject: [PATCH v2 3/4] acpi/ghes, efi/cper: Recognize and process CXL Protocol Errors. Date: Tue, 1 Oct 2024 00:52:33 +0000 Message-ID: <20241001005234.61409-4-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241001005234.61409-1-Smita.KoralahalliChannabasappa@amd.com> References: <20241001005234.61409-1-Smita.KoralahalliChannabasappa@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F3:EE_|SA1PR12MB6847:EE_ X-MS-Office365-Filtering-Correlation-Id: 4579d8fe-956b-4ad9-328f-08dce1b37643 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: Al59W8A9M/4JLDbSheyLtRGp87nKWpNDuMiM9hOdgWH1AqJYVSEqEuBLzD0CWLBoXHfWOvXXyIoT6msVaUkXEhnjqz6XMZvrltuvBYNscGiRPkcX5K3ebJX61izO2i7JyfP9vVMQD2fKR8EPZBz+YPODGPLR+y0OVSLBV8EcT6a0+5k9UkP+LvDRVoCAKlRMzOz7DputmHJ6qssLEMVfg04He7PI+mZces0TFU2tuNraD6Pe3Ex0A5Vka+z7BDnoq5pC0+VAeNm4IPuj8vVhbmHreNRd2a9eoogQRuDKKiCpLXVl/bCmS5wiGjdLv87LA3XelZB0mWKdqfvUbi9xHkE/ylfULY35CY+MmRy6PF5+nGEc7AStgVt5ZVWLbdH/TSYRbJpBAZaoJ4lgmyM14Rl851Rn/gqKxOBrra8OczbPSVJJtkzvOWWUrNtaZ7vttt4bUUJddKb9bj/wySQj1djp4SBfQ/zRaLQrlf2RSqAPQy+U7sZYrqUT+RAXIUBPlzSghK9oNJjeo9wWDHVqMGEyLhisuWrYLsodhYY0w2drRhddSqY6pvCi0phQex9fX4JsfqIsMRXN4nYgj/Yo/8c7xLKh6TeAxxNmATV39Q2gd1ph/hU8ls/PYYa+LQfAN8rpoVo6zetEJFqiZtdFDOnZW/IYg3jJh6ZxN7NFn/KyISiAbrpdXY+7NjLJ+Z4a8LRhH7Wv1nQKl2PuQ0vk8b9yTeqrzNIFWcC2kR2hf0ksb/GVkBg2e0f5kIJo6blVGyAQxC14OarLk70V3fKQl/ZYr/NZLk8w+Azo/5aTiFtQQYe2wKCAmUfqmULvAGfbzXNg4BARaLMzFDYn/JYRT/FW+JrC/vTdy5qQ/n9vdPa0Dvsk9fiZ71xQh7f2e5bgnn2JUKRgr81gyTY1o+1otEXlq3J5FWhfvLlpy7Yrwnoimv1MtQPm2YB9fribLBey8q5SkrR/v7Oq1se3KLKDzC9YIkdwe/S/zrQx7t6VATilqRH3JUZR/htjZpTNOK9qaGqd+orBFT8TGfiZRF93qPDH4K16bhsEqNT1mPlx5+CEnV30iiZTUIsHHmgdhSHj3YBIf9UzvzX01Xk5CAu39VrlNa5iuZB9mageR7ILLcYz266/LfgSZFMm1wS0Mms3IUAQkjmrvTK4ZDFexGOs0OPTOvx+sTVvQwyMjgBgKunOiqCT3WjMzmnoYNDe9b7slHhPgUgCK/Nn1OlOO5mHpA+D0BFN1jBHAr3kyHdXhUhBRbSyn2XmUgWaDFPiShq5OCaIyrfL6sBEOrNjTwC5IvpGFvuQnxlcvXhH9hwa/ddCpCg5K/X0GaRP5+PP1BPT/ybcTlb/RawZuISpTRs5UmrdjriOkHMHaFrQWPJXUs/TYnEw1ecUKaB5TgYoZIHEVexOxR/gnU1Xb6NuMdnUBMxPq74DXdMj4tzjTg5R//V5JoS+NmGcnPSjllcCU7aP X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2024 00:53:27.7872 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4579d8fe-956b-4ad9-328f-08dce1b37643 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6847 UEFI v2.10 section N.2.13 defines a CPER record for CXL Protocol errors. Add GHES support to detect CXL CPER Protocol Error Record and Cache Error Severity, Device ID, Device Serial number and CXL RAS capability struct in struct cxl_cper_prot_err. Include this struct as a member of struct cxl_cper_work_data. Signed-off-by: Smita Koralahalli Reviewed-by: Ira Weiny --- v2: Defined array of structures for Device ID and Serial number comparison. p_err -> rec/p_rec. --- drivers/acpi/apei/ghes.c | 10 +++ drivers/firmware/efi/cper_cxl.c | 115 ++++++++++++++++++++++++++++++++ include/cxl/event.h | 26 ++++++++ 3 files changed, 151 insertions(+) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index ada93cfde9ba..9dcf0f78458f 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -717,6 +717,14 @@ static void cxl_cper_post_event(enum cxl_event_type event_type, schedule_work(cxl_cper_work); } +static void cxl_cper_handle_prot_err(struct acpi_hest_generic_data *gdata) +{ + struct cxl_cper_work_data wd; + + if (cxl_cper_handle_prot_err_info(gdata, &wd.p_rec)) + return; +} + int cxl_cper_register_work(struct work_struct *work) { if (cxl_cper_work) @@ -791,6 +799,8 @@ static bool ghes_do_proc(struct ghes *ghes, struct cxl_cper_event_rec *rec = acpi_hest_get_payload(gdata); cxl_cper_post_event(CXL_CPER_EVENT_MEM_MODULE, rec); + } else if (guid_equal(sec_type, &CPER_SEC_CXL_PROT_ERR)) { + cxl_cper_handle_prot_err(gdata); } else { void *err = acpi_hest_get_payload(gdata); diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cxl.c index 4fd8d783993e..08da7764c066 100644 --- a/drivers/firmware/efi/cper_cxl.c +++ b/drivers/firmware/efi/cper_cxl.c @@ -8,6 +8,7 @@ */ #include +#include #include "cper_cxl.h" #define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0) @@ -44,6 +45,66 @@ enum { USP, /* CXL Upstream Switch Port */ }; +struct agent_info { + const char *string; + bool req_sn; + bool req_sbdf; +}; + +static const struct agent_info agent_info[] = { + [RCD] = { + .string = "Restricted CXL Device", + .req_sbdf = true, + .req_sn = true, + }, + [RCH_DP] = { + .string = "Restricted CXL Host Downstream Port", + .req_sbdf = false, + .req_sn = false, + }, + [DEVICE] = { + .string = "CXL Device", + .req_sbdf = true, + .req_sn = true, + }, + [LD] = { + .string = "CXL Logical Device", + .req_sbdf = true, + .req_sn = true, + }, + [FMLD] = { + .string = "CXL Fabric Manager managed Logical Device", + .req_sbdf = true, + .req_sn = true, + }, + [RP] = { + .string = "CXL Root Port", + .req_sbdf = true, + .req_sn = false, + }, + [DSP] = { + .string = "CXL Downstream Switch Port", + .req_sbdf = true, + .req_sn = false, + }, + [USP] = { + .string = "CXL Upstream Switch Port", + .req_sbdf = true, + .req_sn = false, + }, +}; + +static enum cxl_aer_err_type cper_severity_cxl_aer(int cper_severity) +{ + switch (cper_severity) { + case CPER_SEV_RECOVERABLE: + case CPER_SEV_FATAL: + return CXL_AER_UNCORRECTABLE; + default: + return CXL_AER_CORRECTABLE; + } +} + void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_err) { if (prot_err->valid_bits & PROT_ERR_VALID_AGENT_TYPE) @@ -176,3 +237,57 @@ void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_e sizeof(cxl_ras->header_log), 0); } } + +int cxl_cper_handle_prot_err_info(struct acpi_hest_generic_data *gdata, + struct cxl_cper_prot_err *rec) +{ + struct cper_sec_prot_err *prot_err = acpi_hest_get_payload(gdata); + u8 *dvsec_start, *cap_start; + + if (!(prot_err->valid_bits & PROT_ERR_VALID_DEVICE_ID)) { + pr_err(FW_WARN "No Device ID\n"); + return -EINVAL; + } + + /* + * The device ID or agent address is required for CXL RCD, CXL + * SLD, CXL LD, CXL Fabric Manager Managed LD, CXL Root Port, + * CXL Downstream Switch Port and CXL Upstream Switch Port. + */ + if (!(agent_info[prot_err->agent_type].req_sbdf)) { + pr_err(FW_WARN "Invalid agent type\n"); + return -EINVAL; + } + + rec->segment = prot_err->agent_addr.segment; + rec->bus = prot_err->agent_addr.bus; + rec->device = prot_err->agent_addr.device; + rec->function = prot_err->agent_addr.function; + + if (!(prot_err->valid_bits & PROT_ERR_VALID_ERROR_LOG)) { + pr_err(FW_WARN "Invalid Protocol Error log\n"); + return -EINVAL; + } + + dvsec_start = (u8 *)(prot_err + 1); + cap_start = dvsec_start + prot_err->dvsec_len; + rec->cxl_ras = *(struct cxl_ras_capability_regs *)cap_start; + + /* + * Set device serial number unconditionally. + * + * Print a warning message if it is not valid. The device serial + * number is required for CXL RCD, CXL SLD, CXL LD and CXL Fabric + * Manager Managed LD. + */ + if (!(prot_err->valid_bits & PROT_ERR_VALID_SERIAL_NUMBER) || + !(agent_info[prot_err->agent_type].req_sn)) + pr_warn(FW_WARN "No Device Serial number\n"); + + rec->lower_dw = prot_err->dev_serial_num.lower_dw; + rec->upper_dw = prot_err->dev_serial_num.upper_dw; + + rec->severity = cper_severity_cxl_aer(gdata->error_severity); + + return 0; +} diff --git a/include/cxl/event.h b/include/cxl/event.h index 57b4630568f6..5b316150556a 100644 --- a/include/cxl/event.h +++ b/include/cxl/event.h @@ -158,11 +158,37 @@ struct cxl_ras_capability_regs { u32 header_log[16]; }; +enum cxl_aer_err_type { + CXL_AER_UNCORRECTABLE, + CXL_AER_CORRECTABLE, +}; + +struct cxl_cper_prot_err { + struct cxl_ras_capability_regs cxl_ras; + + /* Device ID */ + u8 function; + u8 device; + u8 bus; + u16 segment; + + /* Device Serial Number */ + u32 lower_dw; + u32 upper_dw; + + int severity; +}; + struct cxl_cper_work_data { enum cxl_event_type event_type; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2024 00:53:28.6309 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d7eb268-e517-45a0-5370-08dce1b376c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4288 When PCIe AER is in FW-First, OS should process CXL Protocol errors from CPER records. Reuse the existing work queue cxl_cper_work registered with GHES to notify the CXL subsystem on a Protocol error. The defined trace events cxl_aer_uncorrectable_error and cxl_aer_correctable_error currently trace native CXL AER errors. Reuse them to trace FW-First Protocol Errors. Signed-off-by: Smita Koralahalli --- v2: Removed pr_warn for serial number. p_err -> rec/p_rec. --- drivers/acpi/apei/ghes.c | 14 ++++++++++++++ drivers/cxl/core/pci.c | 24 ++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 +++ drivers/cxl/pci.c | 20 ++++++++++++++++++-- include/cxl/event.h | 1 + 5 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 9dcf0f78458f..5082885e1f2c 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -723,6 +723,20 @@ static void cxl_cper_handle_prot_err(struct acpi_hest_generic_data *gdata) if (cxl_cper_handle_prot_err_info(gdata, &wd.p_rec)) return; + + guard(spinlock_irqsave)(&cxl_cper_work_lock); + + if (!cxl_cper_work) + return; + + wd.event_type = CXL_CPER_EVENT_PROT_ERR; + + if (!kfifo_put(&cxl_cper_fifo, wd)) { + pr_err_ratelimited("CXL CPER kfifo overflow\n"); + return; + } + + schedule_work(cxl_cper_work); } int cxl_cper_register_work(struct work_struct *work) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 5b46bc46aaa9..39ef24c8991f 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -650,6 +650,30 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL); +void cxl_trace_prot_err(struct cxl_dev_state *cxlds, + struct cxl_cper_prot_err *rec) +{ + u32 status, fe; + + if (rec->severity == CXL_AER_CORRECTABLE) { + status = rec->cxl_ras.cor_status & ~rec->cxl_ras.cor_mask; + + trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + } else { + status = rec->cxl_ras.uncor_status & ~rec->cxl_ras.uncor_mask; + + if (hweight32(status) > 1) + fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, + rec->cxl_ras.cap_control)); + else + fe = status; + + trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, + rec->cxl_ras.header_log); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_trace_prot_err, CXL); + static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 4da07727ab9c..8acd8f2c39c9 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -129,4 +129,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +struct cxl_cper_prot_err; +void cxl_trace_prot_err(struct cxl_dev_state *cxlds, + struct cxl_cper_prot_err *rec); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 915102f5113f..0a29321921a0 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1064,12 +1064,28 @@ static void cxl_handle_cper_event(enum cxl_event_type ev_type, &uuid_null, &rec->event); } +static void cxl_handle_prot_err(struct cxl_cper_prot_err *rec) +{ + struct cxl_dev_state *cxlds; + + cxlds = get_cxl_devstate(rec->segment, rec->bus, + rec->device, rec->function); + if (!cxlds) + return; + + cxl_trace_prot_err(cxlds, rec); +} + static void cxl_cper_work_fn(struct work_struct *work) { struct cxl_cper_work_data wd; - while (cxl_cper_kfifo_get(&wd)) - cxl_handle_cper_event(wd.event_type, &wd.rec); + while (cxl_cper_kfifo_get(&wd)) { + if (wd.event_type == CXL_CPER_EVENT_PROT_ERR) + cxl_handle_prot_err(&wd.p_rec); + else + cxl_handle_cper_event(wd.event_type, &wd.rec); + } } static DECLARE_WORK(cxl_cper_work, cxl_cper_work_fn); diff --git a/include/cxl/event.h b/include/cxl/event.h index 5b316150556a..d854d8c435db 100644 --- a/include/cxl/event.h +++ b/include/cxl/event.h @@ -115,6 +115,7 @@ struct cxl_event_record_raw { } __packed; enum cxl_event_type { + CXL_CPER_EVENT_PROT_ERR, CXL_CPER_EVENT_GENERIC, CXL_CPER_EVENT_GEN_MEDIA, CXL_CPER_EVENT_DRAM,