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Tue, 01 Oct 2024 01:35:51 -0700 (PDT) From: Bartosz Golaszewski Date: Tue, 01 Oct 2024 10:35:30 +0200 Subject: [PATCH v7 1/2] arm64: dts: qcom: sm8650: extend the register range for UFS ICE Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241001-wrapped-keys-dts-v7-1-a668519b7ffe@linaro.org> References: <20241001-wrapped-keys-dts-v7-0-a668519b7ffe@linaro.org> In-Reply-To: <20241001-wrapped-keys-dts-v7-0-a668519b7ffe@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski , Om Prakash Singh , Neil Armstrong , Gaurav Kashyap X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1273; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=G/MbeLTD1yijbokrC0s2c0EyRGDKayzx4cP1dLSlqkU=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBm+7RlISNdxOU5w3B+q5g3zeZQr1mZX75d2d2Op bBQBCW2pLaJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCZvu0ZQAKCRARpy6gFHHX csEJEACUwVzRK8WCaNE9HY4J2E0pCltqZsaCUTrts+1+CZhrJgLX5wMBNeV0Mb9Xce67tca2rzI CDpl2Aw2Y9CxhFGeBWwisMEqtZ9Kpgw9bEEcN0eGnOeoBSQR+3V9VlDwrZPJtOVjBG6KJWid1Eg zH9CQ4fgImpWgssYm733WZIuCMaMaMeGg9BV0P3miBPBhI9DQTh4sYWP6wvxMFODGQLAM18pLmJ HV9kb5vTBoTnbfrteI0ZblL0zU0IvkNpyLsvTX4Rc03lqhddxA1mm/Uu5SSJ+4QddrJD4Zbr7cs JpEVHLR2XtwsZ830GooQXt9kdJ4ZxrA3L09epj3Dtg+XQEgh38d/eKkuwlaCMlw4+X5k8XYWYP/ HXTh5lJXANSm+2UcWAVQLHkRvkBcLIgffMJ6DHVi4MMqgWeOPga/zUo8OvPiep4Zq/ufiTlsG2Z evuSqnvZlD361vZUwt4i0PyiA79DkQThQe3NtPWh1ji8PA53+I3bfAtFK0MhA+nh/xSZVOJBELn aqRykXCj1JLgRNUIhLK49GBYhw0DLbLIGE3UDBoEi3X2HdQBXxhHhFOFAn4lajaLOsuJGggDsxY rKzmGFt6G35RHHlgLrQ9uDX8mAN7YTXtfZBL2GB7+o0wEY44BtKM/sqp8yb2cEfMDSX4TWEE3L6 KsW4xgmanaMZTrg== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski The Inline Crypto Engine (ICE) for UFS/EMMC supports the Hardware Key Manager (HWKM) to securely manage storage keys. Enable using this hardware on sm8650. This requires us to increase the register range: HWKM is an additional piece of hardware sitting alongside ICE, and extends the old ICE's register space. Reviewed-by: Om Prakash Singh Tested-by: Neil Armstrong Signed-off-by: Gaurav Kashyap Co-developed-by: Gaurav Kashyap Signed-off-by: Bartosz Golaszewski Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 01ac3769ffa6..5986a33ddd8b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2595,7 +2595,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, ice: crypto@1d88000 { compatible = "qcom,sm8650-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; From patchwork Tue Oct 1 08:35:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 13817645 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5416619AD4F for ; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski The Inline Crypto Engine (ICE) for UFS/EMMC supports the Hardware Key Manager (HWKM) to securely manage storage keys. Enable using this hardware on sm8550. This requires us to increase the register range: HWKM is an additional piece of hardware sitting alongside ICE, and extends the old ICE's register space. NOTE: Although wrapped keys cannot be independently generated and tested on this platform using generate, prepare and import key calls, there are non-kernel paths to create wrapped keys, and still use the kernel to program them into ICE. Hence, enabling wrapped key support on sm8550 too. Signed-off-by: Gaurav Kashyap Co-developed-by: Gaurav Kashyap Signed-off-by: Bartosz Golaszewski Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9dc0ee3eb98f..93c8aa32e411 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2076,7 +2076,8 @@ opp-300000000 { ice: crypto@1d88000 { compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; };