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Tue, 01 Oct 2024 11:37:46 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 491BbjUO002793; Tue, 1 Oct 2024 11:37:45 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com ([10.213.96.82]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 491BbjWV002790 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 01 Oct 2024 11:37:45 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 2370923) id 52A2353F; Tue, 1 Oct 2024 17:07:44 +0530 (+0530) From: Vivek Pernamitta To: mhi@lists.linux.dev Cc: quic_qianyu@quicinc.com, manivannan.sadhasivam@linaro.org, quic_vbadigan@quicinc.com, quic_krichai@quicinc.com, quic_skananth@quicinc.com, mrana@quicinc.com, Vivek Pernamitta , Slark Xiao , Fabio Porcedda , Mank Wang , linux-arm-msm@vger.kernel.org (open list:MHI BUS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH] bus: mhi: host: pci_generic: Add support for QDU100 device Date: Tue, 1 Oct 2024 17:07:35 +0530 Message-Id: <20241001113738.152467-1-quic_vpernami@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: HA-iO2LzxR8uE8Ptc_-sEAJaWS0yY6ad X-Proofpoint-GUID: HA-iO2LzxR8uE8Ptc_-sEAJaWS0yY6ad X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 mlxscore=0 clxscore=1011 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2410010075 Add MHI controller configuration for QDU100 device. This Qualcomm QDU100 device is inline accelerator card which is an extension to QRU100 5G RAN platform. which is designed to simplify 5G deployments by offering a turnkey solution for ease of deployment with O-RAN fronthaul and 5G NR layer 1 High (L1 High) processing, and to accelerate operator and infrastructure vendor adoption of virtualized RAN platforms. https://docs.qualcomm.com/bundle/publicresource/87-79371-1_REV_A_Qualcomm_X100_5G_RAN_Accelerator_Card_Product_Brief.pdf Signed-off-by: Vivek Pernamitta --- drivers/bus/mhi/host/pci_generic.c | 49 ++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index 9938bb034c1c..1153697fa858 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -245,6 +245,52 @@ struct mhi_pci_dev_info { .channel = ch_num, \ } +static const struct mhi_channel_config modem_qcom_qdu100_mhi_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), + MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), + MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), + MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), + MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), + MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), + MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), + MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), + MHI_CHANNEL_CONFIG_UL(48, "IP_SW1", 256, 6), + MHI_CHANNEL_CONFIG_DL(49, "IP_SW1", 256, 6), + MHI_CHANNEL_CONFIG_UL(50, "IP_SW2", 256, 7), + MHI_CHANNEL_CONFIG_DL(51, "IP_SW2", 256, 7), +}; + +static struct mhi_event_config modem_qcom_qdu100_mhi_events[] = { + /* first ring is control+data ring */ + MHI_EVENT_CONFIG_CTRL(0, 64), + /* SAHARA dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(1, 256), + /* Software channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(2, 64), + MHI_EVENT_CONFIG_SW_DATA(3, 256), + MHI_EVENT_CONFIG_SW_DATA(4, 256), + /* Software IP channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(5, 512), + MHI_EVENT_CONFIG_SW_DATA(6, 512), + MHI_EVENT_CONFIG_SW_DATA(7, 512), +}; + +static const struct mhi_controller_config modem_qcom_qdu100_mhi_config = { + .max_channels = 128, + .timeout_ms = 120000, + .num_channels = ARRAY_SIZE(modem_qcom_qdu100_mhi_channels), + .ch_cfg = modem_qcom_qdu100_mhi_channels, + .num_events = ARRAY_SIZE(modem_qcom_qdu100_mhi_events), + .event_cfg = modem_qcom_qdu100_mhi_events, +}; + static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), @@ -822,6 +868,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* NETPRISMA FCUN69 (SDX6X) */ { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, + /* QDU100, x100-DU */ + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), + .driver_data = (kernel_ulong_t)&modem_qcom_qdu100_mhi_config }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);