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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aVtNSBJDHyLSP3PrgxyyxNzxXlykT9baVBFDL6a20NubRRPPMZ3JX0GbCxw5u911Nj7EU/JD0Fwnb+srE+qOH1awiI8pSMpN9lpg8vsrS6ZSlNJ4L+K/rbLaZAHmHFBYb7OOqXZALXwkinRMfnljj+N53upIK7zJ17KFSdB//vvqCrypCABLTJYAiT7715NDV3QvMkSMrMDiTP4r3r1nsBiiD9xG6Iq6/vptGjFcb3bCt9ZX8f+ddU7YuVGzsmrWORSQ/MxNW9+BvsVFpSOXuGOCtFKxgyH17kusCjTfQy3hSzWi096+4Qo9dYeFqyzPUo9TdqYaRJKI/hWZVuJEwyKiqCa7hp05T1FNA3Qvg2iTxG+IWuMmLnjpaQOSWGa06eI7UjgDuwFoAgrl6mPNLdovfUdv9b8+sOa+JHHwTjKe5Ac42vvLE17dJQqCRk/QXDrs7mo5XK5YQnKVUfibVLYPHYeQ/0JpNORNwABO5PM6eNbSjSvigQiVlfexT0VyJrs5vZAZClKKpUcuq+ollD0dPsQet28UcAPkwl4zrjxqsR8ZdHb81/sezWqzo4h1qce0c6ZKH8FEslaJ7FLJOXwrllDDHzU51VPbA3XiMOgzYxLBzO0oGM+LrKmUOrv9nJzAIRlGfv90xQyNgLYVa9vWQ7+GGcPeEcWiLrju3I/j5E2RcVSHYKQaAueddYiAFonKsraSROxeVgwWI+qTJjNWk1egIwAAxVrfl8MtT7fWeXLDUE51ygfEmlZIqgIdRuPIuwjFXOHN0Fjmng41SNykXFGOejU3k3A9Xhqa7ARNLkklGY8lSq05iWO9PlWiWWYBlitzTi/VMgnqIrEKuWgttyyUEa51X5LheUUm+5v1UHDnHeu/RBx0D/OslfdvfpmtlO/JPd96vGGNyQyVNw6WHzflhE12NNB3S3QtVV4t5GETEerpU+FrpERj/3In+MxhXc7tyFkz0lL5IVJtQs/uNS8B5yP9gQmr0wnJI3FP5FKhjLzuZI52KikemeQCvVHr30YZmPTV/Hn1JULHqOkMPan1/soW86uVPpZlGcDR2Uee9pxhY8pmzHL2GSjVo5vhP/6L+y7+Hs8IxWwToI6AczV4CJHevq0+/0ECvQc3Asfq4vA1csKvn+l+jSKO7An6RjmFcOJvDykWEBkd8+1jLiYm8eJ5hzUqxYgdnunkehDGvhh0WyzzGSk9wEBJ6pJzqYrhQxAc65dvXPTnucwrheiXak5EHoIKbpEPdaSz0lXzYYocrhV7CntrsRwIAgWDlDPXNqqNR388hyN6Gvb9YkELgXT9kQDGlNJRVr44yjwrM+wRwnA+IhSCPoejFwLUhWquyxjD+Wt5DxSL2X6uyvzg0So0N88VyKRVheKt8EHR+Du85GROjw3SbKRqnoDWfrOPrhxPK9la689OX6zGR1uNSzPlQutVwPr8Oi6WAnHw8m+RmdR6J/jMsl//XberYb/KPxGKPfws4HhSyqVu67xa7h56pcnfGPwwE0pJL/kl+mlutFOta/letooJx4NQqRjE7Gat4+E24OwCaHt+2gOELkTgmHYtDivIml++PhKwx9fRub8qIfKKOe0C7+77G4dpM59ObqNWFAvgXSdJBZkfxN27FhJzD3IrycI= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: eb67af99-ab8b-4dae-db23-08dce2436e68 X-MS-Exchange-CrossTenant-AuthSource: CH0PR01MB6873.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2024 18:04:02.5545 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lgzKFlnl4xt9BNNcD7V125yHv1WVuMcjtBqb1m2Zy6KVCZWtXuUVlXyJpmKkn7yZ9r9YNX/fuFU+/fsKIH0yyb9rhzJEdWSJPn0yzFktvWE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR01MB8580 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241001_110410_528152_AE3FC86B X-CRM114-Status: GOOD ( 12.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The commit ce410410f1a7 ("iommu/arm-smmu-v3: Add arm_smmu_strtab_l1/2_idx()") calculated the last index of L1 stream table by 1 << smmu->sid_bits. 1 is 32 bit value. However AmpereOne has 32-bit stream id size. This resulted in ouf-of-bound shift. The disassembly of shift is: ldr w2, [x19, 828] //, smmu_7(D)->sid_bits mov w20, 1 lsl w20, w20, w2 According to ARM spec, if the registers are 32 bit, the instruction actually does: dest = src << (shift % 32) So it actually shifted by zero bit. This caused v6.12-rc1 failed to boot on AmpereOne and UBSAN also reported: UBSAN: shift-out-of-bounds in drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3628:29 shift exponent 32 is too large for 32-bit type 'int' CPU: 70 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.12.0-rc1 #4 Hardware name: ZOLLNER SUNMOONLAKE/SunMoon Lake, BIOS 00.00. 2024-08-28 18:42:45 08/28/2024 Call trace: dump_backtrace+0xdc/0x140 show_stack+0x20/0x40 dump_stack_lvl+0x60/0x80 dump_stack+0x18/0x28 ubsan_epilogue+0x10/0x48 __ubsan_handle_shift_out_of_bounds+0xd8/0x1a0 arm_smmu_init_structures+0x374/0x3c8 arm_smmu_device_probe+0x208/0x600 platform_probe+0x70/0xe8 really_probe+0xc8/0x3a0 __driver_probe_device+0x84/0x160 driver_probe_device+0x44/0x130 __driver_attach+0xcc/0x208 bus_for_each_dev+0x84/0x100 driver_attach+0x2c/0x40 bus_add_driver+0x158/0x290 driver_register+0x70/0x138 __platform_driver_register+0x2c/0x40 arm_smmu_driver_init+0x28/0x40 do_one_initcall+0x60/0x318 do_initcalls+0x198/0x1e0 kernel_init_freeable+0x18c/0x1e8 kernel_init+0x28/0x160 ret_from_fork+0x10/0x20 Using 64 bit immediate when doing shift can solve the problem. The disssembly after the fix looks like: ldr w20, [x19, 828] //, smmu_7(D)->sid_bits mov x0, 1 lsl x0, x0, x20 Signed-off-by: Yang Shi Tested-by: James Morse Tested-by: James Morse --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 737c5b882355..01a2faee04bc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3625,7 +3625,7 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu) u32 l1size; struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; unsigned int last_sid_idx = - arm_smmu_strtab_l1_idx((1 << smmu->sid_bits) - 1); + arm_smmu_strtab_l1_idx((1UL << smmu->sid_bits) - 1); /* Calculate the L1 size, capped to the SIDSIZE. */ cfg->l2.num_l1_ents = min(last_sid_idx + 1, STRTAB_MAX_L1_ENTRIES);