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Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- Change from v1 to v2 - none On going discussion: https://lore.kernel.org/imx/20240930-pci_fixup_addr-v3-2-80ee70352fc7@nxp.com/ don't affect this dts. This work for with/without above patches. --- .../boot/dts/freescale/imx8-ss-hsio.dtsi | 123 +++++++++++ .../boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 52 +++++ arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 + .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 209 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 + .../boot/dts/freescale/imx8qxp-ss-hsio.dtsi | 41 ++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 + 7 files changed, 431 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi new file mode 100644 index 0000000000000..bf05cae05d27a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * + * Richard Zhu + */ +#include + +hsio_axi_clk: clock-hsio-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "hsio_axi_clk"; +}; + +hsio_per_clk: clock-hsio-per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + clock-output-names = "hsio_per_clk"; +}; + +hsio_refa_clk: clock-hsio-refa { + compatible = "gpio-gate-clock"; + clocks = <&xtal100m>; + #clock-cells = <0>; + enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; +}; + +hsio_refb_clk: clock-hsio-refb { + compatible = "gpio-gate-clock"; + clocks = <&xtal100m>; + #clock-cells = <0>; + enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; +}; + +xtal100m: clock-xtal100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "xtal_100MHz"; +}; + +hsio_subsys: bus@5f000000 { + compatible = "simple-bus"; + ranges = <0x5f000000 0x0 0x5f000000 0x21000000>, + <0x80000000 0x0 0x70000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x80000000 0 0x80000000 0x80000000>; + + pcieb: pcie@5f010000 { + compatible = "fsl,imx8q-pcie"; + reg = <0x5f010000 0x10000>, + <0x8ff00000 0x80000>; + reg-names = "dbi", "config"; + ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, + <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, + <&pcieb_lpcg IMX_LPCG_CLK_4>, + <&pcieb_lpcg IMX_LPCG_CLK_5>; + clock-names = "dbi", "mstr", "slv"; + bus-range = <0x00 0xff>; + device_type = "pci"; + fsl,max-link-speed = <3>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + interrupt-map-mask = <0 0 0 0x7>; + num-lanes = <1>; + num-viewport = <4>; + power-domains = <&pd IMX_SC_R_PCIE_B>; + status = "disabled"; + }; + + pcieb_lpcg: clock-controller@5f060000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f060000 0x10000>; + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; + #clock-cells = <1>; + clock-indices = , , ; + clock-output-names = "hsio_pcieb_mstr_axi_clk", + "hsio_pcieb_slv_axi_clk", + "hsio_pcieb_dbi_axi_clk"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + }; + + phyx1_crr1_lpcg: clock-controller@5f0b0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0b0000 0x10000>; + clocks = <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "hsio_phyx1_per_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + pcieb_crr3_lpcg: clock-controller@5f0d0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0d0000 0x10000>; + clocks = <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "hsio_pcieb_per_clk"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + }; + + misc_crr5_lpcg: clock-controller@5f0f0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0f0000 0x10000>; + clocks = <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "hsio_misc_per_clk"; + power-domains = <&pd IMX_SC_R_HSIO_GPIO>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi new file mode 100644 index 0000000000000..f3104e205ae89 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +&hsio_subsys { + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = , , + , ; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + hsio_phy: phy@5f1a0000 { + compatible = "fsl,imx8qxp-hsio"; + reg = <0x5f1a0000 0x10000>, + <0x5f120000 0x10000>, + <0x5f140000 0x10000>, + <0x5f160000 0x10000>; + reg-names = "reg", "phy", "ctrl", "misc"; + clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>, + <&phyx1_lpcg IMX_LPCG_CLK_4>, + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, + <&misc_crr5_lpcg IMX_LPCG_CLK_4>; + clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", + "misc_crr"; + #phy-cells = <3>; + power-domains = <&pd IMX_SC_R_SERDES_1>; + status = "disabled"; + }; +}; + +&pcieb { + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + interrupt-map = <0 0 0 1 &gic 0 47 4>, + <0 0 0 2 &gic 0 48 4>, + <0 0 0 3 &gic 0 49 4>, + <0 0 0 4 &gic 0 50 4>; + interrupt-map-mask = <0 0 0 0x7>; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 7e54cf2028580..76de3db8b9423 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -237,12 +237,14 @@ xtal24m: clock-xtal24m { #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" }; #include "imx8dxl-ss-adma.dtsi" #include "imx8dxl-ss-conn.dtsi" #include "imx8dxl-ss-lsio.dtsi" #include "imx8dxl-ss-ddr.dtsi" +#include "imx8dxl-ss-hsio.dtsi" &cm40_intmux { interrupts = , diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi new file mode 100644 index 0000000000000..6494f55d33f85 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Richard Zhu + */ + +&hsio_subsys { + compatible = "simple-bus"; + ranges = <0x5f000000 0x0 0x5f000000 0x21000000>, + <0x40000000 0x0 0x60000000 0x10000000>, + <0x80000000 0x0 0x70000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + pciea: pcie@5f000000 { + compatible = "fsl,imx8q-pcie"; + reg = <0x5f000000 0x10000>, + <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>, + <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&pciea_lpcg 2>, + <&pciea_lpcg 0>, + <&pciea_lpcg 1>; + clock-names = "dbi", "mstr", "slv"; + bus-range = <0x00 0xff>; + device_type = "pci"; + fsl,max-link-speed = <3>; + interrupt-map = <0 0 0 1 &gic 0 73 4>, + <0 0 0 2 &gic 0 74 4>, + <0 0 0 3 &gic 0 75 4>, + <0 0 0 4 &gic 0 76 4>; + interrupt-map-mask = <0 0 0 0x7>; + num-lanes = <1>; + num-viewport = <4>; + power-domains = <&pd IMX_SC_R_PCIE_A>; + status = "disabled"; + }; + + pcieb: pcie@5f010000 { + compatible = "fsl,imx8q-pcie"; + reg = <0x5f010000 0x10000>, + <0x8ff00000 0x80000>; + reg-names = "dbi", "config"; + ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, + <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; + #interrupt-cells = <1>; + interrupts = ; + interrupt-names = "msi"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&pcieb_lpcg 2>, + <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>; + clock-names = "dbi", "mstr", "slv"; + bus-range = <0x00 0xff>; + device_type = "pci"; + fsl,max-link-speed = <3>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + interrupt-map-mask = <0 0 0 0x7>; + num-lanes = <1>; + num-viewport = <4>; + power-domains = <&pd IMX_SC_R_PCIE_B>; + status = "disabled"; + }; + + sata: sata@5f020000 { + compatible = "fsl,imx8qm-ahci"; + reg = <0x5f020000 0x10000>; + interrupts = ; + clocks = <&sata_lpcg 0>, + <&sata_crr4_lpcg 0>; + clock-names = "sata", "sata_ref"; + /* + * Since "REXT" pin is only present for first lane PHY + * and its calibration result will be stored, and shared + * by the PHY used by SATA. + * + * Add the calibration PHYs for SATA here, although only + * the third lane PHY is used by SATA. + */ + phys = <&hsio_phy 2 PHY_TYPE_SATA 0>, + <&hsio_phy 0 PHY_TYPE_PCIE 0>, + <&hsio_phy 1 PHY_TYPE_PCIE 1>; + phy-names = "sata-phy", "cali-phy0", "cali-phy1"; + power-domains = <&pd IMX_SC_R_SATA_0>; + status = "disabled"; + }; + + pciea_lpcg: clock-controller@5f050000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f050000 0x10000>; + clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; + #clock-cells = <1>; + clock-indices = , , ; + clock-output-names = "hsio_pciea_mstr_axi_clk", + "hsio_pciea_slv_axi_clk", + "hsio_pciea_dbi_axi_clk"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + }; + + sata_lpcg: clock-controller@5f070000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f070000 0x10000>; + clocks = <&hsio_axi_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "hsio_sata_clk"; + power-domains = <&pd IMX_SC_R_SATA_0>; + }; + + phyx2_lpcg: clock-controller@5f080000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f080000 0x10000>; + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, + <&hsio_refa_clk>, <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = , , + , ; + clock-output-names = "hsio_phyx2_pclk_0", + "hsio_phyx2_pclk_1", + "hsio_phyx2_apbclk_0", + "hsio_phyx2_apbclk_1"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + }; + + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + clocks = <&hsio_refa_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = , , + , ; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + phyx2_crr0_lpcg: clock-controller@5f0a0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0a0000 0x10000>; + clocks = <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "hsio_phyx2_per_clk"; + power-domains = <&pd IMX_SC_R_SERDES_0>; + }; + + pciea_crr2_lpcg: clock-controller@5f0c0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0c0000 0x10000>; + clocks = <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "hsio_pciea_per_clk"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + }; + + sata_crr4_lpcg: clock-controller@5f0e0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f0e0000 0x10000>; + clocks = <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "hsio_sata_per_clk"; + power-domains = <&pd IMX_SC_R_SATA_0>; + }; + + hsio_phy: phy@5f180000 { + compatible = "fsl,imx8qm-hsio"; + reg = <0x5f180000 0x30000>, + <0x5f110000 0x20000>, + <0x5f130000 0x30000>, + <0x5f160000 0x10000>; + reg-names = "reg", "phy", "ctrl", "misc"; + clocks = <&phyx2_lpcg IMX_LPCG_CLK_0>, + <&phyx2_lpcg IMX_LPCG_CLK_1>, + <&phyx2_lpcg IMX_LPCG_CLK_4>, + <&phyx2_lpcg IMX_LPCG_CLK_5>, + <&phyx1_lpcg IMX_LPCG_CLK_0>, + <&phyx1_lpcg IMX_LPCG_CLK_1>, + <&phyx1_lpcg IMX_LPCG_CLK_2>, + <&phyx1_lpcg IMX_LPCG_CLK_4>, + <&phyx2_crr0_lpcg IMX_LPCG_CLK_4>, + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, + <&pciea_crr2_lpcg IMX_LPCG_CLK_4>, + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, + <&sata_crr4_lpcg IMX_LPCG_CLK_4>, + <&misc_crr5_lpcg IMX_LPCG_CLK_4>; + clock-names = "pclk0", "pclk1", "apb_pclk0", "apb_pclk1", + "pclk2", "epcs_tx", "epcs_rx", "apb_pclk2", + "phy0_crr", "phy1_crr", "ctl0_crr", + "ctl1_crr", "ctl2_crr", "misc_crr"; + #phy-cells = <3>; + power-domains = <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_SERDES_1>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 3ee6e2869e3cf..ac9064a949d82 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -594,6 +594,7 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll { #include "imx8-ss-dma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" }; #include "imx8qm-ss-img.dtsi" @@ -603,3 +604,4 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll { #include "imx8qm-ss-audio.dtsi" #include "imx8qm-ss-lvds.dtsi" #include "imx8qm-ss-mipi.dtsi" +#include "imx8qm-ss-hsio.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi new file mode 100644 index 0000000000000..47fc6e0cff4a1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Richard Zhu + */ + +&hsio_subsys { + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + #clock-cells = <1>; + clock-indices = , , + , ; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; + + hsio_phy: phy@5f1a0000 { + compatible = "fsl,imx8qxp-hsio"; + reg = <0x5f1a0000 0x10000>, + <0x5f120000 0x10000>, + <0x5f140000 0x10000>, + <0x5f160000 0x10000>; + reg-names = "reg", "phy", "ctrl", "misc"; + clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>, + <&phyx1_lpcg IMX_LPCG_CLK_1>, + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, + <&misc_crr5_lpcg IMX_LPCG_CLK_4>; + clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", + "misc_crr"; + #phy-cells = <3>; + power-domains = <&pd IMX_SC_R_SERDES_1>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 0313f295de2e9..db21c6d64f24d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -323,6 +323,7 @@ map0 { #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" }; 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Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- chagne from v1 to v1 - supports -> support - add space before { --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 4caaecc192277..6259186cd4d92 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -182,6 +182,15 @@ mii_select: regulator-4 { regulator-always-on; }; + reg_pcieb: regulator-pcieb { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "reg_pcieb"; + gpio = <&pca6416_1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + bt_sco_codec: audio-codec-bt { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; @@ -567,6 +576,12 @@ &flexcan3 { status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "output"; + status = "okay"; +}; + &cm40_intmux { status = "disabled"; }; @@ -585,6 +600,16 @@ &lsio_gpio5 { status = "okay"; }; +&pcieb { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcieb>; + status = "okay"; +}; + &sai0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai0>; @@ -868,6 +893,14 @@ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 >; }; + pinctrl_pcieb: pcieagrp { + fsl,pins = < + IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + pinctrl_sai0: sai0grp { fsl,pins = < IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060 From patchwork Thu Oct 3 18:15:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13821372 Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11011024.outbound.protection.outlook.com [52.101.65.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 079578BF0 for ; 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Signed-off-by: Frank Li --- Chagne from v1 to v2 - none --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 936ba5ecdcac7..9f643a4ce8ae7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -45,6 +45,15 @@ usb3_data_ss: endpoint { }; }; + reg_pcieb: regulator-pcie { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "mpcie_3v3"; + gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + sound-wm8960 { compatible = "fsl,imx-audio-wm8960"; model = "wm8960-audio"; @@ -246,6 +255,12 @@ &cm40_intmux { status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -272,6 +287,16 @@ &mu1_m0 { status = "okay"; }; +&pcieb { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcieb>; + status = "okay"; +}; + &scu_key { status = "okay"; }; @@ -493,6 +518,14 @@ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 >; }; + pinctrl_pcieb: pcieagrp { + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + pinctrl_typec: typecgrp { fsl,pins = < IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 From patchwork Thu Oct 3 18:15:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13821373 Received: from DUZPR83CU001.outbound.protection.outlook.com (mail-northeuropeazon11013044.outbound.protection.outlook.com [52.101.67.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A58AF1ABEA7 for ; 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Signed-off-by: Frank Li --- change from v1 to v2 - add space before { --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 62 ++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 62203eed6a6cb..e983633a4bb31 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -181,6 +181,17 @@ reg_can2_stby: regulator-can2-stby { vin-supply = <®_can2_en>; }; + reg_pciea: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-0 = <&pinctrl_pciea_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "mpcie_3v3"; + gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_vref_1v8: regulator-adc-vref { compatible = "regulator-fixed"; regulator-name = "vref_1v8"; @@ -296,6 +307,12 @@ &cm41_intmux { status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-pcieb-sata"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + &i2c0 { #address-cells = <1>; #size-cells = <0>; @@ -541,6 +558,25 @@ &fec2 { status = "okay"; }; +&pciea { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pciea>; + pinctrl-names = "default"; + reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pciea>; + status = "okay"; +}; + +&pcieb { + phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + &qm_pwm_lvds0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_lvds0>; @@ -640,6 +676,10 @@ &sai7 { status = "okay"; }; +&sata { + status = "okay"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -829,6 +869,28 @@ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c >; }; + pinctrl_pciea: pcieagrp { + fsl,pins = < + IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_pciea_reg: pcieareggrp { + fsl,pins = < + IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000021 + >; + }; + + pinctrl_pcieb: pciebgrp { + fsl,pins = < + IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021 + IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 + IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 + >; + }; + pinctrl_pwm_lvds0: pwmlvds0grp { fsl,pins = < IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020