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[88.29.191.45]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86a0afc1sm1338845e9.1.2024.10.03.16.42.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:42:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 01/16] qemu/bswap: Undefine CPU_CONVERT() once done Date: Fri, 4 Oct 2024 01:41:56 +0200 Message-ID: <20241003234211.53644-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Better undefined macros once we are done with them, like we do few lines later with DO_STN_LDN_P(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- include/qemu/bswap.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index ad22910a5d1..b915835bead 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -140,6 +140,8 @@ CPU_CONVERT(le, 16, uint16_t) CPU_CONVERT(le, 32, uint32_t) CPU_CONVERT(le, 64, uint64_t) +#undef CPU_CONVERT + /* * Same as cpu_to_le{16,32,64}, except that gcc will figure the result is * a compile-time constant if you pass in a constant. So this can be From patchwork Thu Oct 3 23:41:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13821659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EE81CF34D8 for ; Thu, 3 Oct 2024 23:43:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swVSx-0007Mt-Vr; Thu, 03 Oct 2024 19:42:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swVSv-0007ME-Ln for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:42:37 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swVSt-0003Sw-8y for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:42:37 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-42cbbb1727eso15203235e9.2 for ; Thu, 03 Oct 2024 16:42:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727998953; x=1728603753; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TcCRLsqYRrcM/7jknEY1pNA2GOIFR+Tysnifvuzq9yg=; b=VLZS/p4b3cPVk1SpmpLXfm0vR+hMLyvQbQngtYb7kghcFN3fcbceDorfgSJmmHHR/v 8fIKfLhEOn3+oNq8m3KOCOBdqO0Zq2o5hwAjmKLHVWOWOoOQ0FscgV2Z7tps+NV6fBH3 X4wrNEhWMou6guvJk/+XLV0cOTn7DbSebtikPJ/O2ZvkbQbkXwDhTKUeIo7raLOevXxK 5J0q+FbbXsQB2dFw4gjuOU20sHiP2+uOd6jFzw8bvH8+997HZ1R9l+Of3AXVd1ji22m5 /SnGSegNwz748lD3cCD/cjexaL8jWl0LRn6JU9vaKjBrf1+VYffQXmeeuG8K83VuhbMs Z/kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727998953; x=1728603753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TcCRLsqYRrcM/7jknEY1pNA2GOIFR+Tysnifvuzq9yg=; b=TIeAAL92Y36oXygk++cyTLVCmX3wjFdoXCIngUVy+FVDHsmmPFWgra6GZ24duxRP3m 3UZQgyjSQO5wxOr0iV/3w0QqebC0dCEO76VDwe3gZWTVmWg1qr/CmqQ9lmINt1OOzYSz yD8k0kgkxXWc6oVDqrHMe+2ayF0ji4JmM/4tv1WLMLA3IHQ7HE+iyfSQt+P+2vHGLMKF 5KeKsSAM24yDoHV4NmcqzB3kcvFEQ0k9U8XZ5/791+qmWf/m/VduqSk36IjGs7B0ELqT vaGiCN5nZ+1nS0whWd99xCmGLDJnoANZQSB24Nn+CWMpdaBtfWc4xP1+Pa7u12hB5/cO w5hw== X-Gm-Message-State: AOJu0YynOa2hovdLcJdKqjQW0xHsvG0CihLhOozO6YfnmfOznOWSJJVh +vJlJp7VW9TItdPGYP5uu0FiUVGDkID6D45ocxxAxJZhFCUNXVMSDA1lVeD6jJnnP95yHY4GDNn t+QQ= X-Google-Smtp-Source: AGHT+IFAX5JsfYFznjj6kznenaTo+F69obC9mIHSdm+s6fhWvEVRA+aYLlo8UcVg7quHOQXqgCCcgw== X-Received: by 2002:a5d:5048:0:b0:37c:d49c:3ac7 with SMTP id ffacd0b85a97d-37d0e8f4b9fmr555862f8f.48.1727998953470; Thu, 03 Oct 2024 16:42:33 -0700 (PDT) Received: from localhost.localdomain (45.red-88-29-191.dynamicip.rima-tde.net. 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Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 02/16] exec/memop: Remove unused memop_big_endian() helper Date: Fri, 4 Oct 2024 01:41:57 +0200 Message-ID: <20241003234211.53644-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Last use of memop_big_endian() was removed in commit 592134617c9 ("accel/tcg: Reorg system mode store helpers"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- include/exec/memop.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index f881fe7af4e..899ea0a2aae 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -164,10 +164,4 @@ static inline MemOp size_memop(unsigned size) return (MemOp)ctz32(size); } -/* Big endianness from MemOp. */ -static inline bool memop_big_endian(MemOp op) -{ - return (op & MO_BSWAP) == MO_BE; -} - #endif From patchwork Thu Oct 3 23:41:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13821662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1CB6CF34D6 for ; Thu, 3 Oct 2024 23:44:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swVT7-0007R6-5C; Thu, 03 Oct 2024 19:42:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swVT3-0007PV-EK for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:42:45 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swVT1-0003Xc-VK for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:42:45 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-42cbc22e1c4so12169225e9.2 for ; Thu, 03 Oct 2024 16:42:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727998962; x=1728603762; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A2b2LwHBDDNlQ4lpraog9QbauHHDsoDaj9FTLQzChw4=; b=Dv6K9vlHkdK0ZrufRyplTCH1bPArT/8GdAbHw5Xr7QwQqTAzTF7ObyfqtnbQF5FS8W dk1NlJouizbAl/AuU1TTSjYZJu/3cHCxReWxyGspBlR6p8YwmJhzD3U8sZSSalT0WJXK xphsrmmdY5Fdj1V1mMpR/4xZVZTBb06hFrEYwzF+HNzceqM4FJacKToZ3PytVr4WtY3c F0UKU/KhrkmSgo+T2xPBWQl7G4IZF7D185mV8dp8Z+WWG68WzHCgvG58SXSRfTvibawk BmDxTYKEkO8S1yWkb0JY4I6bzJ7RuhvGuF6/nRFrRTL19DnT2r6irP/jWJLnZfai/+v2 Myig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727998962; x=1728603762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A2b2LwHBDDNlQ4lpraog9QbauHHDsoDaj9FTLQzChw4=; b=rK7BCS64L9tG+1xGMq72N0KSPzUvdksbKwqlMhzQED6Tj2JePdpZUUyKl5UNzlDF/1 5gpHOfqMuTinSkoQQAS+8O+wphVD7PQLRb3Z6BnDoqs1iRiQlKyhToArpVmOxNMI5M9t 1163O0UgqcfGbbXvopoidstk7GN53r1lmg9Y4pTlOLKzNb3JnjpApAZy3torCacwjTbD UxURDWPH4EaKB1VYTfB4zM7JQUyJDbfdLIKZduPX59IsC1w/p+Ra3QwpMXMK8fRap+mD htaQrD6gIuXODB+H2BMAASyi2WBrroAalC0Q7PQdRf8uR6VqPrbrnkIqb1iiNOniI5il Y+BQ== X-Gm-Message-State: AOJu0YxZpz80fkPrW0OkwhQfAKqxtVpWwm2mFADRFS3bAJqvg0MPlJm2 6K7pvAbf4HGXiMaixdHpPRKWNdRsTbD4klDX4kFTe3euZiNltF1M7JvlLV47gn3/xeufwKk+J3p oIPM= X-Google-Smtp-Source: AGHT+IFUhQSBkMnwy2l0lFzF+iJGccfusHlORuoJfYCEHpm//0iz8GifaG1pW6FqC7DwbSM5AG2H1w== X-Received: by 2002:adf:fe8a:0:b0:37c:ccfc:92c0 with SMTP id ffacd0b85a97d-37d0eb1b83emr472244f8f.57.1727998962052; Thu, 03 Oct 2024 16:42:42 -0700 (PDT) Received: from localhost.localdomain (45.red-88-29-191.dynamicip.rima-tde.net. [88.29.191.45]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d07fde1fesm2201806f8f.0.2024.10.03.16.42.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:42:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 03/16] linux-user/i386: Use explicit little-endian LD/ST API Date: Fri, 4 Oct 2024 01:41:58 +0200 Message-ID: <20241003234211.53644-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- linux-user/i386/signal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index cb90711834f..0f11dba831f 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -754,8 +754,8 @@ static bool restore_sigcontext(CPUX86State *env, struct target_sigcontext *sc) env->eip = tswapl(sc->rip); #endif - cpu_x86_load_seg(env, R_CS, lduw_p(&sc->cs) | 3); - cpu_x86_load_seg(env, R_SS, lduw_p(&sc->ss) | 3); + cpu_x86_load_seg(env, R_CS, lduw_le_p(&sc->cs) | 3); + cpu_x86_load_seg(env, R_SS, lduw_le_p(&sc->ss) | 3); tmpflags = tswapl(sc->eflags); env->eflags = (env->eflags & ~0x40DD5) | (tmpflags & 0x40DD5); From patchwork Thu Oct 3 23:41:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13821661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39458CF34D5 for ; Thu, 3 Oct 2024 23:43:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swVTH-0007Zl-Sl; Thu, 03 Oct 2024 19:42:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swVTD-0007WI-9F for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:42:57 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swVTA-0003cn-5D for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:42:55 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-42cae102702so12306345e9.0 for ; Thu, 03 Oct 2024 16:42:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727998970; x=1728603770; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=660tqqXa5tibARPW9AYEAAZGQpIeIe3jt8UfaadrvBw=; b=XM+BqOW/ecMbnyGoCJNk7wY6qh6mhMJJhX+MyS/q0xBCLKmPpotVapi8zHBpBI+3La vE4GHM+GvO2ppJCQz1CVbKhKGzyrzlDj9ejnyMYOv7eAaIu+fIQtWiAIaV+27ru6T6Eg VzES0FWNIJGPAjjmb37/iw0DcgkEIo0S2L+rLraRGiZm9qrdl3w0/SWa14kk33eT0P/T Mu7eOgou95QT6zXPePb9LvNXIiY7O4ZaXE3UIB7enMMlv5800v+q4O2xHKu63s7v6p5P qOfXrJTZE72fwbbUnGzjXtggGM3odpSWSX6Dg3LOVNbJJW7lIMZibnfVHKMAOj66+Y9G hoMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727998970; x=1728603770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=660tqqXa5tibARPW9AYEAAZGQpIeIe3jt8UfaadrvBw=; b=A9cHKcfE3hBhxGfO5T/YpYk4wB1nXt6rhvDsPm/S93SlGmDeUNHXzIQcMT/Us++YpA /oGJZbIYZI7sPf6Y7d+4N4eFQrkwK5VAkS5W/XrEbMiO6tXjHhohzGM3+5Kw7dFTWx38 DnyLQGYxXSI0MCgHrNUnZRtQYoH8OirUYRwWZJGISw2/CGX/w6spKC3+vR4TLDaKXGuz kVf6xTYzMgdzWRjooUFoTKUxI0YK1S2AvuNMfT0KjZZSiGoPf4iChMPAcAm/adUMLWLt 9yd8al5lmtooAT5ZLKrHt14jECz+sAq3C7UOvni1ICNomQMHjsBPwJU8yBazHTPQq/kD KCIg== X-Gm-Message-State: AOJu0YzsPVQXYXmd9jYJzZjH1RYcyXpL5NWeWSXxHwyTGkyLGQt0GP6H jnRSHtMQSEDJrEI+9WcWQElNuZAg0z0l82jZ3LVO8KCts7pwiBVY/SgasUnUdhk53cCVR94PHAZ e//M= X-Google-Smtp-Source: AGHT+IHo9sePMa2N5NN4I6NNQXgzlh26D+snxVOI/qqhCJDUMzz2LtBPncDtoeC2idC56XydTVoZRQ== X-Received: by 2002:a05:600c:1907:b0:426:6326:4cec with SMTP id 5b1f17b1804b1-42f85af412bmr3516735e9.29.1727998969948; Thu, 03 Oct 2024 16:42:49 -0700 (PDT) Received: from localhost.localdomain (45.red-88-29-191.dynamicip.rima-tde.net. [88.29.191.45]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86b444f1sm1230055e9.38.2024.10.03.16.42.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:42:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 04/16] hw/i386: Use explicit little-endian LD/ST API Date: Fri, 4 Oct 2024 01:41:59 +0200 Message-ID: <20241003234211.53644-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/multiboot.c | 36 ++++++++++++++++++------------------ hw/i386/x86-common.c | 26 +++++++++++++------------- 2 files changed, 31 insertions(+), 31 deletions(-) diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index 3332712ab35..ba4ead5270c 100644 --- a/hw/i386/multiboot.c +++ b/hw/i386/multiboot.c @@ -133,9 +133,9 @@ static void mb_add_mod(MultibootState *s, p = (char *)s->mb_buf + s->offset_mbinfo + MB_MOD_SIZE * s->mb_mods_count; - stl_p(p + MB_MOD_START, start); - stl_p(p + MB_MOD_END, end); - stl_p(p + MB_MOD_CMDLINE, cmdline_phys); + stl_le_p(p + MB_MOD_START, start); + stl_le_p(p + MB_MOD_END, end); + stl_le_p(p + MB_MOD_CMDLINE, cmdline_phys); mb_debug("mod%02d: "HWADDR_FMT_plx" - "HWADDR_FMT_plx, s->mb_mods_count, start, end); @@ -168,9 +168,9 @@ int load_multiboot(X86MachineState *x86ms, /* Ok, let's see if it is a multiboot image. The header is 12x32bit long, so the latest entry may be 8192 - 48. */ for (i = 0; i < (8192 - 48); i += 4) { - if (ldl_p(header+i) == 0x1BADB002) { - uint32_t checksum = ldl_p(header+i+8); - flags = ldl_p(header+i+4); + if (ldl_le_p(header+i) == 0x1BADB002) { + uint32_t checksum = ldl_le_p(header+i+8); + flags = ldl_le_p(header+i+4); checksum += flags; checksum += (uint32_t)0x1BADB002; if (!checksum) { @@ -223,11 +223,11 @@ int load_multiboot(X86MachineState *x86ms, mb_kernel_size, (size_t)mh_entry_addr); } else { /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */ - uint32_t mh_header_addr = ldl_p(header+i+12); - uint32_t mh_load_end_addr = ldl_p(header+i+20); - uint32_t mh_bss_end_addr = ldl_p(header+i+24); + uint32_t mh_header_addr = ldl_le_p(header+i+12); + uint32_t mh_load_end_addr = ldl_le_p(header+i+20); + uint32_t mh_bss_end_addr = ldl_le_p(header+i+24); - mh_load_addr = ldl_p(header+i+16); + mh_load_addr = ldl_le_p(header+i+16); if (mh_header_addr < mh_load_addr) { error_report("invalid load_addr address"); exit(1); @@ -239,7 +239,7 @@ int load_multiboot(X86MachineState *x86ms, uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr); uint32_t mb_load_size = 0; - mh_entry_addr = ldl_p(header+i+28); + mh_entry_addr = ldl_le_p(header+i+28); if (mh_load_end_addr) { if (mh_load_end_addr < mh_load_addr) { @@ -364,22 +364,22 @@ int load_multiboot(X86MachineState *x86ms, /* Commandline support */ kcmdline = g_strdup_printf("%s %s", kernel_filename, kernel_cmdline); - stl_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline)); + stl_le_p(bootinfo + MBI_CMDLINE, mb_add_cmdline(&mbs, kcmdline)); - stl_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs, bootloader_name)); + stl_le_p(bootinfo + MBI_BOOTLOADER, mb_add_bootloader(&mbs, bootloader_name)); - stl_p(bootinfo + MBI_MODS_ADDR, mbs.mb_buf_phys + mbs.offset_mbinfo); - stl_p(bootinfo + MBI_MODS_COUNT, mbs.mb_mods_count); /* mods_count */ + stl_le_p(bootinfo + MBI_MODS_ADDR, mbs.mb_buf_phys + mbs.offset_mbinfo); + stl_le_p(bootinfo + MBI_MODS_COUNT, mbs.mb_mods_count); /* mods_count */ /* the kernel is where we want it to be now */ - stl_p(bootinfo + MBI_FLAGS, MULTIBOOT_FLAGS_MEMORY + stl_le_p(bootinfo + MBI_FLAGS, MULTIBOOT_FLAGS_MEMORY | MULTIBOOT_FLAGS_BOOT_DEVICE | MULTIBOOT_FLAGS_CMDLINE | MULTIBOOT_FLAGS_MODULES | MULTIBOOT_FLAGS_MMAP | MULTIBOOT_FLAGS_BOOTLOADER); - stl_p(bootinfo + MBI_BOOT_DEVICE, 0x8000ffff); /* XXX: use the -boot switch? */ - stl_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP); + stl_le_p(bootinfo + MBI_BOOT_DEVICE, 0x8000ffff); /* XXX: use the -boot switch? */ + stl_le_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP); mb_debug("multiboot: entry_addr = %#x", mh_entry_addr); mb_debug(" mb_buf_phys = "HWADDR_FMT_plx, mbs.mb_buf_phys); diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 992ea1f25e9..daa6a5d500c 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -586,7 +586,7 @@ static bool load_elfboot(const char *kernel_filename, uint64_t elf_low, elf_high; int kernel_size; - if (ldl_p(header) != 0x464c457f) { + if (ldl_le_p(header) != 0x464c457f) { return false; /* no elfboot */ } @@ -669,8 +669,8 @@ void x86_load_linux(X86MachineState *x86ms, * kernel protocol version. * Please see https://www.kernel.org/doc/Documentation/x86/boot.txt */ - if (ldl_p(header + 0x202) == 0x53726448) /* Magic signature "HdrS" */ { - protocol = lduw_p(header + 0x206); + if (ldl_le_p(header + 0x202) == 0x53726448) /* Magic signature "HdrS" */ { + protocol = lduw_be_p(header + 0x206); } else { /* * This could be a multiboot kernel. If it is, let's stop treating it @@ -762,7 +762,7 @@ void x86_load_linux(X86MachineState *x86ms, /* highest address for loading the initrd */ if (protocol >= 0x20c && - lduw_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { + lduw_be_p(header + 0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { /* * Linux has supported initrd up to 4 GB for a very long time (2007, * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), @@ -781,7 +781,7 @@ void x86_load_linux(X86MachineState *x86ms, */ initrd_max = UINT32_MAX; } else if (protocol >= 0x203) { - initrd_max = ldl_p(header + 0x22c); + initrd_max = ldl_le_p(header + 0x22c); } else { initrd_max = 0x37ffffff; } @@ -797,10 +797,10 @@ void x86_load_linux(X86MachineState *x86ms, sev_load_ctx.cmdline_size = strlen(kernel_cmdline) + 1; if (protocol >= 0x202) { - stl_p(header + 0x228, cmdline_addr); + stl_le_p(header + 0x228, cmdline_addr); } else { - stw_p(header + 0x20, 0xA33F); - stw_p(header + 0x22, cmdline_addr - real_addr); + stw_le_p(header + 0x20, 0xA33F); + stw_le_p(header + 0x22, cmdline_addr - real_addr); } /* handle vga= parameter */ @@ -824,7 +824,7 @@ void x86_load_linux(X86MachineState *x86ms, exit(1); } } - stw_p(header + 0x1fa, video_mode); + stw_le_p(header + 0x1fa, video_mode); } /* loader type */ @@ -839,7 +839,7 @@ void x86_load_linux(X86MachineState *x86ms, /* heap */ if (protocol >= 0x201) { header[0x211] |= 0x80; /* CAN_USE_HEAP */ - stw_p(header + 0x224, cmdline_addr - real_addr - 0x200); + stw_le_p(header + 0x224, cmdline_addr - real_addr - 0x200); } /* load initrd */ @@ -879,8 +879,8 @@ void x86_load_linux(X86MachineState *x86ms, sev_load_ctx.initrd_data = initrd_data; sev_load_ctx.initrd_size = initrd_size; - stl_p(header + 0x218, initrd_addr); - stl_p(header + 0x21c, initrd_size); + stl_le_p(header + 0x218, initrd_addr); + stl_le_p(header + 0x21c, initrd_size); } /* load kernel and setup */ @@ -926,7 +926,7 @@ void x86_load_linux(X86MachineState *x86ms, kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; kernel = g_realloc(kernel, kernel_size); - stq_p(header + 0x250, prot_addr + setup_data_offset); + stq_le_p(header + 0x250, prot_addr + setup_data_offset); setup_data = (struct setup_data *)(kernel + setup_data_offset); setup_data->next = 0; From patchwork Thu Oct 3 23:42:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13821671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B93A7CF34D5 for ; Thu, 3 Oct 2024 23:44:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swVTO-0007cp-SW; Thu, 03 Oct 2024 19:43:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swVTL-0007bl-Uo for qemu-devel@nongnu.org; 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[88.29.191.45]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86b1d930sm1307955e9.22.2024.10.03.16.42.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:42:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 05/16] target/i386: Use explicit little-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:00 +0200 Message-ID: <20241003234211.53644-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/gdbstub.c | 26 +++++++++++----------- target/i386/tcg/sysemu/excp_helper.c | 4 ++-- target/i386/xsave_helper.c | 32 ++++++++++++++-------------- 3 files changed, 31 insertions(+), 31 deletions(-) diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 4acf485879e..40c8cb6dc46 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -89,10 +89,10 @@ static int gdb_read_reg_cs64(uint32_t hflags, GByteArray *buf, target_ulong val) static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val) { if (hflags & HF_CS64_MASK) { - *val = ldq_p(buf); + *val = ldq_le_p(buf); return 8; } - *val = ldl_p(buf); + *val = ldl_le_p(buf); return 4; } @@ -221,7 +221,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf) { CPUX86State *env = &cpu->env; - uint16_t selector = ldl_p(mem_buf); + uint16_t selector = ldl_le_p(mem_buf); if (selector != env->segs[sreg].selector) { #if defined(CONFIG_USER_ONLY) @@ -270,7 +270,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } else if (n < CPU_NB_REGS32) { n = gpr_map32[n]; env->regs[n] &= ~0xffffffffUL; - env->regs[n] |= (uint32_t)ldl_p(mem_buf); + env->regs[n] |= (uint32_t)ldl_le_p(mem_buf); return 4; } } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { @@ -281,8 +281,8 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { n -= IDX_XMM_REGS; if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) { - env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf); - env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8); + env->xmm_regs[n].ZMM_Q(0) = ldq_le_p(mem_buf); + env->xmm_regs[n].ZMM_Q(1) = ldq_le_p(mem_buf + 8); return 16; } } else { @@ -290,18 +290,18 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) case IDX_IP_REG: if (TARGET_LONG_BITS == 64) { if (env->hflags & HF_CS64_MASK) { - env->eip = ldq_p(mem_buf); + env->eip = ldq_le_p(mem_buf); } else { - env->eip = ldq_p(mem_buf) & 0xffffffffUL; + env->eip = ldq_le_p(mem_buf) & 0xffffffffUL; } return 8; } else { env->eip &= ~0xffffffffUL; - env->eip |= (uint32_t)ldl_p(mem_buf); + env->eip |= (uint32_t)ldl_le_p(mem_buf); return 4; } case IDX_FLAGS_REG: - env->eflags = ldl_p(mem_buf); + env->eflags = ldl_le_p(mem_buf); return 4; case IDX_SEG_REGS: @@ -327,10 +327,10 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 4; case IDX_FP_REGS + 8: - cpu_set_fpuc(env, ldl_p(mem_buf)); + cpu_set_fpuc(env, ldl_le_p(mem_buf)); return 4; case IDX_FP_REGS + 9: - tmp = ldl_p(mem_buf); + tmp = ldl_le_p(mem_buf); env->fpstt = (tmp >> 11) & 7; env->fpus = tmp & ~0x3800; return 4; @@ -348,7 +348,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 4; case IDX_MXCSR_REG: - cpu_set_mxcsr(env, ldl_p(mem_buf)); + cpu_set_mxcsr(env, ldl_le_p(mem_buf)); return 4; case IDX_CTL_CR0_REG: diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index 8fb05b1f531..de6765099f3 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -86,7 +86,7 @@ static bool ptw_translate(PTETranslate *inout, hwaddr addr, uint64_t ra) static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra) { if (likely(in->haddr)) { - return ldl_p(in->haddr); + return ldl_le_p(in->haddr); } return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } @@ -94,7 +94,7 @@ static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra) static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra) { if (likely(in->haddr)) { - return ldq_p(in->haddr); + return ldq_le_p(in->haddr); } return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index 996e9f3bfef..fc10bfa6718 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -43,8 +43,8 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) for (i = 0; i < CPU_NB_REGS; i++) { uint8_t *xmm = legacy->xmm_regs[i]; - stq_p(xmm, env->xmm_regs[i].ZMM_Q(0)); - stq_p(xmm + 8, env->xmm_regs[i].ZMM_Q(1)); + stq_le_p(xmm, env->xmm_regs[i].ZMM_Q(0)); + stq_le_p(xmm + 8, env->xmm_regs[i].ZMM_Q(1)); } header->xstate_bv = env->xstate_bv; @@ -58,8 +58,8 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) for (i = 0; i < CPU_NB_REGS; i++) { uint8_t *ymmh = avx->ymmh[i]; - stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2)); - stq_p(ymmh + 8, env->xmm_regs[i].ZMM_Q(3)); + stq_le_p(ymmh, env->xmm_regs[i].ZMM_Q(2)); + stq_le_p(ymmh + 8, env->xmm_regs[i].ZMM_Q(3)); } } @@ -101,10 +101,10 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) for (i = 0; i < CPU_NB_REGS; i++) { uint8_t *zmmh = zmm_hi256->zmm_hi256[i]; - stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4)); - stq_p(zmmh + 8, env->xmm_regs[i].ZMM_Q(5)); - stq_p(zmmh + 16, env->xmm_regs[i].ZMM_Q(6)); - stq_p(zmmh + 24, env->xmm_regs[i].ZMM_Q(7)); + stq_le_p(zmmh, env->xmm_regs[i].ZMM_Q(4)); + stq_le_p(zmmh + 8, env->xmm_regs[i].ZMM_Q(5)); + stq_le_p(zmmh + 16, env->xmm_regs[i].ZMM_Q(6)); + stq_le_p(zmmh + 24, env->xmm_regs[i].ZMM_Q(7)); } #ifdef TARGET_X86_64 @@ -177,8 +177,8 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen) for (i = 0; i < CPU_NB_REGS; i++) { const uint8_t *xmm = legacy->xmm_regs[i]; - env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm); - env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm + 8); + env->xmm_regs[i].ZMM_Q(0) = ldq_le_p(xmm); + env->xmm_regs[i].ZMM_Q(1) = ldq_le_p(xmm + 8); } env->xstate_bv = header->xstate_bv; @@ -191,8 +191,8 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen) for (i = 0; i < CPU_NB_REGS; i++) { const uint8_t *ymmh = avx->ymmh[i]; - env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh); - env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh + 8); + env->xmm_regs[i].ZMM_Q(2) = ldq_le_p(ymmh); + env->xmm_regs[i].ZMM_Q(3) = ldq_le_p(ymmh + 8); } } @@ -241,10 +241,10 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen) for (i = 0; i < CPU_NB_REGS; i++) { const uint8_t *zmmh = zmm_hi256->zmm_hi256[i]; - env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh); - env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh + 8); - env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh + 16); - env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh + 24); + env->xmm_regs[i].ZMM_Q(4) = ldq_le_p(zmmh); + env->xmm_regs[i].ZMM_Q(5) = ldq_le_p(zmmh + 8); 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[88.29.191.45]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86a20537sm1340495e9.15.2024.10.03.16.43.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:43:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 06/16] hw/m68k: Use explicit big-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:01 +0200 Message-ID: <20241003234211.53644-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The M68K architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- hw/m68k/bootinfo.h | 28 ++++++++++++++-------------- hw/m68k/mcf5208.c | 2 +- hw/m68k/next-cube.c | 2 +- hw/m68k/q800.c | 4 ++-- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/m68k/bootinfo.h b/hw/m68k/bootinfo.h index 70c1dc0e8c3..0b3e7c4ea01 100644 --- a/hw/m68k/bootinfo.h +++ b/hw/m68k/bootinfo.h @@ -14,39 +14,39 @@ #define BOOTINFO0(base, id) \ do { \ - stw_p(base, id); \ + stw_be_p(base, id); \ base += 2; \ - stw_p(base, sizeof(struct bi_record)); \ + stw_be_p(base, sizeof(struct bi_record)); \ base += 2; \ } while (0) #define BOOTINFO1(base, id, value) \ do { \ - stw_p(base, id); \ + stw_be_p(base, id); \ base += 2; \ - stw_p(base, sizeof(struct bi_record) + 4); \ + stw_be_p(base, sizeof(struct bi_record) + 4); \ base += 2; \ - stl_p(base, value); \ + stl_be_p(base, value); \ base += 4; \ } while (0) #define BOOTINFO2(base, id, value1, value2) \ do { \ - stw_p(base, id); \ + stw_be_p(base, id); \ base += 2; \ - stw_p(base, sizeof(struct bi_record) + 8); \ + stw_be_p(base, sizeof(struct bi_record) + 8); \ base += 2; \ - stl_p(base, value1); \ + stl_be_p(base, value1); \ base += 4; \ - stl_p(base, value2); \ + stl_be_p(base, value2); \ base += 4; \ } while (0) #define BOOTINFOSTR(base, id, string) \ do { \ - stw_p(base, id); \ + stw_be_p(base, id); \ base += 2; \ - stw_p(base, \ + stw_be_p(base, \ (sizeof(struct bi_record) + strlen(string) + \ 1 /* null termination */ + 3 /* padding */) & ~3); \ base += 2; \ @@ -59,13 +59,13 @@ #define BOOTINFODATA(base, id, data, len) \ do { \ - stw_p(base, id); \ + stw_be_p(base, id); \ base += 2; \ - stw_p(base, \ + stw_be_p(base, \ (sizeof(struct bi_record) + len + \ 2 /* length field */ + 3 /* padding */) & ~3); \ base += 2; \ - stw_p(base, len); \ + stw_be_p(base, len); \ base += 2; \ for (unsigned i_ = 0; i_ < len; ++i_) { \ stb_p(base++, data[i_]); \ diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index b6677ad6bc3..e37cd50d189 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -359,7 +359,7 @@ static void mcf5208evb_init(MachineState *machine) /* Initial PC is always at offset 4 in firmware binaries */ ptr = rom_ptr(0x4, 4); assert(ptr != NULL); - env->pc = ldl_p(ptr); + env->pc = ldl_be_p(ptr); } /* Load kernel. */ diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 9b78767ea8e..9832213e7ec 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -1036,7 +1036,7 @@ static void next_cube_init(MachineState *machine) /* Initial PC is always at offset 4 in firmware binaries */ ptr = rom_ptr(0x01000004, 4); g_assert(ptr != NULL); - env->pc = ldl_p(ptr); + env->pc = ldl_be_p(ptr); if (env->pc >= 0x01020000) { error_report("'%s' does not seem to be a valid firmware image.", bios_name); diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index fa7683bf76f..556604e1dcf 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -684,9 +684,9 @@ static void q800_machine_init(MachineState *machine) ptr = rom_ptr(MACROM_ADDR, bios_size); assert(ptr != NULL); - stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */ + stl_phys(cs->as, 0, ldl_be_p(ptr)); /* reset initial SP */ stl_phys(cs->as, 4, - MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */ + MACROM_ADDR + ldl_be_p(ptr + 4)); /* reset initial PC */ } } } From patchwork Thu Oct 3 23:42:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13821669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2C08CF34D5 for ; Thu, 3 Oct 2024 23:44:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swVTr-0007wt-JY; Thu, 03 Oct 2024 19:43:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swVTZ-0007hm-K8 for qemu-devel@nongnu.org; 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Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 07/16] target/m68k: Use explicit big-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:02 +0200 Message-ID: <20241003234211.53644-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The M68K architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- target/m68k/gdbstub.c | 2 +- target/m68k/helper.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c index 15547e2313c..136159f98f2 100644 --- a/target/m68k/gdbstub.c +++ b/target/m68k/gdbstub.c @@ -52,7 +52,7 @@ int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) CPUM68KState *env = cpu_env(cs); uint32_t tmp; - tmp = ldl_p(mem_buf); + tmp = ldl_be_p(mem_buf); if (n < 8) { /* D0-D7 */ diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 4c85badd5d3..9d3db8419de 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -57,15 +57,15 @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) if (n < 8) { float_status s; - env->fregs[n].d = float64_to_floatx80(ldq_p(mem_buf), &s); + env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); return 8; } switch (n) { case 8: /* fpcontrol */ - cpu_m68k_set_fpcr(env, ldl_p(mem_buf)); + cpu_m68k_set_fpcr(env, ldl_be_p(mem_buf)); return 4; case 9: /* fpstatus */ - env->fpsr = ldl_p(mem_buf); + env->fpsr = ldl_be_p(mem_buf); return 4; case 10: /* fpiar, not implemented */ return 4; @@ -107,10 +107,10 @@ static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) } switch (n) { case 8: /* fpcontrol */ - cpu_m68k_set_fpcr(env, ldl_p(mem_buf)); + cpu_m68k_set_fpcr(env, ldl_be_p(mem_buf)); return 4; case 9: /* fpstatus */ - cpu_m68k_set_fpsr(env, ldl_p(mem_buf)); + cpu_m68k_set_fpsr(env, ldl_be_p(mem_buf)); return 4; case 10: /* fpiar, not implemented */ return 4; From patchwork Thu Oct 3 23:42:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13821668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1695CF34D7 for ; Thu, 3 Oct 2024 23:44:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swVU0-0008Fi-Vm; Thu, 03 Oct 2024 19:43:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swVTi-0007uG-CZ for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:43:28 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swVTe-0003qG-N2 for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:43:25 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-42cbc38a997so9273055e9.1 for ; Thu, 03 Oct 2024 16:43:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727999000; x=1728603800; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IdTDYhDUNRanYUWv5agjrp+BpprZZ5LHmcMTx/9wIGM=; b=Z9mCg5z4XKEzlJdLQqqhhgOk41yfJHcrkgw9sVzLczW/FX41Qcm5EOJpwiFOVCoSz/ iJ36tUPKR4iBmj2Z5mVUoBWy+Y1cLijwCNItpT5m4XSp2Ak0aSJFNXFkndnpOCgofJuG 202hFZ2gk5R9Vif2+aEKCJ0m4H1yWMvv+hmjBz+klW6Gg3fuoEhb0FnxEVgEu0GwnZxp ULCzrT22jVO1xLmdYTkzcA9MaMkyPiXUgFr0JiLaKQIlgFBVt/SRY8BNy7mIOGMe4pbV WKG8blVTCEWkODdXDoCXbWEOXJ9fVlYEQjId9i1azaQzWRyj3NCcu/G8+B+q1DctGN0S O3ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727999000; x=1728603800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IdTDYhDUNRanYUWv5agjrp+BpprZZ5LHmcMTx/9wIGM=; b=HaRtx6ElAUFWkjHMr9N0MPwHSOKAVoi4WBTbujI5SgfGXLBC0a1zQKdW9oVhvRPgMF +XfoSF9KUKNN5RiveFGRP0dPUa2m23IdnuWi6qfpgVaLc34PifupvA6239peEiqtLTw+ 7FZRr1E+TtUKwNgLyX0n3tN0PdS9JxyOfIw7rmcJzTPvocZtpOPP59lBShKtGDQpKRUl kHWYM5j61to3mcrB1PsBnbhLc1P/Bnj9Wt04adp5qLa4UsvmoZ2ps+VY+wbBijmrck16 Tsi4jGUEKvydapG+P6laXsDNO6a+dBjU4+oFnC/3wVKApCDEYy4RgIuwypewPL5NOO/q RURg== X-Gm-Message-State: AOJu0YzcvlrlUIpAl9A+i+kOC8UKtpOssBdkUAECpvbhvTbs53P9ADe3 lTdCCUbTkHAWY9+bDUCJ2yz8qctbN7kgFzj+CK2zzxznria5UVMzGq626l0Gy5gVB0kaUraQwVM c2no= X-Google-Smtp-Source: AGHT+IFtrsfD2y4Xoskbuwa2GkreRIJVr4sIYvSzKdKxXWgeQsBR88xjo4iMkIkTxTX9Pj3Jl4KLxw== X-Received: by 2002:a05:600c:4447:b0:42c:b67b:816b with SMTP id 5b1f17b1804b1-42f7df115d3mr31111865e9.1.1727999000451; Thu, 03 Oct 2024 16:43:20 -0700 (PDT) Received: from localhost.localdomain (45.red-88-29-191.dynamicip.rima-tde.net. [88.29.191.45]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86b3951fsm1262715e9.41.2024.10.03.16.43.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:43:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 08/16] hw/ppc/e500: Use explicit big-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:03 +0200 Message-ID: <20241003234211.53644-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The 32-bit PPC architecture uses big endianness. Directly use the big-endian LD/ST API for the E500 hardware. Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/ppce500_spin.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index e08739a443d..8e0ef9467e4 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -64,9 +64,9 @@ static void spin_reset(DeviceState *dev) for (i = 0; i < MAX_CPUS; i++) { SpinInfo *info = &s->spin[i]; - stl_p(&info->pir, i); - stq_p(&info->r3, i); - stq_p(&info->addr, 1); + stl_be_p(&info->pir, i); + stq_be_p(&info->r3, i); + stq_be_p(&info->addr, 1); } } @@ -96,9 +96,9 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data) hwaddr map_start; cpu_synchronize_state(cs); - stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]); - env->nip = ldq_p(&curspin->addr) & (map_size - 1); - env->gpr[3] = ldq_p(&curspin->r3); + stl_be_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]); + env->nip = ldq_be_p(&curspin->addr) & (map_size - 1); + env->gpr[3] = ldq_be_p(&curspin->r3); env->gpr[4] = 0; env->gpr[5] = 0; env->gpr[6] = 0; @@ -106,7 +106,7 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data) env->gpr[8] = 0; env->gpr[9] = 0; - map_start = ldq_p(&curspin->addr) & ~(map_size - 1); + map_start = ldq_be_p(&curspin->addr) & ~(map_size - 1); mmubooke_create_initial_mapping(env, 0, map_start, map_size); cs->halted = 0; @@ -141,14 +141,14 @@ static void spin_write(void *opaque, hwaddr addr, uint64_t value, stb_p(curspin_p, value); break; case 2: - stw_p(curspin_p, value); + stw_be_p(curspin_p, value); break; case 4: - stl_p(curspin_p, value); + stl_be_p(curspin_p, value); break; } - if (!(ldq_p(&curspin->addr) & 1)) { + if (!(ldq_be_p(&curspin->addr) & 1)) { /* run CPU */ run_on_cpu(cpu, spin_kick, RUN_ON_CPU_HOST_PTR(curspin)); } @@ -163,9 +163,9 @@ static uint64_t spin_read(void *opaque, hwaddr addr, unsigned len) case 1: return ldub_p(spin_p); case 2: - return lduw_p(spin_p); + return lduw_be_p(spin_p); case 4: - return ldl_p(spin_p); + return ldl_be_p(spin_p); default: hw_error("ppce500: unexpected %s with len = %u", __func__, len); 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[88.29.191.45]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082e6de8sm2161115f8f.114.2024.10.03.16.43.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:43:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 09/16] hw/s390x: Use explicit big-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:04 +0200 Message-ID: <20241003234211.53644-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The S390 architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- hw/s390x/ipl.c | 4 +- hw/s390x/s390-pci-inst.c | 166 +++++++++++++++++++-------------------- 2 files changed, 85 insertions(+), 85 deletions(-) diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index dd71689642b..5ab74339087 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -252,8 +252,8 @@ static void s390_ipl_realize(DeviceState *dev, Error **errp) */ romptr = rom_ptr(INITRD_PARM_START, 16); if (romptr) { - stq_p(romptr, initrd_offset); - stq_p(romptr + 1, initrd_size); + stq_be_p(romptr, initrd_offset); + stq_be_p(romptr + 1, initrd_size); } } } diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 30149546c08..41655082dac 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -55,26 +55,26 @@ static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) uint64_t resume_token; rc = 0; - if (lduw_p(&rrb->request.hdr.len) != 32) { + if (lduw_be_p(&rrb->request.hdr.len) != 32) { res_code = CLP_RC_LEN; rc = -EINVAL; goto out; } - if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { + if ((ldl_be_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { res_code = CLP_RC_FMT; rc = -EINVAL; goto out; } - if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || - ldq_p(&rrb->request.reserved1) != 0) { + if ((ldl_be_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || + ldq_be_p(&rrb->request.reserved1) != 0) { res_code = CLP_RC_RESNOT0; rc = -EINVAL; goto out; } - resume_token = ldq_p(&rrb->request.resume_token); + resume_token = ldq_be_p(&rrb->request.resume_token); if (resume_token) { pbdev = s390_pci_find_dev_by_idx(s, resume_token); @@ -87,13 +87,13 @@ static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) pbdev = s390_pci_find_next_avail_dev(s, NULL); } - if (lduw_p(&rrb->response.hdr.len) < 48) { + if (lduw_be_p(&rrb->response.hdr.len) < 48) { res_code = CLP_RC_8K; rc = -EINVAL; goto out; } - initial_l2 = lduw_p(&rrb->response.hdr.len); + initial_l2 = lduw_be_p(&rrb->response.hdr.len); if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) != 0) { res_code = CLP_RC_LEN; @@ -102,33 +102,33 @@ static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) goto out; } - stl_p(&rrb->response.fmt, 0); - stq_p(&rrb->response.reserved1, 0); - stl_p(&rrb->response.mdd, FH_MASK_SHM); - stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); + stl_be_p(&rrb->response.fmt, 0); + stq_be_p(&rrb->response.reserved1, 0); + stl_be_p(&rrb->response.mdd, FH_MASK_SHM); + stw_be_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); rrb->response.flags = UID_CHECKING_ENABLED; rrb->response.entry_size = sizeof(ClpFhListEntry); i = 0; g_l2 = LIST_PCI_HDR_LEN; while (g_l2 < initial_l2 && pbdev) { - stw_p(&rrb->response.fh_list[i].device_id, + stw_be_p(&rrb->response.fh_list[i].device_id, pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); - stw_p(&rrb->response.fh_list[i].vendor_id, + stw_be_p(&rrb->response.fh_list[i].vendor_id, pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); /* Ignore RESERVED devices. */ - stl_p(&rrb->response.fh_list[i].config, + stl_be_p(&rrb->response.fh_list[i].config, pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); - stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); - stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); + stl_be_p(&rrb->response.fh_list[i].fid, pbdev->fid); + stl_be_p(&rrb->response.fh_list[i].fh, pbdev->fh); g_l2 += sizeof(ClpFhListEntry); /* Add endian check for DPRINTF? */ trace_s390_pci_list_entry(g_l2, - lduw_p(&rrb->response.fh_list[i].vendor_id), - lduw_p(&rrb->response.fh_list[i].device_id), - ldl_p(&rrb->response.fh_list[i].fid), - ldl_p(&rrb->response.fh_list[i].fh)); + lduw_be_p(&rrb->response.fh_list[i].vendor_id), + lduw_be_p(&rrb->response.fh_list[i].device_id), + ldl_be_p(&rrb->response.fh_list[i].fid), + ldl_be_p(&rrb->response.fh_list[i].fh)); pbdev = s390_pci_find_next_avail_dev(s, pbdev); i++; } @@ -138,13 +138,13 @@ static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) } else { resume_token = pbdev->fh & FH_MASK_INDEX; } - stq_p(&rrb->response.resume_token, resume_token); - stw_p(&rrb->response.hdr.len, g_l2); - stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); + stq_be_p(&rrb->response.resume_token, resume_token); + stw_be_p(&rrb->response.hdr.len, g_l2); + stw_be_p(&rrb->response.hdr.rsp, CLP_RC_OK); out: if (rc) { trace_s390_pci_list(rc); - stw_p(&rrb->response.hdr.rsp, res_code); + stw_be_p(&rrb->response.hdr.rsp, res_code); } return rc; } @@ -172,7 +172,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) return 0; } reqh = (ClpReqHdr *)buffer; - req_len = lduw_p(&reqh->len); + req_len = lduw_be_p(&reqh->len); if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { s390_program_interrupt(env, PGM_OPERAND, ra); return 0; @@ -184,7 +184,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) return 0; } resh = (ClpRspHdr *)(buffer + req_len); - res_len = lduw_p(&resh->len); + res_len = lduw_be_p(&resh->len); if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { s390_program_interrupt(env, PGM_OPERAND, ra); return 0; @@ -201,11 +201,11 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) } if (req_len != 32) { - stw_p(&resh->rsp, CLP_RC_LEN); + stw_be_p(&resh->rsp, CLP_RC_LEN); goto out; } - switch (lduw_p(&reqh->cmd)) { + switch (lduw_be_p(&reqh->cmd)) { case CLP_LIST_PCI: { ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; list_pci(rrb, &cc); @@ -215,9 +215,9 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; - pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); + pbdev = s390_pci_find_dev_by_fh(s, ldl_be_p(&reqsetpci->fh)); if (!pbdev) { - stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); + stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); goto out; } @@ -225,17 +225,17 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) case CLP_SET_ENABLE_PCI_FN: switch (reqsetpci->ndas) { case 0: - stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); + stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); goto out; case 1: break; default: - stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); + stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); goto out; } if (pbdev->fh & FH_MASK_ENABLE) { - stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); + stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); goto out; } @@ -249,29 +249,29 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) /* Take this opportunity to make sure we are sync'd with host */ if (!s390_pci_get_host_fh(pbdev, &pbdev->fh) || !(pbdev->fh & FH_MASK_ENABLE)) { - stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); + stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); goto out; } } pbdev->fh |= FH_MASK_ENABLE; pbdev->state = ZPCI_FS_ENABLED; - stl_p(&ressetpci->fh, pbdev->fh); - stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); + stl_be_p(&ressetpci->fh, pbdev->fh); + stw_be_p(&ressetpci->hdr.rsp, CLP_RC_OK); break; case CLP_SET_DISABLE_PCI_FN: if (!(pbdev->fh & FH_MASK_ENABLE)) { - stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); + stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); goto out; } device_cold_reset(DEVICE(pbdev)); pbdev->fh &= ~FH_MASK_ENABLE; pbdev->state = ZPCI_FS_DISABLED; - stl_p(&ressetpci->fh, pbdev->fh); - stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); + stl_be_p(&ressetpci->fh, pbdev->fh); + stw_be_p(&ressetpci->hdr.rsp, CLP_RC_OK); break; default: trace_s390_pci_unknown("set-pci", reqsetpci->oc); - stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); + stw_be_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); break; } break; @@ -280,23 +280,23 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; - pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); + pbdev = s390_pci_find_dev_by_fh(s, ldl_be_p(&reqquery->fh)); if (!pbdev) { - trace_s390_pci_nodev("query", ldl_p(&reqquery->fh)); - stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); + trace_s390_pci_nodev("query", ldl_be_p(&reqquery->fh)); + stw_be_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); goto out; } - stq_p(&resquery->sdma, pbdev->zpci_fn.sdma); - stq_p(&resquery->edma, pbdev->zpci_fn.edma); - stw_p(&resquery->pchid, pbdev->zpci_fn.pchid); - stw_p(&resquery->vfn, pbdev->zpci_fn.vfn); + stq_be_p(&resquery->sdma, pbdev->zpci_fn.sdma); + stq_be_p(&resquery->edma, pbdev->zpci_fn.edma); + stw_be_p(&resquery->pchid, pbdev->zpci_fn.pchid); + stw_be_p(&resquery->vfn, pbdev->zpci_fn.vfn); resquery->flags = pbdev->zpci_fn.flags; resquery->pfgid = pbdev->zpci_fn.pfgid; resquery->pft = pbdev->zpci_fn.pft; resquery->fmbl = pbdev->zpci_fn.fmbl; - stl_p(&resquery->fid, pbdev->zpci_fn.fid); - stl_p(&resquery->uid, pbdev->zpci_fn.uid); + stl_be_p(&resquery->fid, pbdev->zpci_fn.fid); + stl_be_p(&resquery->uid, pbdev->zpci_fn.uid); memcpy(resquery->pfip, pbdev->zpci_fn.pfip, CLP_PFIP_NR_SEGMENTS); memcpy(resquery->util_str, pbdev->zpci_fn.util_str, CLP_UTIL_STR_LEN); @@ -304,16 +304,16 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) uint32_t data = pci_get_long(pbdev->pdev->config + PCI_BASE_ADDRESS_0 + (i * 4)); - stl_p(&resquery->bar[i], data); + stl_be_p(&resquery->bar[i], data); resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? ctz64(pbdev->pdev->io_regions[i].size) : 0; trace_s390_pci_bar(i, - ldl_p(&resquery->bar[i]), + ldl_be_p(&resquery->bar[i]), pbdev->pdev->io_regions[i].size, resquery->bar_size[i]); } - stw_p(&resquery->hdr.rsp, CLP_RC_OK); + stw_be_p(&resquery->hdr.rsp, CLP_RC_OK); break; } case CLP_QUERY_PCI_FNGRP: { @@ -326,23 +326,23 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) if (!group) { /* We do not allow access to unknown groups */ /* The group must have been obtained with a vfio device */ - stw_p(&resgrp->hdr.rsp, CLP_RC_QUERYPCIFG_PFGID); + stw_be_p(&resgrp->hdr.rsp, CLP_RC_QUERYPCIFG_PFGID); goto out; } resgrp->fr = group->zpci_group.fr; - stq_p(&resgrp->dasm, group->zpci_group.dasm); - stq_p(&resgrp->msia, group->zpci_group.msia); - stw_p(&resgrp->mui, group->zpci_group.mui); - stw_p(&resgrp->i, group->zpci_group.i); - stw_p(&resgrp->maxstbl, group->zpci_group.maxstbl); + stq_be_p(&resgrp->dasm, group->zpci_group.dasm); + stq_be_p(&resgrp->msia, group->zpci_group.msia); + stw_be_p(&resgrp->mui, group->zpci_group.mui); + stw_be_p(&resgrp->i, group->zpci_group.i); + stw_be_p(&resgrp->maxstbl, group->zpci_group.maxstbl); resgrp->version = group->zpci_group.version; resgrp->dtsm = group->zpci_group.dtsm; - stw_p(&resgrp->hdr.rsp, CLP_RC_OK); + stw_be_p(&resgrp->hdr.rsp, CLP_RC_OK); break; } default: - trace_s390_pci_unknown("clp", lduw_p(&reqh->cmd)); - stw_p(&resh->rsp, CLP_RC_CMD); + trace_s390_pci_unknown("clp", lduw_be_p(&reqh->cmd)); + stw_be_p(&resh->rsp, CLP_RC_CMD); break; } @@ -914,7 +914,7 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, for (i = 0; i < len / 8; i++) { result = memory_region_dispatch_write(mr, offset + i * 8, - ldq_p(buffer + i * 8), + ldq_be_p(buffer + i * 8), MO_64, MEMTXATTRS_UNSPECIFIED); if (result != MEMTX_OK) { s390_program_interrupt(env, PGM_OPERAND, ra); @@ -935,13 +935,13 @@ specification_error: static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) { int ret, len; - uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); + uint8_t isc = FIB_DATA_ISC(ldl_be_p(&fib.data)); pbdev->routes.adapter.adapter_id = css_get_adapter_id( CSS_IO_ADAPTER_PCI, isc); - pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); - len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); - pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); + pbdev->summary_ind = get_indicator(ldq_be_p(&fib.aisb), sizeof(uint64_t)); + len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_be_p(&fib.data))) * sizeof(unsigned long); + pbdev->indicator = get_indicator(ldq_be_p(&fib.aibv), len); ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); if (ret) { @@ -953,13 +953,13 @@ static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) goto out; } - pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); - pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); - pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); - pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); + pbdev->routes.adapter.summary_addr = ldq_be_p(&fib.aisb); + pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_be_p(&fib.data)); + pbdev->routes.adapter.ind_addr = ldq_be_p(&fib.aibv); + pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_be_p(&fib.data)); pbdev->isc = isc; - pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); - pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); + pbdev->noi = FIB_DATA_NOI(ldl_be_p(&fib.data)); + pbdev->sum = FIB_DATA_SUM(ldl_be_p(&fib.data)); trace_s390_pci_irqs("register", pbdev->routes.adapter.adapter_id); return 0; @@ -994,9 +994,9 @@ static int reg_ioat(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib, uintptr_t ra) { S390PCIIOMMU *iommu = pbdev->iommu; - uint64_t pba = ldq_p(&fib.pba); - uint64_t pal = ldq_p(&fib.pal); - uint64_t g_iota = ldq_p(&fib.iota); + uint64_t pba = ldq_be_p(&fib.pba); + uint64_t pal = ldq_be_p(&fib.pal); + uint64_t g_iota = ldq_be_p(&fib.iota); uint8_t dt = (g_iota >> 2) & 0x7; uint8_t t = (g_iota >> 11) & 0x1; @@ -1289,7 +1289,7 @@ int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, } break; case ZPCI_MOD_FC_SET_MEASURE: { - uint64_t fmb_addr = ldq_p(&fib.fmb_addr); + uint64_t fmb_addr = ldq_be_p(&fib.fmb_addr); if (fmb_addr & FMBK_MASK) { cc = ZPCI_PCI_LS_ERR; @@ -1399,17 +1399,17 @@ int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, return 0; } - stq_p(&fib.pba, pbdev->iommu->pba); - stq_p(&fib.pal, pbdev->iommu->pal); - stq_p(&fib.iota, pbdev->iommu->g_iota); - stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); - stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); - stq_p(&fib.fmb_addr, pbdev->fmb_addr); + stq_be_p(&fib.pba, pbdev->iommu->pba); + stq_be_p(&fib.pal, pbdev->iommu->pal); + stq_be_p(&fib.iota, pbdev->iommu->g_iota); + stq_be_p(&fib.aibv, pbdev->routes.adapter.ind_addr); + stq_be_p(&fib.aisb, pbdev->routes.adapter.summary_addr); + stq_be_p(&fib.fmb_addr, pbdev->fmb_addr); data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; 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[88.29.191.45]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d081f7464sm2170287f8f.12.2024.10.03.16.43.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:43:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 10/16] target/s390x: Use explicit big-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:05 +0200 Message-ID: <20241003234211.53644-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The S390 architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- target/s390x/gdbstub.c | 4 ++-- target/s390x/ioinst.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index a9f4eb92adf..f346208f79d 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -88,7 +88,7 @@ static int cpu_write_ac_reg(CPUState *cs, uint8_t *mem_buf, int n) switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: - env->aregs[n] = ldl_p(mem_buf); + env->aregs[n] = ldl_be_p(mem_buf); cpu_synchronize_post_init(env_cpu(env)); return 4; default: @@ -123,7 +123,7 @@ static int cpu_write_fp_reg(CPUState *cs, uint8_t *mem_buf, int n) switch (n) { case S390_FPC_REGNUM: - env->fpc = ldl_p(mem_buf); + env->fpc = ldl_be_p(mem_buf); return 4; case S390_F0_REGNUM ... S390_F15_REGNUM: *get_freg(env, n - S390_F0_REGNUM) = ldtul_p(mem_buf); diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c index bbe45a497a8..a944f16c254 100644 --- a/target/s390x/ioinst.c +++ b/target/s390x/ioinst.c @@ -603,7 +603,7 @@ static int chsc_sei_nt2_have_event(void) #define CHSC_SEI_NT2 (1ULL << 61) static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res) { - uint64_t selection_mask = ldq_p(&req->param1); + uint64_t selection_mask = ldq_be_p(&req->param1); uint8_t *res_flags = (uint8_t *)res->data; int have_event = 0; int have_more = 0; From patchwork Thu Oct 3 23:42:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13821665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E695CCF34D6 for ; Thu, 3 Oct 2024 23:44:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1swVUD-0000qJ-TO; Thu, 03 Oct 2024 19:43:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1swVU6-00009r-IU for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:43:51 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1swVU3-00042g-Hf for qemu-devel@nongnu.org; Thu, 03 Oct 2024 19:43:50 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-42cb8dac900so14748715e9.3 for ; Thu, 03 Oct 2024 16:43:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727999025; x=1728603825; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=40sQ4VfLlzD0bwKrU0yv53LEQFzkHa33/3LdJQsX1lI=; b=C6dSb+HU7s024JWuPCW04mC67eiQRg5D9BCm3dH1rg2h0fkBdmTIDraO5cwKBgzXgt hTg7Db2e3/s7W0e51KMaaoG+GQu9HURSXcyrWLHVFb1EFEBpBnnCvY8frWJn2ebwhq5x 6ssIsnLbx2eRKdxbFST6RYYgkeU8oOmtXnWrR5o9zsYsK+6ih4RyEfxduus95PsWWciS e0PpeDEnDDIg4Px+DeOTYMUOaH0xtrTHkwPpLUIAI895WuyKx5801XhezBPnAM7jEbVv 5cbAg3ABC8JejCvKLON4BNrMs7EEp8Ma/V+hBuRh/qAjK1PTkCGo46iFC5aVGgPm4EeJ mFyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727999025; x=1728603825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=40sQ4VfLlzD0bwKrU0yv53LEQFzkHa33/3LdJQsX1lI=; b=wHUNRAggdv6lC6WbWioxBleShoRfz5dO/FBdAy5mddUAyWU+GeDOuE0nNQB76DTQJL 4sCnW67Lu7uvZpmFTab3xBKOpwluLtn40GnhnVnlvFlyvDlXp2NxkX2IrwLz5gNxPW9t 5hMQeBYI7wZkPgP1VHa2m1UR2QL+gZqz8ocHnye8tFKw64NEG7NTn9Y4ilRWo2q2kXus XWZDEd/cF/mog6rAPImSpxJ6kIc0apId3xTHRRus1uAbfzegGfNJgyKC1Utdvl83CDms wZ5rU4a8sci+ASHpl8mQe8741682vYZPeP3v25lKp0ke1bIcqhXDu5yAtL1m9kRS6soC lasw== X-Gm-Message-State: AOJu0YyRz6mFByijVKmGOnVsFwQAQGwhdw4T+olLlrkqFJEJnJx7PlYX ZGB57N/VeSCYAORVcFRkTK87/mw8TgndDlArexZrtc2nWjhkylAlgHvvZziy8hYxJ6mljk0dJgs skUw= X-Google-Smtp-Source: AGHT+IE6wDFO3YWjtJCgM/UhCvl215hi1nTPJ7ePzE5qEO3OwVI5fPDybbhIShNyCPzor5JXBSc9KA== X-Received: by 2002:adf:f7c1:0:b0:37c:ced2:843b with SMTP id ffacd0b85a97d-37d0e6f0373mr594835f8f.20.1727999024875; Thu, 03 Oct 2024 16:43:44 -0700 (PDT) Received: from localhost.localdomain (45.red-88-29-191.dynamicip.rima-tde.net. [88.29.191.45]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42f86b1d566sm1315975e9.14.2024.10.03.16.43.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:43:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 11/16] hw/sparc: Use explicit big-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:06 +0200 Message-ID: <20241003234211.53644-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The SPARC architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Reviewed-by: Chigot Clément --- hw/sparc/leon3.c | 42 +++++++++++++++++++++--------------------- hw/sparc/sun4m.c | 6 +++--- hw/sparc64/sun4u.c | 6 +++--- 3 files changed, 27 insertions(+), 27 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 6aaa04cb191..021b5070128 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -78,21 +78,21 @@ typedef struct ResetData { static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) { - stl_p(code++, 0x82100000); /* mov %g0, %g1 */ - stl_p(code++, 0x84100000); /* mov %g0, %g2 */ - stl_p(code++, 0x03000000 + + stl_be_p(code++, 0x82100000); /* mov %g0, %g1 */ + stl_be_p(code++, 0x84100000); /* mov %g0, %g2 */ + stl_be_p(code++, 0x03000000 + extract32(addr, 10, 22)); /* sethi %hi(addr), %g1 */ - stl_p(code++, 0x82106000 + + stl_be_p(code++, 0x82106000 + extract32(addr, 0, 10)); /* or %g1, addr, %g1 */ - stl_p(code++, 0x05000000 + + stl_be_p(code++, 0x05000000 + extract32(val, 10, 22)); /* sethi %hi(val), %g2 */ - stl_p(code++, 0x8410a000 + + stl_be_p(code++, 0x8410a000 + extract32(val, 0, 10)); /* or %g2, val, %g2 */ - stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */ + stl_be_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */ return code; } @@ -112,13 +112,13 @@ static void write_bootloader(void *ptr, hwaddr kernel_addr) /* If we are running on a secondary CPU, jump directly to the kernel. */ - stl_p(p++, 0x85444000); /* rd %asr17, %g2 */ - stl_p(p++, 0x8530a01c); /* srl %g2, 0x1c, %g2 */ - stl_p(p++, 0x80908000); /* tst %g2 */ + stl_be_p(p++, 0x85444000); /* rd %asr17, %g2 */ + stl_be_p(p++, 0x8530a01c); /* srl %g2, 0x1c, %g2 */ + stl_be_p(p++, 0x80908000); /* tst %g2 */ /* Filled below. */ sec_cpu_branch_p = p; - stl_p(p++, 0x0BADC0DE); /* bne xxx */ - stl_p(p++, 0x01000000); /* nop */ + stl_be_p(p++, 0x0BADC0DE); /* bne xxx */ + stl_be_p(p++, 0x01000000); /* nop */ /* Initialize the UARTs */ /* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */ @@ -133,17 +133,17 @@ static void write_bootloader(void *ptr, hwaddr kernel_addr) p = gen_store_u32(p, 0x80000318, 3); /* Now, the relative branch above can be computed. */ - stl_p(sec_cpu_branch_p, 0x12800000 - + (p - sec_cpu_branch_p)); + stl_be_p(sec_cpu_branch_p, 0x12800000 + + (p - sec_cpu_branch_p)); /* JUMP to the entry point */ - stl_p(p++, 0x82100000); /* mov %g0, %g1 */ - stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22)); - /* sethi %hi(kernel_addr), %g1 */ - stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10)); - /* or kernel_addr, %g1 */ - stl_p(p++, 0x81c04000); /* jmp %g1 */ - stl_p(p++, 0x01000000); /* nop */ + stl_be_p(p++, 0x82100000); /* mov %g0, %g1 */ + stl_be_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22)); + /* sethi %hi(kernel_addr), %g1 */ + stl_be_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10)); + /* or kernel_addr, %g1 */ + stl_be_p(p++, 0x81c04000); /* jmp %g1 */ + stl_be_p(p++, 0x01000000); /* nop */ } static void leon3_cpu_reset(void *opaque) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index d52e6a7213f..f375f0d389b 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -271,9 +271,9 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename, if (*initrd_size > 0) { for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); - if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ - stl_p(ptr + 16, INITRD_LOAD_ADDR); - stl_p(ptr + 20, *initrd_size); + if (ptr && ldl_be_p(ptr) == 0x48647253) { /* HdrS */ + stl_be_p(ptr + 16, INITRD_LOAD_ADDR); + stl_be_p(ptr + 20, *initrd_size); break; } } diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 4ece1ac1ffc..e591e5a741a 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -210,9 +210,9 @@ static uint64_t sun4u_load_kernel(const char *kernel_filename, if (*initrd_size > 0) { for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { ptr = rom_ptr(*kernel_addr + i, 32); - if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ - stl_p(ptr + 24, *initrd_addr + *kernel_addr); - stl_p(ptr + 28, *initrd_size); + if (ptr && ldl_be_p(ptr + 8) == 0x48647253) { /* HdrS */ + stl_be_p(ptr + 24, *initrd_addr + *kernel_addr); + stl_be_p(ptr + 28, *initrd_size); break; } } From patchwork Thu Oct 3 23:42:07 2024 Content-Type: text/plain; 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[88.29.191.45]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082a6a2esm2138210f8f.66.2024.10.03.16.43.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Oct 2024 16:43:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Michael Rolnik , Halil Pasic , Christian Borntraeger , Mark Cave-Ayland , Frederic Konrad , Artyom Tarasenko , Matthew Rosato , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , David Hildenbrand , Peter Xu , Ilya Leoshkevich , Song Gao , Thomas Huth , Marcel Apfelbaum , Eduardo Habkost , qemu-s390x@nongnu.org, Laurent Vivier , Eric Farman , =?utf-8?q?Cl=C3=A9ment_Chigot?= , Paolo Bonzini , "Michael S. Tsirkin" , Thomas Huth , Bastian Koppelmann , Richard Henderson , Pierrick Bouvier Subject: [PATCH 12/16] target/sparc: Use explicit big-endian LD/ST API Date: Fri, 4 Oct 2024 01:42:07 +0200 Message-ID: <20241003234211.53644-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241003234211.53644-1-philmd@linaro.org> References: <20241003234211.53644-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The SPARC architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland --- target/sparc/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index ec0036e9ef6..da72a7d3f69 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -110,7 +110,7 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) #if defined(TARGET_ABI32) uint32_t tmp; - tmp = ldl_p(mem_buf); + tmp = ldl_be_p(mem_buf); #else target_ulong tmp; @@ -165,7 +165,7 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) #else else if (n < 64) { /* f0-f31 */ - tmp = ldl_p(mem_buf); + tmp = ldl_be_p(mem_buf); if (n & 1) { env->fpr[(n - 32) / 2].l.lower = tmp; } else {