From patchwork Sat Oct 5 10:37:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13823221 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29CCE14A629; Sat, 5 Oct 2024 10:37:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728124671; cv=none; b=XpbcQgGy/kr+OaAQoSo9enjq9YNklIyA8uYOQZKf+lK5NVuIVhGEuwqe2nWr7szVo6onUBRgWycmFtYeoc4rdFD2ctNVMB2OcRj+IBkTkaQeU8h3FNivoBLiK5YJPxqfjDRgi1NgKSBAv8ONKaljWMuFJm0fNFwQWCLraVyUJZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728124671; c=relaxed/simple; bh=QbqPPtlt/36NRRykoSC6fOII09vEJC3Jof1+QZGywM8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aWo9Hxa0Poh4+CQKA5QJzAm/o3/GXcgv7BFJSrFEE8/jo9izAeMLNPthWMoK9v0/Np8gDZ3FUNlAM3NLCgtIw8jU0EfOhHSG7K6v27ta+XpZCOpr/+yTyHH1R8AM1cBxeeF/1HHSkVyklHOHIed3lo09Abk3GF5TaG0Qufv4CZ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gxNjaWC6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gxNjaWC6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48605C4CECC; Sat, 5 Oct 2024 10:37:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728124670; bh=QbqPPtlt/36NRRykoSC6fOII09vEJC3Jof1+QZGywM8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gxNjaWC6yOVVvp3TMQ8pK+Y47LltPtgyzBJ+hbuujEketXsOB7YBITOgP5KLKv7Fh 0OVgIm2Zy2Qv+TgKuM53JDZ7DhODgJyDbczWCtFp0lwX8evsnMSY2uiws08EDFZbIA S7uJlLqOYDt+ORQZUO7qHLvlTUHqgcDCPZ4OqG0jUkSswAMhbul7bBaA47eREfnC0v MyWuTKby6JtyPUuCG1V7ZtILpTNK1kBaFxU8SUU9wf/et7sw2bnlGmyBDz4u2S+IDV er72uLHiXeC3rJ8kOK5V5nw1I90ecO3yGKerwsYlIPFT+S85q4n1J7V4SZTSE/0spI cdeVdGYawuP7g== From: Mark Brown Date: Sat, 05 Oct 2024 11:37:28 +0100 Subject: [PATCH v14 1/5] KVM: arm64: Expose S1PIE to guests Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241005-arm64-gcs-v14-1-59060cd6092b@kernel.org> References: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> In-Reply-To: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=1617; i=broonie@kernel.org; h=from:subject:message-id; bh=QbqPPtlt/36NRRykoSC6fOII09vEJC3Jof1+QZGywM8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnARb1QtItMZjozqWtKsSdLOTTu4J0BaffKuWKVeZ3 xoSzl+CJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZwEW9QAKCRAk1otyXVSH0F0/B/ 46fuNQRlGNAqZbCOsnnF7mhJNrGYEvzbev4l+BTYXh44XesiYS4VZpe1sVwTTFzydKT2vwtcXeqj1r gFq4DV+cXQuGcasG5FqfvZjvHpZVvxC+bpYtEnSSrgUhrzBxzm0B6K38G6BtcjX9pMcCHVgAVHFqz0 6uIIvXv+I9xLimBYJ9MwHXX89cP2076yXOdNqEPdOw7BXS0g/oFjCKNCj4twz3gbcpl9kHHO+UHsEp gA0FuiK1rK7f4ijpvSEJ8Bogm/mlGIL0T7ECRnUDMuSfMQkJvq6B0rc6j4CqjDfzkmQl8KbX3cFiPa O+vQmbbMc5a348nl0WSYEpAjxeyeRW X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Prior to commit 70ed7238297f ("KVM: arm64: Sanitise ID_AA64MMFR3_EL1") we just exposed the santised view of ID_AA64MMFR3_EL1 to guests, meaning that they saw both TCRX and S1PIE if present on the host machine. That commit added VMM control over the contents of the register and exposed S1POE but removed S1PIE, meaning that the extension is no longer visible to guests. Reenable support for S1PIE with VMM control. Fixes: 70ed7238297f ("KVM: arm64: Sanitise ID_AA64MMFR3_EL1") Signed-off-by: Mark Brown --- arch/arm64/kvm/sys_regs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dad88e31f9537fe02e28b117d6a740f15572e0ba..d48f89ad6aa7139078e7991ce6c8ebc4a0543551 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1550,7 +1550,8 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; break; case SYS_ID_AA64MMFR3_EL1: - val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE; + val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE | + ID_AA64MMFR3_EL1_S1PIE; break; case SYS_ID_MMFR4_EL1: val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX); @@ -2433,6 +2434,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64MMFR2_EL1_NV | ID_AA64MMFR2_EL1_CCIDX)), ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX | + ID_AA64MMFR3_EL1_S1PIE | ID_AA64MMFR3_EL1_S1POE)), ID_SANITISED(ID_AA64MMFR4_EL1), ID_UNALLOCATED(7,5), From patchwork Sat Oct 5 10:37:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13823222 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F26D14D71D; Sat, 5 Oct 2024 10:37:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728124674; cv=none; b=jrleDPQcAby/VhMH+SnYtrdfCZqJm8WvrZrGJdjyzQRZwuSW6QgTqyINEc3lKBR8g87KIcSbX1UxHKor2BcJiGStMQeeUdbjIcAOSGV8NNHJFCigaHmDiIwpESFzkdTEGo7Pu9+gs05yHThvddnY2bZ1Vl5PA7791GtTMZkEC6g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728124674; c=relaxed/simple; bh=8Pjxo9INu/EMoo+OhS44/Ry5FhrWqchqYTe1rDN+srw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tTh90bB08iGrjEPJU3o9gOYpEVME5W5LqlB3Nh/2/RJhnOhscU5VE2L7Hg0OuvXwSv5HdIufi0ssQE8uMvX3ry3kzdDUFeCLWVXw7USq0G7l9Q7oaweg82fo6SN2Z3ZASINf/vpmCpOO/5PsOIuYWf+OPedN8WmXnhlKvr+bZNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bvXwRAie; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bvXwRAie" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2A788C4CEC2; Sat, 5 Oct 2024 10:37:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728124673; bh=8Pjxo9INu/EMoo+OhS44/Ry5FhrWqchqYTe1rDN+srw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=bvXwRAie93MFmCGJRO4V+tIfv2x+W2yImgIjT6hJdi8+RZuCnPhDyIVR62QeMeBcP bLQZCqgGCXtgHpKLinhIeNj46JJWPgstEjHAmGFEGUatlhtrYZLlhOHv/sRa6dKcAC JCtd6Ozz9HTybQtmamvlkhY5/NEcsikCKeWJzS/wrEbHijhTrJY981GAAK7dZ218F+ k2ABlQM8wSaUG3CdsJSr33xOYVzszcTUbkwEsJWW4/fpWBJtznqHkZ7tv32Oe4KV7b FbI9M7fwPpdHJ8IirLdpZ1fSJ4BjohM10BkYdiwy/qkVyd+uE934J4TpkoyvHywrPG yCL//zlICqG9A== From: Mark Brown Date: Sat, 05 Oct 2024 11:37:29 +0100 Subject: [PATCH v14 2/5] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241005-arm64-gcs-v14-2-59060cd6092b@kernel.org> References: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> In-Reply-To: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=1301; i=broonie@kernel.org; h=from:subject:message-id; bh=8Pjxo9INu/EMoo+OhS44/Ry5FhrWqchqYTe1rDN+srw=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnARb1lDpxvdKpZowgvD/JRoSi/pRDCs1WIRe/PPzb EpioVFSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZwEW9QAKCRAk1otyXVSH0LmUB/ 0banw7+CVnBt752fDpu8Y34/fz21ZAwQ8KbJGKTIH6/tX1K8ReNsMuZBsW2PSDY5tDYDQ4HQMLqHRl 230LEsoW/n2GqS/bGxFWXghMpzb/a0HiHyze5zB6NkXDiYhtLeb/gVocsBYnrUj85xpKCk7wDbciBX ru0Nft+Baamtso/j+nZfPBbV3D0aeG0jLuFs3e4vboXmQ08Wyr/DeKT2+d4LQpMYi1SxhjRcQaCiyJ aAW7h0aI3udMpf2yEJC73UWibBJ1FRrgbNyVz1FkR/M/QpKw+Ei+cfSirjvaLvKmGLIXjFJH5ae01B SRGU9w7ZvzFVN1KR7cBlqQd7nn+Nku X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The initial EL2 setup for GCS did not include disabling of EL1 usage of GCS instructions, also disable these traps. This is the first disabling of instruction traps, use x2 to store the value to be written. Signed-off-by: Mark Brown --- arch/arm64/include/asm/el2_setup.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 27086a81eae34483a682681ab1be1959a339527a..99e887a5b2190f8810f1ed22d35b7acd26d2fd1e 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -170,6 +170,7 @@ cbz x1, .Lskip_fgt_\@ mov x0, xzr + mov x2, xzr mrs x1, id_aa64dfr0_el1 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 cmp x1, #3 @@ -217,10 +218,14 @@ orr x0, x0, #HFGxTR_EL2_nGCS_EL1_MASK orr x0, x0, #HFGxTR_EL2_nGCS_EL0_MASK + orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK + orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK + orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK + .Lset_fgt_\@: msr_s SYS_HFGRTR_EL2, x0 msr_s SYS_HFGWTR_EL2, x0 - msr_s SYS_HFGITR_EL2, xzr + msr_s SYS_HFGITR_EL2, x2 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 From patchwork Sat Oct 5 10:37:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13823223 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCCCB149DF4; Sat, 5 Oct 2024 10:37:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728124677; cv=none; b=of+pBcTDuBN9ljuoAdsvdCtDw4HRYt6xlnTZtuTviBKoS2AvgMTHAnJ4hz4qD/K5pbgOMyYyrGjoVn9zC7D/aUX/oxHOpBA5ZiuWL++s14GS0bV6BJ4DipE5MLUC7hAzgZugSxOutdLSdNfjkmzLOlGspf3x8liis0uiZ7nvyaE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728124677; c=relaxed/simple; bh=dzX0F6AkcdLZYT5mpocXi/GY4x2mPuF9cmobEMLRggA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vr7q3DMo1+DEf/tyR9Z/Pd7riOfbbsoaO2PGgCCPyfZeprZuNEXmm9gHPBsPmJezDYPESPgeAC1P6pXHcyqKJMjNq499lXvpBKAHvh3RNRdub0fkX7qJWdcRnokVoA6dHoX9tXJ5cWYrT6JCJ1eRKZIXR7geGe5SqbhfX36pFw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YAwCRfHd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YAwCRfHd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0FFE7C4CECC; Sat, 5 Oct 2024 10:37:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728124676; bh=dzX0F6AkcdLZYT5mpocXi/GY4x2mPuF9cmobEMLRggA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YAwCRfHdNOg0sMHndi8ixDMIeWqSvh2+SJmTQyHHEScnn5LBrs/NlM6YUYhZunA4R +Mi7wIoz2lV5pHO/ZAHEwTcp8FjBbEFDAia6DTkG5XSu5XDXxjNatCD79veo8ovLNA gRBwoCgzo5Y0CJ+NnmJ0avIwCRMstrR+JYBw8cY6atdFtDQm9jttj4Q+tuQkLIVMzB OZGd8sB2aauE6DZpPsuPBgCNXtyM+0SRV2H+vkjfN/oA1yY7QecomCkuP7fKuOwmah CygxV7uGuDWFq7fwVY18W61XJNaSjH0B5mw0ZrCjiUJXkh/dCpzyWRBVN5ulqoZkOl 2oSrShERUHGTw== From: Mark Brown Date: Sat, 05 Oct 2024 11:37:30 +0100 Subject: [PATCH v14 3/5] KVM: arm64: Manage GCS access and registers for guests Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241005-arm64-gcs-v14-3-59060cd6092b@kernel.org> References: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> In-Reply-To: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=8836; i=broonie@kernel.org; h=from:subject:message-id; bh=dzX0F6AkcdLZYT5mpocXi/GY4x2mPuF9cmobEMLRggA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnARb2lQ6Qnt7ZiWaHHFmsh/ZOmgb9W5Q7C7sibDJa e9SyCJSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZwEW9gAKCRAk1otyXVSH0Aw0B/ 9p00D662X983Uc3hA/Z7Y9PuwjrekynLAB4kqlvf5lv64bpIvazAPegeYEIigTOUYjJhqlA9mMScdK ER+lOfSYmvatW/E7F6s3opDOdMUFU4VGcwTkaXChlih4y865dez0nN8kduBPg3u9lXSL/Kxl4QXXyy 1/YJ77lDaBwOCLN33fvVedNSll4ooXPXeakYzA0oim1CRmlaSm5O7ygdJHojFI0P0L5MMRylEuKT6k GJGtVppZ/hmls6OjESObLzCA4cTeEieERXRtNu+17/GM6UA216e4kS4QwFVw9xUYbNrB44Ib6Sugc1 jPW0q0rlnc6VJSkPC8sO07JT56Vu1a X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS introduces a number of system registers for EL1 and EL0, on systems with GCS we need to context switch them and expose them to VMMs to allow guests to use GCS. In order to allow guests to use GCS we also need to configure HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and CHKFEAT will report GCS as disabled. Also enable fine grained traps for access to the GCS registers by guests which do not have the feature enabled. In order to allow userspace to control availability of the feature to guests we enable writability for only ID_AA64PFR1_EL1.GCS, this is a deliberately conservative choice to avoid errors due to oversights. Further fields should be made writable in future. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 12 ++++++++++++ arch/arm64/include/asm/vncr_mapping.h | 2 ++ arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 31 ++++++++++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 31 +++++++++++++++++++++++++++++- 4 files changed, 75 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 329619c6fa9611b474dc4823fccf01a3b9dd61a8..31887d3f3de18bf1936ce4329256894f6210c67e 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -448,6 +448,10 @@ enum vcpu_sysreg { POR_EL0, /* Permission Overlay Register 0 (EL0) */ + /* Guarded Control Stack registers */ + GCSCRE0_EL1, /* Guarded Control Stack Control (EL0) */ + GCSPR_EL0, /* Guarded Control Stack Pointer (EL0) */ + /* FP/SIMD/SVE */ SVCR, FPMR, @@ -525,6 +529,10 @@ enum vcpu_sysreg { VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */ + /* Guarded Control Stack registers */ + VNCR(GCSPR_EL1), /* Guarded Control Stack Pointer (EL1) */ + VNCR(GCSCR_EL1), /* Guarded Control Stack Control (EL1) */ + VNCR(HFGRTR_EL2), VNCR(HFGWTR_EL2), VNCR(HFGITR_EL2), @@ -1495,4 +1503,8 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); (system_supports_fpmr() && \ kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP)) +#define kvm_has_gcs(k) \ + (system_supports_gcs() && \ + kvm_has_feat((k), ID_AA64PFR1_EL1, GCS, IMP)) + #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm/vncr_mapping.h index 06f8ec0906a6e92b6dd57c692e1293ac3d4244fd..e289064148b3268a00830c6fee708029c4c0fbbb 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -89,6 +89,8 @@ #define VNCR_PMSIRR_EL1 0x840 #define VNCR_PMSLATFR_EL1 0x848 #define VNCR_TRFCR_EL1 0x880 +#define VNCR_GCSPR_EL1 0x8C0 +#define VNCR_GCSCR_EL1 0x8D0 #define VNCR_MPAM1_EL1 0x900 #define VNCR_MPAMHCR_EL2 0x930 #define VNCR_MPAMVPMV_EL2 0x938 diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h index 1579a3c08a36b989fec7fdc3f38b64cb498326f3..70bd6143083439d75387eccc17f5c3811c689047 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -17,6 +17,7 @@ #include static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt); +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt); static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt) { @@ -31,6 +32,11 @@ static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt) { ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0); ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0); + + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL0) = read_sysreg_s(SYS_GCSPR_EL0); + ctxt_sys_reg(ctxt, GCSCRE0_EL1) = read_sysreg_s(SYS_GCSCRE0_EL1); + } } static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt) @@ -83,6 +89,17 @@ static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt) return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64MMFR3_EL1, S1POE, IMP); } +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt) +{ + struct kvm_vcpu *vcpu; + + if (!cpus_have_final_cap(ARM64_HAS_GCS)) + return false; + + vcpu = ctxt_to_vcpu(ctxt); + return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64PFR1_EL1, GCS, IMP); +} + static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR); @@ -96,6 +113,10 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) if (ctxt_has_s1pie(ctxt)) { ctxt_sys_reg(ctxt, PIR_EL1) = read_sysreg_el1(SYS_PIR); ctxt_sys_reg(ctxt, PIRE0_EL1) = read_sysreg_el1(SYS_PIRE0); + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL1) = read_sysreg_el1(SYS_GCSPR); + ctxt_sys_reg(ctxt, GCSCR_EL1) = read_sysreg_el1(SYS_GCSCR); + } } if (ctxt_has_s1poe(ctxt)) @@ -150,6 +171,11 @@ static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); + if (ctxt_has_gcs(ctxt)) { + write_sysreg_s(ctxt_sys_reg(ctxt, GCSPR_EL0), SYS_GCSPR_EL0); + write_sysreg_s(ctxt_sys_reg(ctxt, GCSCRE0_EL1), + SYS_GCSCRE0_EL1); + } } static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) @@ -181,6 +207,11 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) if (ctxt_has_s1pie(ctxt)) { write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR); write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0); + + if (ctxt_has_gcs(ctxt)) { + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSPR_EL1), SYS_GCSPR); + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSCR_EL1), SYS_GCSCR); + } } if (ctxt_has_s1poe(ctxt)) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d48f89ad6aa7139078e7991ce6c8ebc4a0543551..0d0c400ce15f0db2ffbe71d310eee6dbc2280429 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1642,6 +1642,15 @@ static unsigned int raz_visibility(const struct kvm_vcpu *vcpu, return REG_RAZ; } +static unsigned int gcs_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r) +{ + if (kvm_has_gcs(vcpu->kvm)) + return 0; + + return REG_HIDDEN; +} + /* cpufeature ID register access trap handlers */ static bool access_id_reg(struct kvm_vcpu *vcpu, @@ -2377,7 +2386,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64PFR0_EL1_RAS | ID_AA64PFR0_EL1_AdvSIMD | ID_AA64PFR0_EL1_FP), }, - ID_SANITISED(ID_AA64PFR1_EL1), + ID_WRITABLE(ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_GCS), ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR), ID_UNALLOCATED(4,3), ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), @@ -2463,6 +2472,13 @@ static const struct sys_reg_desc sys_reg_descs[] = { PTRAUTH_KEY(APDB), PTRAUTH_KEY(APGA), + { SYS_DESC(SYS_GCSCR_EL1), NULL, reset_val, GCSCR_EL1, 0, + .visibility = gcs_visibility }, + { SYS_DESC(SYS_GCSPR_EL1), NULL, reset_unknown, GCSPR_EL1, + .visibility = gcs_visibility }, + { SYS_DESC(SYS_GCSCRE0_EL1), NULL, reset_val, GCSCRE0_EL1, 0, + .visibility = gcs_visibility }, + { SYS_DESC(SYS_SPSR_EL1), access_spsr}, { SYS_DESC(SYS_ELR_EL1), access_elr}, @@ -2569,6 +2585,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { CTR_EL0_IDC_MASK | CTR_EL0_DminLine_MASK | CTR_EL0_IminLine_MASK), + { SYS_DESC(SYS_GCSPR_EL0), NULL, reset_unknown, GCSPR_EL0, + .visibility = gcs_visibility }, { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, @@ -4663,6 +4681,9 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) if (kvm_has_fpmr(kvm)) vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM; + + if (kvm_has_gcs(kvm)) + vcpu->arch.hcrx_el2 |= HCRX_EL2_GCSEn; } if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) @@ -4716,6 +4737,14 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | HFGxTR_EL2_nPOR_EL0); + if (!kvm_has_gcs(kvm)) { + kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nGCS_EL0 | + HFGxTR_EL2_nGCS_EL1); + kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_nGCSEPP | + HFGITR_EL2_nGCSSTR_EL1 | + HFGITR_EL2_nGCSPUSHM_EL1); + } + if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP)) kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 | HAFGRTR_EL2_RES1); From patchwork Sat Oct 5 10:37:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13823224 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C911C15350B; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dF1gD6G0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E7BDCC4CECE; Sat, 5 Oct 2024 10:37:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728124679; bh=1w+V9LlE1J6cc3An9dYnLJVfYeaBJHjSV6dDDI8zsLg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=dF1gD6G0dluyvIOR3G73dKhwQFvzLmkQmr6FRjX8YxT9aFTj8OT9zeZiuK276sscu o1a1ZREALGTqYLByST2a4agP1z6gY2OYfn1CRSRu3eKul/ksTSsoLcTBju6KMDXGye 3E0e5w678JHwPK2btii1HnyWLpynAup2VYE6vLr3nHIbCaTNUWTj0E/UgWtE3DmgrY bMlpV5RwTMMGmeFnj+eKP0zGslqpgpPbkU1PT1lPeJWl9vN/qISi34HYTBwmlKxHgP 9z/AyHye/vChBcV5E7EGZwA8FZEIh+lNtOJ0YCXSD4nEIeJnWLijHlwfJZr3K/ur5e MQQC1Sq9+H54A== From: Mark Brown Date: Sat, 05 Oct 2024 11:37:31 +0100 Subject: [PATCH v14 4/5] KVM: arm64: Set PSTATE.EXLOCK when entering an exception Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241005-arm64-gcs-v14-4-59060cd6092b@kernel.org> References: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> In-Reply-To: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=2111; i=broonie@kernel.org; h=from:subject:message-id; bh=1w+V9LlE1J6cc3An9dYnLJVfYeaBJHjSV6dDDI8zsLg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnARb3XNsQxPIIVJgqL1ofZ9n+yPUBRv+TsEKWQi+9 EUnXChSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZwEW9wAKCRAk1otyXVSH0OMeB/ 48PIFxhsSEeGYLvbkQwXs0CsofuASzZyRNlYQd6TAmR33CckB3r9f4MbRDTPD5/BKjU8M42crd5dGE N7zCYVdZJK2rwkjnPX66tP2rxRMGYFoffktadf1k4YV3lpeLslgP0ffiXr8GyhrfokscwNGuQ9YsWC xAw1Q2aNwYoTyDwAPI+tJn/R0W1kIrS1oufeh1EJI3eVrF6HQug330/7ZncwYvQIxpIpGrcacAlvi9 PBQdwoofpHTWI4Mq+dCe0WJf8LKGctAJ9624a3XkMY3qO3dNs7gsZnJku6G/q7uQT2+hUWeWhx/0ob wfMwN83sha2Pc6WbQr90onjrvSer0V X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per DDI 0487 RWTXBY we need to manage PSTATE.EXLOCK when entering an exception, when the exception is entered from a lower EL the bit is cleared while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN. Implement this behaviour in enter_exception64(). Signed-off-by: Mark Brown --- arch/arm64/include/uapi/asm/ptrace.h | 2 ++ arch/arm64/kvm/hyp/exception.c | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h index 0f39ba4f3efd4a8760f0fca0fbf1a2563b191c7d..9987957f4f7137bf107653b817885bb976853a83 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h @@ -37,6 +37,7 @@ #define PSR_MODE_EL3t 0x0000000c #define PSR_MODE_EL3h 0x0000000d #define PSR_MODE_MASK 0x0000000f +#define PSR_EL_MASK 0x0000000c /* AArch32 CPSR bits */ #define PSR_MODE32_BIT 0x00000010 @@ -56,6 +57,7 @@ #define PSR_C_BIT 0x20000000 #define PSR_Z_BIT 0x40000000 #define PSR_N_BIT 0x80000000 +#define PSR_EXLOCK_BIT 0x400000000 #define PSR_BTYPE_SHIFT 10 diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c index 424a5107cddb5e1cdd75ef3581adef03aaadabb7..0d41b9b75cf83250b2c0d20cd82c153869efb0e4 100644 --- a/arch/arm64/kvm/hyp/exception.c +++ b/arch/arm64/kvm/hyp/exception.c @@ -160,6 +160,16 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode, // PSTATE.BTYPE is set to zero upon any exception to AArch64 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. + // PSTATE.EXLOCK is set to 0 upon any exception to a higher + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same + // exception level. See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a. + if (kvm_has_gcs(vcpu->kvm) && + (target_mode & PSR_EL_MASK) == (mode & PSR_EL_MASK)) { + u64 gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL1); + if (gcscr & GCSCR_ELx_EXLOCKEN) + new |= PSR_EXLOCK_BIT; + } + new |= PSR_D_BIT; new |= PSR_A_BIT; new |= PSR_I_BIT; From patchwork Sat Oct 5 10:37:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13823225 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98B2D1547C9; Sat, 5 Oct 2024 10:38:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728124682; cv=none; b=RdbDlxe5x0sDv323xbb7eiEyMl5zBhahjh2thS5A2mx9sEZxkCvZwYjAH2cXDz6PcVqfYpahvwlLlbAGOq0qkD94kuzvvdnQpZEWpa92Lg66ZxWlZSIoWN109OSoM4LqxRiLci/PLgu0K/egECs7mzuiFQu8afY3GkRoIb6eG20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728124682; c=relaxed/simple; bh=djrrE5vI61PLt6bp7VaUC+7O2DJ3zSyZt7/lGI0Flkc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DcUKGwqFXtmqrCkwoYpAb7k/zI8YfK/P27v+zic1I0nzKEp+cxUYinIil0KkmN59DIwEAaaoyBPa4UI7kR7EFzOsfrpIo+zCwgMaRl8zcusWZv8rcfPDcW/jFUYifRuFu0s0Cocb6rv6IZ0LggGU33VbWFkTl2RA37IidK9gkNM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EX17Zg/L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EX17Zg/L" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD481C4CEC2; Sat, 5 Oct 2024 10:37:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728124682; bh=djrrE5vI61PLt6bp7VaUC+7O2DJ3zSyZt7/lGI0Flkc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EX17Zg/LFPJeWiupkMxyTmV0uaAUAGotvuvbBzRs04NA+ZvyjHMvTpRojnKAFMkgb tkn0EnrqSRh3QGc3NZrByx5ulwjjOXAeFI3xJ11xrBWuU+T7cNeS+B6usOh6ncBF1w JgAQ1VK9Rbzdi14hcovmQZhQD68bAoEfpLh/UeBLJaib40U/vZHcXSZLpgStABQglE 1Pxl77AkVEcQI1MdQ/5V7jFhNhy8eGDXKjEFMMCVXtlakGKcFipYjRoBZtPtKZDlO7 G7VbHP4x4sjsvtfCzP7NUdIvtg4jE1pW7jp2azF18czb9eD5H5TeLSIoQXfreS7d96 +LL9Kq9Q+eM2w== From: Mark Brown Date: Sat, 05 Oct 2024 11:37:32 +0100 Subject: [PATCH v14 5/5] KVM: selftests: arm64: Add GCS registers to get-reg-list Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241005-arm64-gcs-v14-5-59060cd6092b@kernel.org> References: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> In-Reply-To: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown , Thiago Jung Bauermann X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=2472; i=broonie@kernel.org; h=from:subject:message-id; bh=djrrE5vI61PLt6bp7VaUC+7O2DJ3zSyZt7/lGI0Flkc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnARb4qiU+YPzWEcVBFo6t1JABWxQ5MjKPP1N/ZAgr jErfBQ2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZwEW+AAKCRAk1otyXVSH0BelB/ 9zvYadAZSXpdeHQ2QzcBmpXKpLn70G/fNZB6nAQh+5Lxf101g53WDUQ26PhUMy45Y8E17xuxWYRd2j Tc+1bCXD46lsDosehDL5SlodyeMPCuxXAajDOryY0Nv4VGbaSLMezChTRukxOzepiM693wv8kDEA+a +7JkN2Rus0HM/VNzfOTvoC+0k0Ge17kF/4UItbFE/U/KkaFBzMwsJSOvLxh5miKn8776vkMv84z1nA 5/dwfu88KVjqt5Odz31mxU4e6HL3xOevYT0O8ueh8KgOzmMOriJOH4wXahZ7tInfCPT3G1TNQJo0as tIRbxHq1aJbJtUERr+tFnVOiletCeH X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS adds new registers GCSCR_EL1, GCSCRE0_EL1, GCSPR_EL1 and GCSPR_EL0. Add these to those validated by get-reg-list. Reviewed-by: Thiago Jung Bauermann Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index d43fb3f49050ba3de950d19d56b45beefec9dbeb..c17451069a15d181bb5a7efc8963290828f58c4b 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -29,6 +29,24 @@ static struct feature_id_reg feat_id_regs[] = { 0, 1 }, + { + ARM64_SYS_REG(3, 0, 2, 5, 0), /* GCSCR_EL1 */ + ARM64_SYS_REG(3, 0, 0, 4, 1), /* ID_AA64PFR1_EL1 */ + 44, + 1 + }, + { + ARM64_SYS_REG(3, 0, 2, 5, 1), /* GCSPR_EL1 */ + ARM64_SYS_REG(3, 0, 0, 4, 1), /* ID_AA64PFR1_EL1 */ + 44, + 1 + }, + { + ARM64_SYS_REG(3, 0, 2, 5, 2), /* GCSCRE0_EL1 */ + ARM64_SYS_REG(3, 0, 0, 4, 1), /* ID_AA64PFR1_EL1 */ + 44, + 1 + }, { ARM64_SYS_REG(3, 0, 10, 2, 2), /* PIRE0_EL1 */ ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */ @@ -52,6 +70,12 @@ static struct feature_id_reg feat_id_regs[] = { ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */ 16, 1 + }, + { + ARM64_SYS_REG(3, 3, 2, 5, 1), /* GCSPR_EL0 */ + ARM64_SYS_REG(3, 0, 0, 4, 1), /* ID_AA64PFR1_EL1 */ + 44, + 1 } }; @@ -472,6 +496,9 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 2, 0, 1), /* TTBR1_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 2), /* TCR_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 0), /* GCSCR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 1), /* GCSPR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 2), /* GCSCRE0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 0), /* AFSR0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 1), /* AFSR1_EL1 */ ARM64_SYS_REG(3, 0, 5, 2, 0), /* ESR_EL1 */ @@ -488,6 +515,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */ ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */ ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ + ARM64_SYS_REG(3, 3, 2, 5, 1), /* GCSPR_EL0 */ ARM64_SYS_REG(3, 3, 10, 2, 4), /* POR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */