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Mon, 07 Oct 2024 07:03:41 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d1688a486sm5857022f8f.0.2024.10.07.07.03.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2024 07:03:41 -0700 (PDT) From: Neil Armstrong Date: Mon, 07 Oct 2024 16:03:37 +0200 Subject: [PATCH v3 1/3] dt-bindings: mmc: controller: move properties common with slot out to mmc-controller-common Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241007-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v3-1-ad4eb22c2a8d@linaro.org> References: <20241007-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v3-0-ad4eb22c2a8d@linaro.org> In-Reply-To: <20241007-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v3-0-ad4eb22c2a8d@linaro.org> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Move the common MMC "slot" properties because they are shared by the single-slot or multi-slot controllers, and will help defining a simple mmc-slot bindings document with proper slot properties and nodename. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring (Arm) --- .../bindings/mmc/mmc-controller-common.yaml | 357 +++++++++++++++++++++ .../devicetree/bindings/mmc/mmc-controller.yaml | 344 +------------------- 2 files changed, 360 insertions(+), 341 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml new file mode 100644 index 000000000000..e02d3cbcc271 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -0,0 +1,357 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MMC Controller & Slots Common Properties + +maintainers: + - Ulf Hansson + +description: | + These properties are common to multiple MMC host controllers and the + possible slots or ports for multi-slot controllers. + +properties: + "#address-cells": + const: 1 + description: | + The cell is the slot ID if a function subnode is used. + + "#size-cells": + const: 0 + + # Card Detection. + # If none of these properties are supplied, the host native card + # detect will be used. Only one of them should be provided. + + broken-cd: + $ref: /schemas/types.yaml#/definitions/flag + description: + There is no card detection available; polling must be used. + + cd-gpios: + maxItems: 1 + description: + The card detection will be done using the GPIO provided. + + non-removable: + $ref: /schemas/types.yaml#/definitions/flag + description: + Non-removable slot (like eMMC); assume always present. + + # *NOTE* on CD and WP polarity. To use common for all SD/MMC host + # controllers line polarity properties, we have to fix the meaning + # of the "normal" and "inverted" line levels. We choose to follow + # the SDHCI standard, which specifies both those lines as "active + # low." Therefore, using the "cd-inverted" property means, that the + # CD line is active high, i.e. it is high, when a card is + # inserted. Similar logic applies to the "wp-inverted" property. + # + # CD and WP lines can be implemented on the hardware in one of two + # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or + # as dedicated pins. Polarity of dedicated pins can be specified, + # using *-inverted properties. GPIO polarity can also be specified + # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the + # latter case. We choose to use the XOR logic for GPIO CD and WP + # lines. This means, the two properties are "superimposed," for + # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the + # respective *-inverted property property results in a + # double-inversion and actually means the "normal" line polarity is + # in effect. + wp-inverted: + $ref: /schemas/types.yaml#/definitions/flag + description: + The Write Protect line polarity is inverted. + + cd-inverted: + $ref: /schemas/types.yaml#/definitions/flag + description: + The CD line polarity is inverted. + + # Other properties + + bus-width: + description: + Number of data lines. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 4, 8] + default: 1 + + max-frequency: + description: | + Maximum operating frequency of the bus: + - for eMMC, the maximum supported frequency is 200MHz, + - for SD/SDIO cards the SDR104 mode has a max supported + frequency of 208MHz, + - some mmc host controllers do support a max frequency upto + 384MHz. + So, lets keep the maximum supported value here. + + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 400000 + maximum: 384000000 + + disable-wp: + $ref: /schemas/types.yaml#/definitions/flag + description: + When set, no physical write-protect line is present. This + property should only be specified when the controller has a + dedicated write-protect detection logic. If a GPIO is always used + for the write-protect detection logic, it is sufficient to not + specify the wp-gpios property in the absence of a write-protect + line. Not used in combination with eMMC or SDIO. + + wp-gpios: + maxItems: 1 + description: + GPIO to use for the write-protect detection. + + cd-debounce-delay-ms: + description: + Set delay time before detecting card after card insert + interrupt. + + no-1-8-v: + $ref: /schemas/types.yaml#/definitions/flag + description: + When specified, denotes that 1.8V card voltage is not supported + on this system, even if the controller claims it. + + cap-sd-highspeed: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD high-speed timing is supported. + + cap-mmc-highspeed: + $ref: /schemas/types.yaml#/definitions/flag + description: + MMC high-speed timing is supported. + + sd-uhs-sdr12: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR12 speed is supported. + + sd-uhs-sdr25: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR25 speed is supported. + + sd-uhs-sdr50: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR50 speed is supported. + + sd-uhs-sdr104: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS SDR104 speed is supported. + + sd-uhs-ddr50: + $ref: /schemas/types.yaml#/definitions/flag + description: + SD UHS DDR50 speed is supported. + + cap-power-off-card: + $ref: /schemas/types.yaml#/definitions/flag + description: + Powering off the card is safe. + + cap-mmc-hw-reset: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC hardware reset is supported + + cap-sdio-irq: + $ref: /schemas/types.yaml#/definitions/flag + description: + enable SDIO IRQ signalling on this interface + + full-pwr-cycle: + $ref: /schemas/types.yaml#/definitions/flag + description: + Full power cycle of the card is supported. + + full-pwr-cycle-in-suspend: + $ref: /schemas/types.yaml#/definitions/flag + description: + Full power cycle of the card in suspend is supported. + + mmc-ddr-1_2v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC high-speed DDR mode (1.2V I/O) is supported. + + mmc-ddr-1_8v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC high-speed DDR mode (1.8V I/O) is supported. + + mmc-ddr-3_3v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC high-speed DDR mode (3.3V I/O) is supported. + + mmc-hs200-1_2v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS200 mode (1.2V I/O) is supported. + + mmc-hs200-1_8v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS200 mode (1.8V I/O) is supported. + + mmc-hs400-1_2v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS400 mode (1.2V I/O) is supported. + + mmc-hs400-1_8v: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS400 mode (1.8V I/O) is supported. + + mmc-hs400-enhanced-strobe: + $ref: /schemas/types.yaml#/definitions/flag + description: + eMMC HS400 enhanced strobe mode is supported + + no-mmc-hs400: + $ref: /schemas/types.yaml#/definitions/flag + description: + All eMMC HS400 modes are not supported. + + dsr: + description: + Value the card Driver Stage Register (DSR) should be programmed + with. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xffff + + no-sdio: + $ref: /schemas/types.yaml#/definitions/flag + description: + Controller is limited to send SDIO commands during + initialization. + + no-sd: + $ref: /schemas/types.yaml#/definitions/flag + description: + Controller is limited to send SD commands during initialization. + + no-mmc: + $ref: /schemas/types.yaml#/definitions/flag + description: + Controller is limited to send MMC commands during + initialization. + + fixed-emmc-driver-type: + description: + For non-removable eMMC, enforce this driver type. The value is + the driver type as specified in the eMMC specification (table + 206 in spec version 5.1) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4 + + post-power-on-delay-ms: + description: + It was invented for MMC pwrseq-simple which could be referred to + mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay + waiting for I/O signalling and card power supply to be stable, + regardless of whether pwrseq-simple is used. Default to 10ms if + no available. + default: 10 + + supports-cqe: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates that the corresponding + MMC host controller supports HW command queue feature. + + disable-cqe-dcmd: + $ref: /schemas/types.yaml#/definitions/flag + description: + The presence of this property indicates that the MMC + controller\'s command queue engine (CQE) does not support direct + commands (DCMDs). + + keep-power-in-suspend: + $ref: /schemas/types.yaml#/definitions/flag + description: + SDIO only. Preserves card power during a suspend/resume cycle. + + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: + SDIO only. Enables wake up of host system on SDIO IRQ assertion. + + vmmc-supply: + description: + Supply for the card power + + vqmmc-supply: + description: + Supply for the bus IO line power, such as a level shifter. + If the level shifter is controlled by a GPIO line, this shall + be modeled as a "regulator-fixed" with a GPIO line for + switching the level shifter on/off. + + mmc-pwrseq: + $ref: /schemas/types.yaml#/definitions/phandle + description: + System-on-Chip designs may specify a specific MMC power + sequence. To successfully detect an (e)MMC/SD/SDIO card, that + power sequence must be maintained while initializing the card. + +patternProperties: + "^.*@[0-9]+$": + type: object + description: | + On embedded systems the cards connected to a host may need + additional properties. These can be specified in subnodes to the + host controller node. The subnodes are identified by the + standard \'reg\' property. Which information exactly can be + specified depends on the bindings for the SDIO function driver + for the subnode, as specified by the compatible string. + + properties: + compatible: + description: | + Name of SDIO function following generic names recommended + practice + + reg: + items: + - minimum: 0 + maximum: 7 + description: + Must contain the SDIO function number of the function this + subnode describes. A value of 0 denotes the memory SD + function, values from 1 to 7 denote the SDIO functions. + + required: + - reg + + "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$": + $ref: /schemas/types.yaml#/definitions/uint32-array + + minItems: 2 + maxItems: 2 + items: + minimum: 0 + maximum: 359 + description: + Set the clock (phase) delays which are to be configured in the + controller while switching to particular speed mode. These values + are in pair of degrees. + +dependencies: + cd-debounce-delay-ms: [ cd-gpios ] + fixed-emmc-driver-type: [ non-removable ] + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 58ae298cd2fc..99c01ce318d3 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -18,351 +18,13 @@ description: | (and the corresponding mmcblkN devices) by defining an alias in the /aliases device tree node. +$ref: mmc-controller-common.yaml# + properties: $nodename: pattern: "^mmc(@.*)?$" - "#address-cells": - const: 1 - description: | - The cell is the slot ID if a function subnode is used. - - "#size-cells": - const: 0 - - # Card Detection. - # If none of these properties are supplied, the host native card - # detect will be used. Only one of them should be provided. - - broken-cd: - $ref: /schemas/types.yaml#/definitions/flag - description: - There is no card detection available; polling must be used. - - cd-gpios: - maxItems: 1 - description: - The card detection will be done using the GPIO provided. - - non-removable: - $ref: /schemas/types.yaml#/definitions/flag - description: - Non-removable slot (like eMMC); assume always present. - - # *NOTE* on CD and WP polarity. To use common for all SD/MMC host - # controllers line polarity properties, we have to fix the meaning - # of the "normal" and "inverted" line levels. We choose to follow - # the SDHCI standard, which specifies both those lines as "active - # low." Therefore, using the "cd-inverted" property means, that the - # CD line is active high, i.e. it is high, when a card is - # inserted. Similar logic applies to the "wp-inverted" property. - # - # CD and WP lines can be implemented on the hardware in one of two - # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or - # as dedicated pins. Polarity of dedicated pins can be specified, - # using *-inverted properties. GPIO polarity can also be specified - # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the - # latter case. We choose to use the XOR logic for GPIO CD and WP - # lines. This means, the two properties are "superimposed," for - # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the - # respective *-inverted property property results in a - # double-inversion and actually means the "normal" line polarity is - # in effect. - wp-inverted: - $ref: /schemas/types.yaml#/definitions/flag - description: - The Write Protect line polarity is inverted. - - cd-inverted: - $ref: /schemas/types.yaml#/definitions/flag - description: - The CD line polarity is inverted. - - # Other properties - - bus-width: - description: - Number of data lines. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 4, 8] - default: 1 - - max-frequency: - description: | - Maximum operating frequency of the bus: - - for eMMC, the maximum supported frequency is 200MHz, - - for SD/SDIO cards the SDR104 mode has a max supported - frequency of 208MHz, - - some mmc host controllers do support a max frequency upto - 384MHz. - So, lets keep the maximum supported value here. - - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 400000 - maximum: 384000000 - - disable-wp: - $ref: /schemas/types.yaml#/definitions/flag - description: - When set, no physical write-protect line is present. This - property should only be specified when the controller has a - dedicated write-protect detection logic. If a GPIO is always used - for the write-protect detection logic, it is sufficient to not - specify the wp-gpios property in the absence of a write-protect - line. Not used in combination with eMMC or SDIO. - - wp-gpios: - maxItems: 1 - description: - GPIO to use for the write-protect detection. - - cd-debounce-delay-ms: - description: - Set delay time before detecting card after card insert - interrupt. - - no-1-8-v: - $ref: /schemas/types.yaml#/definitions/flag - description: - When specified, denotes that 1.8V card voltage is not supported - on this system, even if the controller claims it. - - cap-sd-highspeed: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD high-speed timing is supported. - - cap-mmc-highspeed: - $ref: /schemas/types.yaml#/definitions/flag - description: - MMC high-speed timing is supported. - - sd-uhs-sdr12: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR12 speed is supported. - - sd-uhs-sdr25: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR25 speed is supported. - - sd-uhs-sdr50: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR50 speed is supported. - - sd-uhs-sdr104: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS SDR104 speed is supported. - - sd-uhs-ddr50: - $ref: /schemas/types.yaml#/definitions/flag - description: - SD UHS DDR50 speed is supported. - - cap-power-off-card: - $ref: /schemas/types.yaml#/definitions/flag - description: - Powering off the card is safe. - - cap-mmc-hw-reset: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC hardware reset is supported - - cap-sdio-irq: - $ref: /schemas/types.yaml#/definitions/flag - description: - enable SDIO IRQ signalling on this interface - - full-pwr-cycle: - $ref: /schemas/types.yaml#/definitions/flag - description: - Full power cycle of the card is supported. - - full-pwr-cycle-in-suspend: - $ref: /schemas/types.yaml#/definitions/flag - description: - Full power cycle of the card in suspend is supported. - - mmc-ddr-1_2v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC high-speed DDR mode (1.2V I/O) is supported. - - mmc-ddr-1_8v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC high-speed DDR mode (1.8V I/O) is supported. - - mmc-ddr-3_3v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC high-speed DDR mode (3.3V I/O) is supported. - - mmc-hs200-1_2v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS200 mode (1.2V I/O) is supported. - - mmc-hs200-1_8v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS200 mode (1.8V I/O) is supported. - - mmc-hs400-1_2v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS400 mode (1.2V I/O) is supported. - - mmc-hs400-1_8v: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS400 mode (1.8V I/O) is supported. - - mmc-hs400-enhanced-strobe: - $ref: /schemas/types.yaml#/definitions/flag - description: - eMMC HS400 enhanced strobe mode is supported - - no-mmc-hs400: - $ref: /schemas/types.yaml#/definitions/flag - description: - All eMMC HS400 modes are not supported. - - dsr: - description: - Value the card Driver Stage Register (DSR) should be programmed - with. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 0xffff - - no-sdio: - $ref: /schemas/types.yaml#/definitions/flag - description: - Controller is limited to send SDIO commands during - initialization. - - no-sd: - $ref: /schemas/types.yaml#/definitions/flag - description: - Controller is limited to send SD commands during initialization. - - no-mmc: - $ref: /schemas/types.yaml#/definitions/flag - description: - Controller is limited to send MMC commands during - initialization. - - fixed-emmc-driver-type: - description: - For non-removable eMMC, enforce this driver type. The value is - the driver type as specified in the eMMC specification (table - 206 in spec version 5.1) - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 4 - - post-power-on-delay-ms: - description: - It was invented for MMC pwrseq-simple which could be referred to - mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay - waiting for I/O signalling and card power supply to be stable, - regardless of whether pwrseq-simple is used. Default to 10ms if - no available. - default: 10 - - supports-cqe: - $ref: /schemas/types.yaml#/definitions/flag - description: - The presence of this property indicates that the corresponding - MMC host controller supports HW command queue feature. - - disable-cqe-dcmd: - $ref: /schemas/types.yaml#/definitions/flag - description: - The presence of this property indicates that the MMC - controller\'s command queue engine (CQE) does not support direct - commands (DCMDs). - - keep-power-in-suspend: - $ref: /schemas/types.yaml#/definitions/flag - description: - SDIO only. Preserves card power during a suspend/resume cycle. - - wakeup-source: - $ref: /schemas/types.yaml#/definitions/flag - description: - SDIO only. Enables wake up of host system on SDIO IRQ assertion. - - vmmc-supply: - description: - Supply for the card power - - vqmmc-supply: - description: - Supply for the bus IO line power, such as a level shifter. - If the level shifter is controlled by a GPIO line, this shall - be modeled as a "regulator-fixed" with a GPIO line for - switching the level shifter on/off. - - mmc-pwrseq: - $ref: /schemas/types.yaml#/definitions/phandle - description: - System-on-Chip designs may specify a specific MMC power - sequence. To successfully detect an (e)MMC/SD/SDIO card, that - power sequence must be maintained while initializing the card. - -patternProperties: - "^.*@[0-9]+$": - type: object - description: | - On embedded systems the cards connected to a host may need - additional properties. These can be specified in subnodes to the - host controller node. The subnodes are identified by the - standard \'reg\' property. Which information exactly can be - specified depends on the bindings for the SDIO function driver - for the subnode, as specified by the compatible string. - - properties: - compatible: - description: | - Name of SDIO function following generic names recommended - practice - - reg: - items: - - minimum: 0 - maximum: 7 - description: - Must contain the SDIO function number of the function this - subnode describes. A value of 0 denotes the memory SD - function, values from 1 to 7 denote the SDIO functions. - - required: - - reg - - "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$": - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 2 - maxItems: 2 - items: - minimum: 0 - maximum: 359 - description: - Set the clock (phase) delays which are to be configured in the - controller while switching to particular speed mode. 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the mmc-slot, which is a subnode of a multi-slot MMC controller, each slot is represented as a full MMC controller, the top node handling all the shared resources and slot mux. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/mmc/mmc-slot.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mmc-slot.yaml b/Documentation/devicetree/bindings/mmc/mmc-slot.yaml new file mode 100644 index 000000000000..1f0667828063 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-slot.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mmc-slot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MMC slot properties + +maintainers: + - Ulf Hansson + +description: + These properties defines slot properties for MMC controlers that + have multiple slots or ports provided by the same controller and + sharing the same resources. + +$ref: mmc-controller-common.yaml# + +properties: + $nodename: + pattern: "^slot(@.*)?$" + + compatible: + const: mmc-slot + + reg: + description: + the slot (or "port") ID + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mmc { + #address-cells = <1>; + #size-cells = <0>; + slot@0 { + compatible = "mmc-slot"; + reg = <0>; + bus-width = <4>; + }; + }; + +... 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Mon, 07 Oct 2024 07:03:43 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d1688a486sm5857022f8f.0.2024.10.07.07.03.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2024 07:03:43 -0700 (PDT) From: Neil Armstrong Date: Mon, 07 Oct 2024 16:03:39 +0200 Subject: [PATCH v3 3/3] dt-bindings: mmc: convert amlogic,meson-mx-sdio.txt to dtschema Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241007-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v3-3-ad4eb22c2a8d@linaro.org> References: <20241007-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v3-0-ad4eb22c2a8d@linaro.org> In-Reply-To: <20241007-topic-amlogic-arm32-upstream-bindings-fixes-convert-meson-mx-sdio-v3-0-ad4eb22c2a8d@linaro.org> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Convert the Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller bindings to dt-schema. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring (Arm) Reviewed-by: Martin Blumenstingl --- .../bindings/mmc/amlogic,meson-mx-sdio.txt | 54 ------------- .../bindings/mmc/amlogic,meson-mx-sdio.yaml | 94 ++++++++++++++++++++++ 2 files changed, 94 insertions(+), 54 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt deleted file mode 100644 index 8765c605e6bc..000000000000 --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.txt +++ /dev/null @@ -1,54 +0,0 @@ -* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller - -The highspeed MMC host controller on Amlogic SoCs provides an interface -for MMC, SD, SDIO and SDHC types of memory cards. - -Supported maximum speeds are the ones of the eMMC standard 4.41 as well -as the speed of SD standard 2.0. - -The hardware provides an internal "mux" which allows up to three slots -to be controlled. Only one slot can be accessed at a time. - -Required properties: - - compatible : must be one of - - "amlogic,meson8-sdio" - - "amlogic,meson8b-sdio" - along with the generic "amlogic,meson-mx-sdio" - - reg : mmc controller base registers - - interrupts : mmc controller interrupt - - #address-cells : must be 1 - - size-cells : must be 0 - - clocks : phandle to clock providers - - clock-names : must contain "core" and "clkin" - -Required child nodes: -A node for each slot provided by the MMC controller is required. -NOTE: due to a driver limitation currently only one slot (= child node) - is supported! - -Required properties on each child node (= slot): - - compatible : must be "mmc-slot" (see mmc.txt within this directory) - - reg : the slot (or "port") ID - -Optional properties on each child node (= slot): - - bus-width : must be 1 or 4 (8-bit bus is not supported) - - for cd and all other additional generic mmc parameters - please refer to mmc.txt within this directory - -Examples: - mmc@c1108c20 { - compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; - reg = <0xc1108c20 0x20>; - interrupts = <0 28 1>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; - clock-names = "core", "clkin"; - - slot@1 { - compatible = "mmc-slot"; - reg = <1>; - - bus-width = <4>; - }; - }; diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml new file mode 100644 index 000000000000..022682a977c6 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-mx-sdio.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller + +description: | + The highspeed MMC host controller on Amlogic SoCs provides an interface + for MMC, SD, SDIO and SDHC types of memory cards. + + Supported maximum speeds are the ones of the eMMC standard 4.41 as well + as the speed of SD standard 2.0. + + The hardware provides an internal "mux" which allows up to three slots + to be controlled. Only one slot can be accessed at a time. + +maintainers: + - Neil Armstrong + +properties: + compatible: + items: + - enum: + - amlogic,meson8-sdio + - amlogic,meson8b-sdio + - const: amlogic,meson-mx-sdio + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: clkin + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "slot@[0-2]$": + $ref: mmc-slot.yaml# + description: + A node for each slot provided by the MMC controller + + properties: + reg: + enum: [0, 1, 2] + + bus-width: + enum: [1, 4] + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + mmc@c1108c20 { + compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; + reg = <0xc1108c20 0x20>; + interrupts = ; + clocks = <&clk_core>, <&clk_in>; + clock-names = "core", "clkin"; + #address-cells = <1>; + #size-cells = <0>; + + slot@1 { + compatible = "mmc-slot"; + reg = <1>; + bus-width = <4>; + }; + };