From patchwork Tue Oct 8 06:15:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 13826350 Received: from mail-m92248.xmail.ntesmail.com (mail-m92248.xmail.ntesmail.com [103.126.92.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C41511D4141; Tue, 8 Oct 2024 11:41:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.126.92.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728387715; cv=none; b=gNRqOsnq3fK5AUDilR6xnvcBg8QKaXmjcAigTgwtS4J2hFLlotFMGq4N0uAo0FDtD3hW+AJcgXk0ty+m5IGdc8w+pqDXApdu1/lLVxdtcZscIGU9enXJMGDvmSGvZNGXg1c2SFOHBx2k2Z6Mxn4y1CLxnW3o5B7nB4SJYmOuTl0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728387715; c=relaxed/simple; bh=S6XkNkmuedD1pQiaxwUmsamoq7LhM5melxm3Vc1eKDQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=MHs0HvDaKGlb2Djz3wqmSGvc4gN9vomFE6rhU3RD3QnqEIVv4bNel3GUNjHBSC+7TD50n5HnDyVje9UTgywW5ovexflM/kghupoPDurpkRVvibHaOZNd4d7MutiQR1U4vh12YQEL90QoTEZlp8SrP6YZJQfkcGIbJE8kZwQng6E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=HRYrF1OG; arc=none smtp.client-ip=103.126.92.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="HRYrF1OG" DKIM-Signature: a=rsa-sha256; b=HRYrF1OGMwGO2XCvcjO7vadF6OFvDsh/Ue7CpxudlEzsKrt1kuwoGsQw/zm3nrOPRuIITH7Rns0atrp3Q9tJ0LF2jEPXelDJLPv8jlOg/jTgSm5UCe3KE4qOicBCwB9l4D2An2mdIbI7hp0lK3YRTi/MZhG3S8E2bv10ej/Ua+M=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=nOR0BMICsxKcbiEHiB0O1t4LWarRiz326TLSWeKN3ho=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTPA id 83B8052075A; Tue, 8 Oct 2024 14:16:07 +0800 (CST) From: Shawn Lin To: Rob Herring , "James E . J . Bottomley" , "Martin K . Petersen" , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Heiko Stuebner Cc: Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , YiFeng Zhao , Liang Chen , linux-scsi@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Shawn Lin Subject: [PATCH v3 1/5] scsi: ufs: core: Add UFSHCI_QUIRK_DME_RESET_ENABLE_AFTER_HCE Date: Tue, 8 Oct 2024 14:15:26 +0800 Message-Id: <1728368130-37213-2-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> References: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQhhCS1ZDTE9LS01MHx8dSkNWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a926ac54e3703afkunm83b8052075a X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Nkk6TRw4MzIZFBYwNzYCDTga AjMwChdVSlVKTElDSE1DSk1CS01JVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQU9IQkk3Bg++ Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: HCE on Rockchip SoC is different from both of ufshcd_hba_execute_hce() and UFSHCI_QUIRK_BROKEN_HCE case. It need to do dme_reset and dme_enable after enabling HCE. So in order not to abuse UFSHCI_QUIRK_BROKEN_HCE, add a new quirk UFSHCI_QUIRK_DME_RESET_ENABLE_AFTER_HCE, to deal with that limitation. Suggested-by: Manivannan Sadhasivam Signed-off-by: Shawn Lin --- Changes in v3: None Changes in v2: None drivers/ufs/core/ufshcd.c | 17 +++++++++++++++++ include/ufs/ufshcd.h | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 7cab1031..4868099 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -4819,6 +4819,7 @@ static int ufshcd_hba_execute_hce(struct ufs_hba *hba) { int retry_outer = 3; int retry_inner; + int ret; start: if (ufshcd_is_hba_active(hba)) @@ -4865,6 +4866,22 @@ static int ufshcd_hba_execute_hce(struct ufs_hba *hba) /* enable UIC related interrupts */ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); + /* + * Do dme_reset and dme_enable if a UFS host controller need + * this procedure to actually finish HCE. + */ + if (hba->quirks & UFSHCI_QUIRK_DME_RESET_ENABLE_AFTER_HCE) { + ret = ufshcd_dme_reset(hba); + if (!ret) { + ret = ufshcd_dme_enable(hba); + if (ret) + dev_err(hba->dev, + "Failed to do dme_enable after HCE.\n"); + } else { + dev_err(hba->dev, "Failed to do dme_reset after HCE.\n"); + } + } + ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); return 0; diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index a95282b..73b888f 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -685,6 +685,12 @@ enum ufshcd_quirks { * single doorbell mode. */ UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25, + + /* + * This quirks needs to be enabled if host controller need to + * do dme_reset and dme_enable after hce. + */ + UFSHCI_QUIRK_DME_RESET_ENABLE_AFTER_HCE = 1 << 26, }; enum ufshcd_caps { From patchwork Tue Oct 8 06:15:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 13826352 Received: from mail-m92248.xmail.ntesmail.com (mail-m92248.xmail.ntesmail.com [103.126.92.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 533EF1D54E9; Tue, 8 Oct 2024 11:41:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.126.92.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728387716; cv=none; b=sUKsiIMRpC0/f/vRNT8OW7LiZoYPBWxg9/Y6+1vZ7ibls2EgOEfsKkqd6pzWfGodkRQLLrCZ0PzxeEcVVFKPI7oirHbpjAxXeNWRSGPCOn6GldQPc5yNrfpTtGSYlI96ayCcORhg51dA91iF/PW20Bw7hoZOnSIowBnNfQ0+Bxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728387716; c=relaxed/simple; bh=hL20nF2GAbPt9Dmwz+lPbghO14iAkuDz4HsVtgYryxI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=TM1iKSa/zlw+ONbG8Fay8zL32XLC3LGjaCOZrGn2/C4zFcgif4oWvFLXuc0/wRZ/GM2KoYgI4+kPwUKQGy8URILHy/8JVjD3nZJsSp0QNNodso2pLPHzU2OtCBlttR+qcuSfCVf7rEtgi+019967oKgeLgCa5IkJgf4VeSX8jug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=fh1AmXna; arc=none smtp.client-ip=103.126.92.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="fh1AmXna" DKIM-Signature: a=rsa-sha256; b=fh1AmXna3dWoxzFU4RxBgDi5rzS2EakRqgGDDynXI9227yQ9eIBR27lHCmLwl2iPcgFqFjkZcF3jcl0TJoJb9gZs7+kfajA9nK6l0j2X1IGrLyFmPm0k/itRXLu7fdRhkexETurGHQzYA/IN1fzXsrhiYNU3dodcL3UoVgUc1/I=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=AXK3YnjXax5rcpF78zMigMzTMhZlDrdMm0wDQmoO/X8=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTPA id 0B25B52057A; Tue, 8 Oct 2024 14:16:23 +0800 (CST) From: Shawn Lin To: Rob Herring , "James E . J . Bottomley" , "Martin K . Petersen" , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Heiko Stuebner Cc: Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , YiFeng Zhao , Liang Chen , linux-scsi@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Shawn Lin Subject: [PATCH v3 2/5] dt-bindings: ufs: Document Rockchip UFS host controller Date: Tue, 8 Oct 2024 14:15:27 +0800 Message-Id: <1728368130-37213-3-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> References: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQ0IfT1ZKSEIdSxhKH0lKGk5WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a926ac58ea403afkunm0b25b52057a X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6ND46Ejo5EzItLhY8GSwYNyg9 SgEwCylVSlVKTElDSE1DSkNOTEpPVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQU5DS0g3Bg++ Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Document Rockchip UFS host controller for RK3576 SoC. Signed-off-by: Shawn Lin Reviewed-by: Krzysztof Kozlowski --- Changes in v3: - rename the file to rockchip,rk3576-ufshc.yaml - add description for reset-gpios - use rockchip,rk3576-ufshc as compatible Changes in v2: - rename the file - add reset-gpios .../bindings/ufs/rockchip,rk3576-ufshc.yaml | 103 +++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml diff --git a/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml new file mode 100644 index 0000000..1c78ea5 --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/rockchip,rk3576-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip UFS Host Controller + +maintainers: + - Shawn Lin + +allOf: + - $ref: ufs-common.yaml + +properties: + compatible: + const: rockchip,rk3576-ufshc + + reg: + maxItems: 5 + + reg-names: + items: + - const: hci + - const: mphy + - const: hci_grf + - const: mphy_grf + - const: hci_apb + + clocks: + maxItems: 4 + + clock-names: + items: + - const: core + - const: pclk + - const: pclk_mphy + - const: ref_out + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: biu + - const: sys + - const: ufs + - const: grf + + reset-gpios: + maxItems: 1 + description: | + GPIO specifiers for host to reset the device. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - power-domains + - resets + - reset-names + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ufs: ufs@2a2d0000 { + compatible = "rockchip,rk3576-ufshc"; + reg = <0x0 0x2a2d0000 0x0 0x10000>, + <0x0 0x2b040000 0x0 0x10000>, + <0x0 0x2601f000 0x0 0x1000>, + <0x0 0x2603c000 0x0 0x1000>, + <0x0 0x2a2e0000 0x0 0x10000>; + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, + <&cru CLK_REF_UFS_CLKOUT>; + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; + interrupts = ; + power-domains = <&power RK3576_PD_USB>; + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, + <&cru SRST_P_UFS_GRF>; + reset-names = "biu", "sys", "ufs", "grf"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + }; + }; From patchwork Tue Oct 8 06:15:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 13826692 Received: from mail-m2418.xmail.ntesmail.com (mail-m2418.xmail.ntesmail.com [45.195.24.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FA6C1D31A0; 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J . Bottomley" , "Martin K . Petersen" , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Heiko Stuebner Cc: Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , YiFeng Zhao , Liang Chen , linux-scsi@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Shawn Lin Subject: [PATCH v3 3/5] soc: rockchip: add header for suspend mode SIP interface Date: Tue, 8 Oct 2024 14:15:28 +0800 Message-Id: <1728368130-37213-4-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> References: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkJPTVZOGhlCThpCT0hMSkxWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a926ac5b36903afkunm7081f520718 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MRg6GBw5GjIvNhYOTi1MNw1W Ex8aCQpVSlVKTElDSE1DSkJOS0pJVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhKQ0o3Bg++ Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add ROCKCHIP_SIP_SUSPEND_MODE to pass down parameters to Trusted Firmware in order to decide suspend mode. Currently only add ROCKCHIP_SLEEP_PD_CONFIG which teaches firmware to power down controllers or not. Signed-off-by: Shawn Lin --- Changes in v3: None Changes in v2: None include/soc/rockchip/rockchip_sip.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h index c46a9ae..501ad1f 100644 --- a/include/soc/rockchip/rockchip_sip.h +++ b/include/soc/rockchip/rockchip_sip.h @@ -6,6 +6,9 @@ #ifndef __SOC_ROCKCHIP_SIP_H #define __SOC_ROCKCHIP_SIP_H +#define ROCKCHIP_SIP_SUSPEND_MODE 0x82000003 +#define ROCKCHIP_SLEEP_PD_CONFIG 0xff + #define ROCKCHIP_SIP_DRAM_FREQ 0x82000008 #define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01 From patchwork Tue Oct 8 06:15:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 13826351 Received: from mail-m92248.xmail.ntesmail.com (mail-m92248.xmail.ntesmail.com [103.126.92.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3970D1D54D3; Tue, 8 Oct 2024 11:41:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.126.92.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728387716; cv=none; b=VQbUy4R8lySkjkhKpEtzJJHJxbL1kyAh1j0+v6HX5pytTMO5z7IVskH9sKwMmtuQfO/4+6tIl4MxTstn7ASr+FCsJMxlTjDN0CRnx+PjxNl3Ofj57UgwuGNYz1+GFwZaWIYR6BvtJLMO6/pU40QA7p0Ji/XkV7J+SlKWO3YwooQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728387716; c=relaxed/simple; bh=wFKvfRRQoBJZqY0ukQccdKGlX0xobNOL4S/eBEm4eb0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=bV+e6cnbdaO4eUGjaAA0KzvWG1HzbGoupBO7XVvXz2NGnx9iUQU222seNfsIFz7ZpAoDfRYTKqluAs8tvQ2VP8Vq2OY8LilsjhZEj6W1xg9tnnvyQ6i8CX+aFaI/fhCxVMVKANXOmFysRT3XTIwr8CzeHTRO2P/bcvkpaN6G64E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=CUV9JQ6T; arc=none smtp.client-ip=103.126.92.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="CUV9JQ6T" DKIM-Signature: a=rsa-sha256; b=CUV9JQ6TT2aQrm0e8FD1ZsjGt5wb9K9sADQwmJlXb7ulBtlgwtlT3cghiWc4PhQ5mIHuB1TBC0zBEtj18UGFnduRctYHYxlSd2q9KnHggh/bAKvKW0bTzjm6/6KY9TTdz5PLjDz/I7IXTaGVQKYu13qnH+HqRJ5crGaLDkBgsSM=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=sDFPfh0ntBvyHdRIGFyGIID/VxPyFOd/6skrF31OfxY=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTPA id 2C382520783; Tue, 8 Oct 2024 14:16:40 +0800 (CST) From: Shawn Lin To: Rob Herring , "James E . J . Bottomley" , "Martin K . Petersen" , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Heiko Stuebner Cc: Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , YiFeng Zhao , Liang Chen , linux-scsi@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Shawn Lin Subject: [PATCH v3 4/5] soc: rockchip: power-domain: Add GENPD_FLAG_RPM_ALWAYS_ON support Date: Tue, 8 Oct 2024 14:15:29 +0800 Message-Id: <1728368130-37213-5-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> References: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGh5MHVZKGEoeS0lPTE0ZShlWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a926ac5cda303afkunm2c382520783 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PDI6Kzo5LTItDBYrGSMhN00u CxMaCwpVSlVKTElDSE1DSUtKQkNMVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhLQ003Bg++ Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: If low level driver claims to keep its own power domain always on, let pd driver respect the flag of GENPD_FLAG_RPM_ALWAYS_ON. Signed-off-by: Shawn Lin --- Changes in v3: None Changes in v2: None drivers/pmdomain/rockchip/pm-domains.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c index cb0f938..b2bb458 100644 --- a/drivers/pmdomain/rockchip/pm-domains.c +++ b/drivers/pmdomain/rockchip/pm-domains.c @@ -621,6 +621,9 @@ static int rockchip_pd_power_off(struct generic_pm_domain *domain) { struct rockchip_pm_domain *pd = to_rockchip_pd(domain); + if (pd->genpd.flags & GENPD_FLAG_RPM_ALWAYS_ON) + return 0; + return rockchip_pd_power(pd, false); } From patchwork Tue Oct 8 06:15:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 13826848 Received: from mail-m243.xmail.ntesmail.com (mail-m243.xmail.ntesmail.com [45.195.24.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 899E6136982; Tue, 8 Oct 2024 18:41:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.195.24.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728412915; cv=none; b=rdraYYZp4f1afQxok57JF2tQ7VmqIYEoO77ZoWmngaS2LShA7OOKNUaxSg+vPdheKPbQZgUfmGRggwDJSoXuKKiqz2wSyflN7gcwz+CwthFeUewYCumZbMmowRLagB8/l4MnaNxpa1PLBPufR5M/+fK8vaKLnZPFdojBsBwI4Bg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728412915; c=relaxed/simple; bh=w9JUd73/2EICDe/cSsk8RvY0nQgd1bm6MZBTj7sGgd8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=uB8IRRsl3M2ysaY6YShT3hX3tl5Itp+QhqRDO1sgeoKLYvQc7WOcOUMeObo6N10kmrcjfP80OhcFgBiAaaWYH2/ED4wk/2vCWkAgVqhtH3QOcNpdY2BUziqpJLXlyfcmYsuTLvot38Djjn9evySsAtUn2656bYrd2URFSK6fDYA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=PxwxeKuI; arc=none smtp.client-ip=45.195.24.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="PxwxeKuI" DKIM-Signature: a=rsa-sha256; b=PxwxeKuIR3y5+xsbeqEYm/n/7VtM2yDszZP3Lm9CB4xk/oJKcHEWeN6/ce+/lPVEZ1v1cwV/5HXhDnLWRJ9fspHX0lw4gtU6w0rare398q9bUZtI4dU0Jf3T0+eNqD/n/oQF/CwicF1b5BZIJP24JjmtlVykw2W40FGB+LOavh4=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=sphq7VT177lwXyPzZxdvggixhJey8IJxX7+GPwoLk6k=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTPA id 497205201FC; Tue, 8 Oct 2024 14:16:44 +0800 (CST) From: Shawn Lin To: Rob Herring , "James E . J . Bottomley" , "Martin K . Petersen" , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Heiko Stuebner Cc: Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , YiFeng Zhao , Liang Chen , linux-scsi@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Shawn Lin Subject: [PATCH v3 5/5] scsi: ufs: rockchip: initial support for UFS Date: Tue, 8 Oct 2024 14:15:30 +0800 Message-Id: <1728368130-37213-6-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> References: <1728368130-37213-1-git-send-email-shawn.lin@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGR5LQ1ZMTUlNHk5DSkNJShlWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCSE NVSktLVUpCS0tZBg++ X-HM-Tid: 0a926ac5ddba03afkunm497205201fc X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PUk6Hjo5MjIeCBYDNy5RN0gs LQgKCytVSlVKTElDSE1DSUtNSkhIVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUpDSU5DNwY+ Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: RK3576 SoC contains a UFS controller, add initial support fot it. The features are: (1) support UFS 2.0 features (2) High speed up to HS-G3 (3) 2RX-2TX lanes (4) auto H8 entry and exit Software limitation: (1) HCE procedure: enbale controller->enbale intr->dme_reset->dme_enable (2) disable unipro timeout values before power mode change Signed-off-by: Shawn Lin --- Changes in v3: - reword Kconfig description - elaborate more about controller in commit msg - use rockchip,rk3576-ufshc for compatible - remove useless header file - remove inline for ufshcd_is_device_present - use usleep_range instead - remove initialization, reverse Xmas order - remove useless varibles - check vops for null - other small fixes for err path - remove pm_runtime_set_active - fix the active and inactive reset-gpios logic - fix rpm_lvl and spm_lvl to 5 and move to end of probe path - remove unnecessary system PM callbacks - use UFSHCI_QUIRK_DME_RESET_ENABLE_AFTER_HCE instead of UFSHCI_QUIRK_BROKEN_HCE Changes in v2: None drivers/ufs/host/Kconfig | 12 ++ drivers/ufs/host/Makefile | 1 + drivers/ufs/host/ufs-rockchip.c | 346 ++++++++++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-rockchip.h | 51 ++++++ 4 files changed, 410 insertions(+) create mode 100644 drivers/ufs/host/ufs-rockchip.c create mode 100644 drivers/ufs/host/ufs-rockchip.h diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig index 580c8d0..191fbd7 100644 --- a/drivers/ufs/host/Kconfig +++ b/drivers/ufs/host/Kconfig @@ -142,3 +142,15 @@ config SCSI_UFS_SPRD Select this if you have UFS controller on Unisoc chipset. If unsure, say N. + +config SCSI_UFS_ROCKCHIP + tristate "Rockchip UFS host controller driver" + depends on SCSI_UFSHCD_PLATFORM && (ARCH_ROCKCHIP || COMPILE_TEST) + help + This selects the Rockchip specific additions to UFSHCD platform driver. + UFS host on Rockchip needs some vendor specific configuration before + accessing the hardware which includes PHY configuration and vendor + specific registers. + + Select this if you have UFS controller on Rockchip chipset. + If unsure, say N. diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile index 4573aea..2f97feb 100644 --- a/drivers/ufs/host/Makefile +++ b/drivers/ufs/host/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o +obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o diff --git a/drivers/ufs/host/ufs-rockchip.c b/drivers/ufs/host/ufs-rockchip.c new file mode 100644 index 0000000..98bd646 --- /dev/null +++ b/drivers/ufs/host/ufs-rockchip.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Rockchip UFS Host Controller driver + * + * Copyright (C) 2024 Rockchip Electronics Co.Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "ufshcd-pltfrm.h" +#include "ufs-rockchip.h" + +static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + int err = 0; + + if (status == POST_CHANGE) + err = ufshcd_vops_phy_initialization(hba); + + return err; +} + +static void ufs_rockchip_set_pm_lvl(struct ufs_hba *hba) +{ + hba->rpm_lvl = UFS_PM_LVL_5; + hba->spm_lvl = UFS_PM_LVL_5; +} + +static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba) +{ + struct ufs_rockchip_host *host = ufshcd_get_variant(hba); + + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0); + /* enable the mphy DME_SET cfg */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x200, 0x0), 0x40); + for (int i = 0; i < 2; i++) { + /* Configuration M-TX */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, SEL_TX_LANE0 + i), 0x06); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, SEL_TX_LANE0 + i), 0x02); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, SEL_TX_LANE0 + i), 0x44); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, SEL_TX_LANE0 + i), 0xe6); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, SEL_TX_LANE0 + i), 0x07); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x94, SEL_TX_LANE0 + i), 0x93); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x93, SEL_TX_LANE0 + i), 0xc9); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7f, SEL_TX_LANE0 + i), 0x00); + /* Configuration M-RX */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, SEL_RX_LANE0 + i), 0x06); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, SEL_RX_LANE0 + i), 0x00); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, SEL_RX_LANE0 + i), 0x58); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, SEL_RX_LANE0 + i), 0x8c); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, SEL_RX_LANE0 + i), 0x02); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, SEL_RX_LANE0 + i), 0xf6); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, SEL_RX_LANE0 + i), 0x69); + } + /* disable the mphy DME_SET cfg */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x200, 0x0), 0x00); + + ufs_sys_writel(host->mphy_base, 0x80, 0x08C); + ufs_sys_writel(host->mphy_base, 0xB5, 0x110); + ufs_sys_writel(host->mphy_base, 0xB5, 0x250); + + ufs_sys_writel(host->mphy_base, 0x03, 0x134); + ufs_sys_writel(host->mphy_base, 0x03, 0x274); + + ufs_sys_writel(host->mphy_base, 0x38, 0x0E0); + ufs_sys_writel(host->mphy_base, 0x38, 0x220); + + ufs_sys_writel(host->mphy_base, 0x50, 0x164); + ufs_sys_writel(host->mphy_base, 0x50, 0x2A4); + + ufs_sys_writel(host->mphy_base, 0x80, 0x178); + ufs_sys_writel(host->mphy_base, 0x80, 0x2B8); + + ufs_sys_writel(host->mphy_base, 0x18, 0x1B0); + ufs_sys_writel(host->mphy_base, 0x18, 0x2F0); + + ufs_sys_writel(host->mphy_base, 0x03, 0x128); + ufs_sys_writel(host->mphy_base, 0x03, 0x268); + + ufs_sys_writel(host->mphy_base, 0x20, 0x12C); + ufs_sys_writel(host->mphy_base, 0x20, 0x26C); + + ufs_sys_writel(host->mphy_base, 0xC0, 0x120); + ufs_sys_writel(host->mphy_base, 0xC0, 0x260); + + ufs_sys_writel(host->mphy_base, 0x03, 0x094); + + ufs_sys_writel(host->mphy_base, 0x03, 0x1B4); + ufs_sys_writel(host->mphy_base, 0x03, 0x2F4); + + ufs_sys_writel(host->mphy_base, 0xC0, 0x08C); + usleep_range(1, 2); + ufs_sys_writel(host->mphy_base, 0x00, 0x08C); + + usleep_range(200, 250); + /* start link up */ + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, 0), 0x1); + + return 0; +} + +static int ufs_rockchip_common_init(struct ufs_hba *hba) +{ + struct device *dev = hba->dev; + struct platform_device *pdev = to_platform_device(dev); + struct ufs_rockchip_host *host; + int err; + + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); + if (!host) + return -ENOMEM; + + /* system control register for hci */ + host->ufs_sys_ctrl = devm_platform_ioremap_resource_byname(pdev, "hci_grf"); + if (IS_ERR(host->ufs_sys_ctrl)) + return dev_err_probe(dev, PTR_ERR(host->ufs_sys_ctrl), + "cannot ioremap for hci system control register\n"); + + /* system control register for mphy */ + host->ufs_phy_ctrl = devm_platform_ioremap_resource_byname(pdev, "mphy_grf"); + if (IS_ERR(host->ufs_phy_ctrl)) + return dev_err_probe(dev, PTR_ERR(host->ufs_phy_ctrl), + "cannot ioremap for mphy system control register\n"); + + /* mphy base register */ + host->mphy_base = devm_platform_ioremap_resource_byname(pdev, "mphy"); + if (IS_ERR(host->mphy_base)) + return dev_err_probe(dev, PTR_ERR(host->mphy_base), + "cannot ioremap for mphy base register\n"); + + host->rst = devm_reset_control_array_get_exclusive(dev); + if (IS_ERR(host->rst)) + return dev_err_probe(dev, PTR_ERR(host->rst), + "failed to get reset control\n"); + + reset_control_assert(host->rst); + usleep_range(1, 2); + reset_control_deassert(host->rst); + + host->ref_out_clk = devm_clk_get_enabled(dev, "ref_out"); + if (IS_ERR(host->ref_out_clk)) + return dev_err_probe(dev, PTR_ERR(host->ref_out_clk), + "ref_out unavailable\n"); + + host->rst_gpio = devm_gpiod_get(&pdev->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(host->rst_gpio)) + return dev_err_probe(&pdev->dev, PTR_ERR(host->rst_gpio), + "invalid reset-gpios property in node\n"); + + host->clks[0].id = "core"; + host->clks[1].id = "pclk"; + host->clks[2].id = "pclk_mphy"; + err = devm_clk_bulk_get_optional(dev, UFS_MAX_CLKS, host->clks); + if (err) + return dev_err_probe(dev, err, "failed to get clocks\n"); + + err = clk_bulk_prepare_enable(UFS_MAX_CLKS, host->clks); + if (err) + return dev_err_probe(dev, err, "failed to enable clocks\n"); + + host->hba = hba; + + ufshcd_set_variant(hba, host); + + return 0; +} + +static int ufs_rockchip_rk3576_init(struct ufs_hba *hba) +{ + struct device *dev = hba->dev; + struct ufs_rockchip_host *host = ufshcd_get_variant(hba); + int ret; + + hba->quirks = UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING | + UFSHCI_QUIRK_DME_RESET_ENABLE_AFTER_HCE; + + /* Enable BKOPS when suspend */ + hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; + /* Enable putting device into deep sleep */ + hba->caps |= UFSHCD_CAP_DEEPSLEEP; + /* Enable devfreq of UFS */ + hba->caps |= UFSHCD_CAP_CLK_SCALING; + /* Enable WriteBooster */ + hba->caps |= UFSHCD_CAP_WB_EN; + + host->pd_id = RK3576_PD_UFS; + + ret = ufs_rockchip_common_init(hba); + if (ret) + return dev_err_probe(dev, ret, "ufs common init fail\n"); + + return 0; +} + +static int ufs_rockchip_device_reset(struct ufs_hba *hba) +{ + struct ufs_rockchip_host *host = ufshcd_get_variant(hba); + + /* Active the reset-gpios */ + gpiod_set_value_cansleep(host->rst_gpio, 1); + usleep_range(20, 25); + + /* Inactive the reset-gpios */ + gpiod_set_value_cansleep(host->rst_gpio, 0); + usleep_range(20, 25); + + return 0; +} + +static const struct ufs_hba_variant_ops ufs_hba_rk3576_vops = { + .name = "rk3576", + .init = ufs_rockchip_rk3576_init, + .device_reset = ufs_rockchip_device_reset, + .hce_enable_notify = ufs_rockchip_hce_enable_notify, + .phy_initialization = ufs_rockchip_rk3576_phy_init, +}; + +static const struct of_device_id ufs_rockchip_of_match[] = { + { .compatible = "rockchip,rk3576-ufshc", .data = &ufs_hba_rk3576_vops}, + {}, +}; +MODULE_DEVICE_TABLE(of, ufs_rockchip_of_match); + +static int ufs_rockchip_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct ufs_hba_variant_ops *vops; + struct ufs_hba *hba; + int err; + + vops = device_get_match_data(dev); + if (!vops) + return dev_err_probe(dev, -EINVAL, "ufs_hba_variant_ops not defined.\n"); + + err = ufshcd_pltfrm_init(pdev, vops); + if (err) + return dev_err_probe(dev, err, "ufshcd_pltfrm_init failed\n"); + + hba = platform_get_drvdata(pdev); + /* Set the default desired pm level in case no users set via sysfs */ + ufs_rockchip_set_pm_lvl(hba); + + return 0; +} + +static void ufs_rockchip_remove(struct platform_device *pdev) +{ + struct ufs_hba *hba = platform_get_drvdata(pdev); + struct ufs_rockchip_host *host = ufshcd_get_variant(hba); + + pm_runtime_forbid(&pdev->dev); + pm_runtime_get_noresume(&pdev->dev); + ufshcd_remove(hba); + ufshcd_dealloc_host(hba); + clk_disable_unprepare(host->ref_out_clk); +} + +static int ufs_rockchip_runtime_suspend(struct device *dev) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + struct ufs_rockchip_host *host = ufshcd_get_variant(hba); + struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); + + clk_disable_unprepare(host->ref_out_clk); + + /* + * Shouldn't power down if rpm_lvl is less than level 5. + * This flag will be passed down to platform power-domain driver + * which has the final decision. + */ + if (hba->rpm_lvl < UFS_PM_LVL_5) + genpd->flags |= GENPD_FLAG_RPM_ALWAYS_ON; + else + genpd->flags &= ~GENPD_FLAG_RPM_ALWAYS_ON; + + return ufshcd_runtime_suspend(dev); +} + +static int ufs_rockchip_runtime_resume(struct device *dev) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + struct ufs_rockchip_host *host = ufshcd_get_variant(hba); + int err; + + err = clk_prepare_enable(host->ref_out_clk); + if (err) { + dev_err(hba->dev, "failed to enable ref out clock %d\n", err); + return err; + } + + reset_control_assert(host->rst); + usleep_range(1, 2); + reset_control_deassert(host->rst); + + return ufshcd_runtime_resume(dev); +} + +static int ufs_rockchip_system_suspend(struct device *dev) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + struct ufs_rockchip_host *host = ufshcd_get_variant(hba); + + /* Pass down desired spm_lvl to Firmware */ + arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG, + host->pd_id, hba->spm_lvl < 5 ? 1 : 0, 0, 0, 0, 0, NULL); + + return ufshcd_system_suspend(dev); +} + +static const struct dev_pm_ops ufs_rockchip_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(ufs_rockchip_system_suspend, ufshcd_system_resume) + SET_RUNTIME_PM_OPS(ufs_rockchip_runtime_suspend, ufs_rockchip_runtime_resume, NULL) + .prepare = ufshcd_suspend_prepare, + .complete = ufshcd_resume_complete, +}; + +static struct platform_driver ufs_rockchip_pltform = { + .probe = ufs_rockchip_probe, + .remove = ufs_rockchip_remove, + .driver = { + .name = "ufshcd-rockchip", + .pm = &ufs_rockchip_pm_ops, + .of_match_table = ufs_rockchip_of_match, + }, +}; +module_platform_driver(ufs_rockchip_pltform); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Rockchip UFS Host Driver"); diff --git a/drivers/ufs/host/ufs-rockchip.h b/drivers/ufs/host/ufs-rockchip.h new file mode 100644 index 0000000..37c45a5 --- /dev/null +++ b/drivers/ufs/host/ufs-rockchip.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Rockchip UFS Host Controller driver + * + * Copyright (C) 2024 Rockchip Electronics Co.Ltd. + */ + +#ifndef _UFS_ROCKCHIP_H_ +#define _UFS_ROCKCHIP_H_ + +#define UFS_MAX_CLKS 3 + +#define SEL_TX_LANE0 0x0 +#define SEL_TX_LANE1 0x1 +#define SEL_TX_LANE2 0x2 +#define SEL_TX_LANE3 0x3 +#define SEL_RX_LANE0 0x4 +#define SEL_RX_LANE1 0x5 +#define SEL_RX_LANE2 0x6 +#define SEL_RX_LANE3 0x7 + +#define MIB_T_DBG_CPORT_TX_ENDIAN 0xc022 +#define MIB_T_DBG_CPORT_RX_ENDIAN 0xc023 + +#define RK3576_PD_UFS 0x7 + +struct ufs_rockchip_host { + struct ufs_hba *hba; + void __iomem *ufs_phy_ctrl; + void __iomem *ufs_sys_ctrl; + void __iomem *mphy_base; + struct gpio_desc *rst_gpio; + struct reset_control *rst; + struct clk *ref_out_clk; + struct clk_bulk_data clks[UFS_MAX_CLKS]; + uint64_t caps; + uint64_t pd_id; +}; + +#define ufs_sys_writel(base, val, reg) \ + writel((val), (base) + (reg)) +#define ufs_sys_readl(base, reg) readl((base) + (reg)) +#define ufs_sys_set_bits(base, mask, reg) \ + ufs_sys_writel( \ + (base), ((mask) | (ufs_sys_readl((base), (reg)))), (reg)) +#define ufs_sys_ctrl_clr_bits(base, mask, reg) \ + ufs_sys_writel((base), \ + ((~(mask)) & (ufs_sys_readl((base), (reg)))), \ + (reg)) + +#endif /* _UFS_ROCKCHIP_H_ */