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Sat, 09 Mar 2019 06:09:43 -0800 (PST) Received: from localhost.localdomain ([150.109.119.235]) by smtp.gmail.com with ESMTPSA id g3sm1094195pgg.41.2019.03.09.06.09.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Mar 2019 06:09:42 -0800 (PST) From: Qiang Yu To: dri-devel@lists.freedesktop.org Subject: [PATCH v2] drm/fourcc: add ARM GPU tile format Date: Sat, 9 Mar 2019 22:09:02 +0800 Message-Id: <20190309140902.9871-1-yuq825@gmail.com> X-Mailer: git-send-email 2.17.1 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=KXwjlkCcf9qgoq9lk9POoloFgux/QDqRT1rCDZGzNSY=; b=KpW3FZm8+zcn+sdAdvt9q6pTjwIIovv4G/1mInCvdAIGOtPxD1Dl2i2ehIDSA1yNwN EsDP2Oq3ZBYtkkfgK0rOGyNcOhz3mupDQBb4zxVv+0qzO2+nBl4Pm0dnXbSxpyK88taP CRTXaqY4PeRLUIbec73Wm6y4/RNyg03DmcITW8HhR2k3/6zQ9F2zq6ld0b4GiqXHs7cp YeMh1tyv/5X2sVYUS4u0Eq9rnJ0oyib+uSe1jHqQ7JchNGRyfLW5siaOe70G12YQ+qkw AbajbSwW3vk4sn3wHn3kjXAq3bn3rs2NrpJ3+mXF2t/lKn3CYwMnuwEGSTSITTBqZ/4+ ZEag== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lima@lists.freedesktop.org, Maxime Ripard , David Airlie , Qiang Yu , Sean Paul , Alyssa Rosenzweig MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP v2: seperate AFBC and GPU encoding Cc: Brian Starkey Cc: Rob Herring Cc: Alyssa Rosenzweig Signed-off-by: Qiang Yu Reviewed-by: Alyssa Rosenzweig --- include/uapi/drm/drm_fourcc.h | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 9fa7cf7bb274..7af5197e7ebc 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -601,6 +601,19 @@ extern "C" { */ #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6) +/* + * Arm Device code + * + * Arm has multiple devices which do not share buffer format, + * so add a device field at the MSB of the format field to seperate + * each device's encoding. + */ +#define DRM_FORMAT_MOD_ARM_DEVICE_AFBC 0x00 +#define DRM_FORMAT_MOD_ARM_DEVICE_GPU 0x01 + +#define DRM_FORMAT_MOD_ARM_CODE(device, val) \ + fourcc_mod_code(ARM, ((__u64)device << 48) | ((val) & 0x0000ffffffffffffULL)) + /* * Arm Framebuffer Compression (AFBC) modifiers * @@ -615,7 +628,8 @@ extern "C" { * Further information on the use of AFBC modifiers can be found in * Documentation/gpu/afbc.rst */ -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_DEVICE_AFBC, __afbc_mode) /* * AFBC superblock size @@ -709,6 +723,21 @@ extern "C" { */ #define AFBC_FORMAT_MOD_BCH (1ULL << 11) +/* + * Arm GPU modifiers + */ +#define DRM_FORMAT_MOD_ARM_GPU(mode) \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_DEVICE_GPU, mode) + +/* + * Arm GPU tiled format + * + * This is used by ARM Mali Utgard/Midgard GPU. It divides buffer into + * 16x16 pixel blocks. Blocks are stored linearly in order, but pixels + * in the block are reordered. + */ +#define DRM_FORMAT_MOD_ARM_GPU_TILED DRM_FORMAT_MOD_ARM_GPU(1) + /* * Allwinner tiled modifier *