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Wed, 9 Oct 2024 00:39:52 -0500 From: Vineeth Karumanchi To: , , , , , , , , , , CC: , , , , Subject: [RFC PATCH net-next 1/5] dt-bindings: net: macb: Add support for versal2 10gbe device Date: Wed, 9 Oct 2024 11:09:42 +0530 Message-ID: <20241009053946.3198805-2-vineeth.karumanchi@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009053946.3198805-1-vineeth.karumanchi@amd.com> References: <20241009053946.3198805-1-vineeth.karumanchi@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D0:EE_|SA3PR12MB7922:EE_ X-MS-Office365-Filtering-Correlation-Id: acac4029-a62d-43d2-3c5e-08dce824d039 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024|921020; X-Microsoft-Antispam-Message-Info: V6geU5FYTLO3bQ+hkt1FqnVjyMBD0bxz/9LbgncaQYF1psdxK4SO9VA50xfPQyG3ZnMLFMxS1VCq/RZPmOJOJ7ms1UYSF4QrfG97qJqnHUJ16eSC29RuA0FQQH8v3Gb+AUKu0tH2TiyV+7Qvh6K+CLrDaRMvtaC7sD7JplH2pAr0qzaAQdgDeQiskj9NQ68KpqcpFAk/pg0xjr+c2/ZI/FTJbnHFAOLNaNWr6G19Hg54urc8859fTH88wI79xdrrfmmODCBrAOHowSe6YDgywqh21oBHONbVIsVNeCAN8SxNiYeOXsghnMWEMf+XOkJKI4t6adodM98rAdz2KROYn5INXjKV8903S68yq7OL6zZCsa4oFHkIsmLr/HB1DLaC8Bd9CdlHky5yQtrhkHl4h0yLRaflTy/d4nOUH223eUrkalpEKBXVuc6+dN6ZFLondzRzWt/h+COC7GIwQPDqX3G0ensZU0W8rQvZw7l9T9IowlQMhoIpiR+3lJyxiNPrhArEzb88tbhdzQ0rh32AswLFNZMbUIMSogIgwBtjnxUrAyCvzs3LOuEVhn1JFK3PDpzlkWSZWBsxF1qI/ytt2NyNl3b4cBrLk0YpXbrMPcUtTPv7Y5oxUVX6BFivv6jT+aIlqXgswHd8Pl04TmjPmi518xURNHvUljZvvAv2HA37hgTjO4F0o0qYJ2qtQNxHDAGiIBSQthzEZcxJZ93f2G5zdiw9NlzICyY1KAOa13wNt8IOve/7YjW6Vx9h/jla8GYuKa7udEx7SuhnXtYbCp4tDszGlOJ7Q7bmbhkmd02Bm9bRVq7x5x5Dgi1zi1M1bDbljfMTnZE0z/CFMCA2Oi7ekCiUyETSBGErxIAVX4EyuqMl81xYtoTaISqOQKd9lRTCmQdGj84W2NGRm3ZUP0Xo8VruhhEUQfeTnHqMI8BaCZLBDJWynTyfKe5jeM5UoyME/x2dfVDwskgvkRJl/L0cY+4h2xdPVnxbYmsMtIOR/mGpUYRQYunJ1FwDWzlpZUoPWPvlokFhBylz390phl+Ko232+1UlDnBulonCCiqu3DLISYFEo5IiirYoghuFSa75mLxDg7OmOsPyQ0c28fV/5pLjSztsQ4eYa/MaWXnFXZIB23eyrzLE3Vp6QObT8Opk4JkCLTPSprPK78OzgcP4f2EfMqkPoufOfa0Q2WCtBbq0JWYetqJPvU4kXkkxxnZRXPu1XBgNij+N5UvYkdRCCnqW9+n2URoVmi0KWTuCiDdwZkGEVR43wXUgmhOeLhDolemYGzian7ECC59Sj5139pgTWKb3Znh4WSctyR8i2zQvANYRXB44bLPdCQz0qnsC1Y8aYrr7dq9unHvHiNY0ubKEwp4K/miFZvsueRj7YANFQ+eZkKnTuovb577X X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024)(921020);DIR:OUT;SFP:1101; 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It has USX pcs for higher speed and SGMII PCS for low transmission. Signed-off-by: Vineeth Karumanchi --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index 3c30dd23cd4e..3870e4846e8a 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - xlnx,versal-gem # Xilinx Versal + - amd,versal2-10gbe # AMD Versal2 10gbe - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC - const: cdns,gem # Generic From patchwork Wed Oct 9 05:39:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineeth Karumanchi X-Patchwork-Id: 13827557 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2058.outbound.protection.outlook.com [40.107.212.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 622A9165EEB; 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Signed-off-by: Vineeth Karumanchi --- drivers/net/ethernet/cadence/macb_main.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 79db6cd01844..8f893f035289 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -4951,6 +4951,16 @@ static const struct macb_config versal_config = { .usrio = &macb_default_usrio, }; +static const struct macb_config versal2_10gbe_config = { + .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_QUEUE_DISABLE, + .dma_burst_length = 16, + .clk_init = macb_clk_init, + .init = init_reset_optional, + .jumbo_max_len = 10240, + .usrio = &macb_default_usrio, +}; + static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, { .compatible = "cdns,macb" }, @@ -4974,6 +4984,7 @@ static const struct of_device_id macb_dt_ids[] = { { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config}, { .compatible = "xlnx,zynq-gem", .data = &zynq_config }, { .compatible = "xlnx,versal-gem", .data = &versal_config}, + { .compatible = "amd,versal2-10gbe", .data = &versal2_10gbe_config}, { /* sentinel */ } }; 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Constants of the bitfeilds in USX_CONTROL reg: - HS_SPEED_*: Multiple speed constants of USX_SPEED bitfeild. - MACB_SERDES_RATE_*: Multiple serdes rate constants of SERDES_RATE bitfeild. Since MACB_SERDES_RATE_* and HS_SPEED_* are register constants, move them to the header file. Signed-off-by: Vineeth Karumanchi --- drivers/net/ethernet/cadence/macb.h | 12 ++++++++++++ drivers/net/ethernet/cadence/macb_main.c | 3 --- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 5740c98d8c9f..47e80fa72865 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -563,11 +563,23 @@ #define GEM_RX_SCR_BYPASS_SIZE 1 #define GEM_TX_SCR_BYPASS_OFFSET 8 #define GEM_TX_SCR_BYPASS_SIZE 1 +#define GEM_RX_SYNC_RESET_OFFSET 2 +#define GEM_RX_SYNC_RESET_SIZE 1 #define GEM_TX_EN_OFFSET 1 #define GEM_TX_EN_SIZE 1 #define GEM_SIGNAL_OK_OFFSET 0 #define GEM_SIGNAL_OK_SIZE 1 +/* Constants for USX_CONTROL */ +#define HS_SPEED_10000M 4 +#define HS_SPEED_5000M 3 +#define HS_SPEED_2500M 2 +#define HS_SPEED_1000M 1 +#define MACB_SERDES_RATE_10G 1 +#define MACB_SERDES_RATE_5G 0 +#define MACB_SERDES_RATE_2_5G 0 +#define MACB_SERDES_RATE_1G 0 + /* Bitfields in USX_STATUS. */ #define GEM_USX_BLOCK_LOCK_OFFSET 0 #define GEM_USX_BLOCK_LOCK_SIZE 1 diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 8f893f035289..3f9dc0b037c0 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -87,9 +87,6 @@ struct sifive_fu540_macb_mgmt { #define MACB_WOL_ENABLED BIT(0) -#define HS_SPEED_10000M 4 -#define MACB_SERDES_RATE_10G 1 - /* Graceful stop timeouts in us. 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Wed, 9 Oct 2024 00:40:11 -0500 Received: from xhdvineethc40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Wed, 9 Oct 2024 00:40:07 -0500 From: Vineeth Karumanchi To: , , , , , , , , , , CC: , , , , Subject: [RFC PATCH net-next 4/5] net: macb: Configure High Speed Mac for given speed. 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Move the initialization instances to macb_usx_pcs_link_up(). Signed-off-by: Vineeth Karumanchi --- drivers/net/ethernet/cadence/macb.h | 1 + drivers/net/ethernet/cadence/macb_main.c | 57 ++++++++++++++++++++---- 2 files changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 47e80fa72865..ed4edeac3a59 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -825,6 +825,7 @@ }) #define MACB_READ_NSR(bp) macb_readl(bp, NSR) +#define MACB_READ_USX_STATUS(bp) gem_readl(bp, USX_STATUS) /* struct macb_dma_desc - Hardware DMA descriptor * @addr: DMA address of data buffer diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 3f9dc0b037c0..7beb775a0bd7 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -94,6 +94,7 @@ struct sifive_fu540_macb_mgmt { #define MACB_PM_TIMEOUT 100 /* ms */ #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */ +#define GEM_SYNC_TIMEOUT 2500000 /* in usecs */ /* DMA buffer descriptor might be different size * depends on hardware configuration: @@ -564,14 +565,59 @@ static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, int duplex) { struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs); - u32 config; + u32 speed_val, serdes_rate, config; + bool hs_mac = false; + + switch (speed) { + case SPEED_1000: + speed_val = HS_SPEED_1000M; + serdes_rate = MACB_SERDES_RATE_1G; + break; + case SPEED_2500: + speed_val = HS_SPEED_2500M; + serdes_rate = MACB_SERDES_RATE_2_5G; + break; + case SPEED_5000: + speed_val = HS_SPEED_5000M; + serdes_rate = MACB_SERDES_RATE_5G; + hs_mac = true; + break; + case SPEED_10000: + speed_val = HS_SPEED_10000M; + serdes_rate = MACB_SERDES_RATE_10G; + hs_mac = true; + break; + default: + netdev_err(bp->dev, "Specified speed not supported\n"); + return; + } + + /* Enable HS MAC for high speeds */ + if (hs_mac) { + config = macb_or_gem_readl(bp, NCR); + config |= GEM_BIT(ENABLE_HS_MAC); + macb_or_gem_writel(bp, NCR, config); + } + + /* Configure HS MAC for specified speed */ + config = gem_readl(bp, HS_MAC_CONFIG); + config = GEM_BFINS(HS_MAC_SPEED, speed_val, config); + gem_writel(bp, HS_MAC_CONFIG, config); config = gem_readl(bp, USX_CONTROL); - config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config); - config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config); + config = GEM_BFINS(SERDES_RATE, serdes_rate, config); + config = GEM_BFINS(USX_CTRL_SPEED, speed_val, config); config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS)); + config |= GEM_BIT(RX_SYNC_RESET); + gem_writel(bp, USX_CONTROL, config); + mdelay(250); + config &= ~GEM_BIT(RX_SYNC_RESET); config |= GEM_BIT(TX_EN); gem_writel(bp, USX_CONTROL, config); + + if (readx_poll_timeout(MACB_READ_USX_STATUS, bp, config, config & GEM_BIT(USX_BLOCK_LOCK), + 1, GEM_SYNC_TIMEOUT)) + netdev_err(bp->dev, "USX PCS block lock not achieved\n"); } static void macb_usx_pcs_get_state(struct phylink_pcs *pcs, @@ -662,7 +708,6 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode, ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) { ctrl |= GEM_BIT(PCSSEL); - ncr |= GEM_BIT(ENABLE_HS_MAC); } else if (bp->caps & MACB_CAPS_MIIONRGMII && bp->phy_interface == PHY_INTERFACE_MODE_MII) { ncr |= MACB_BIT(MIIONRGMII); @@ -766,10 +811,6 @@ static void macb_mac_link_up(struct phylink_config *config, macb_or_gem_writel(bp, NCFGR, ctrl); - if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER) - gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M, - gem_readl(bp, HS_MAC_CONFIG))); - spin_unlock_irqrestore(&bp->lock, flags); if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) From patchwork Wed Oct 9 05:39:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vineeth Karumanchi X-Patchwork-Id: 13827560 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2070.outbound.protection.outlook.com [40.107.94.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC68D16EB4C; Wed, 9 Oct 2024 05:40:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.70 ARC-Seal: i=2; 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Signed-off-by: Vineeth Karumanchi --- drivers/net/ethernet/cadence/macb_main.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 7beb775a0bd7..48ba19a76418 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -624,14 +624,21 @@ static void macb_usx_pcs_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state) { struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs); + u32 hs_mac_map[] = {SPEED_UNKNOWN, SPEED_1000, SPEED_2500, + SPEED_5000, SPEED_10000}; u32 val; - state->speed = SPEED_10000; state->duplex = 1; state->an_complete = 1; - val = gem_readl(bp, USX_STATUS); - state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK)); + val = gem_readl(bp, HS_MAC_CONFIG); + val = GEM_BFEXT(HS_MAC_SPEED, val); + state->speed = hs_mac_map[val]; + + state->link = (state->speed < SPEED_5000) ? + !!(macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) : + !!(gem_readl(bp, USX_STATUS) & GEM_BIT(USX_BLOCK_LOCK)); + val = gem_readl(bp, NCFGR); if (val & GEM_BIT(PAE)) state->pause = MLO_PAUSE_RX;