From patchwork Wed Oct 9 08:50:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF6ECCED62A for ; Wed, 9 Oct 2024 08:50:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 57C8410E699; Wed, 9 Oct 2024 08:50:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="jfHYdrji"; dkim-atps=neutral Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5247510E696 for ; Wed, 9 Oct 2024 08:50:30 +0000 (UTC) Received: by mail-pj1-f41.google.com with SMTP id 98e67ed59e1d1-2e0946f9a8eso4536570a91.1 for ; Wed, 09 Oct 2024 01:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463830; x=1729068630; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=c7bIuQoomWT/rx9ticSN25UJS+k6AR92dNlVIMn4xi0=; b=jfHYdrjirj3h1IUbtqAhGoelVJC7rpSCBkh+yzSsBgesXc2blDQbc7/I/ETx4FGvH4 XdgVy4JBH1mWKY3WWiBb+p49kuSZX+p+W3g01bU0Sv4F4ymg68wxgmw2MdZsSOAoKIA+ 4s4H69FXpfTPA5W+4uO8db9XscyPqcmu2+1qZo9lOBQ2Gw3ZKNM8/UOqAOmGsgpoc9v3 oZgMExUR8eqljWYBuNyjD0wTKLXB920PCSfkhaoZoNoyuBsH3WYK+T0SZLrTEt12tgba 4mWYot0MOZl/PHRcOKFJVM2p8nPgK+fJ8RGyqkwNJqviW+JdXKepd5NjtcnEYh0E7IDL GR2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463830; x=1729068630; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c7bIuQoomWT/rx9ticSN25UJS+k6AR92dNlVIMn4xi0=; b=Tfykcn4lTSsYJoC9bqsl9EzilQmvhGXeTk4WC5Vaeksua0rwKLSrqcJIKhmnRWtIky crJru9b8WmTtF8fkMc/RRd2RUu92apR9DFCnqaWgNHQS+l1AwNiLA8Ex6YEtXqHMWLEP zkXCWv6Zys9p4G3LNlc9tSzcs00Ojmj/mcZseggRFbzd4s2ui63nrlwELR2M4QDG4cDc 4PxLR0DUzkaVGDz66216KpXHMa1SA0DMqcmJwT+Fl8AWOff5pCTv2WcvrJVKGp3Fqxx+ QkPvlA3P1xMIHQg/s+tYx6LuURnSDBi/UmgVZ3UREZjgyKBKe3MsTsyH4uWkWgSLlxlq MONQ== X-Forwarded-Encrypted: i=1; AJvYcCXtBr3T9hzbZmaFvI+GjjsGK4FpLe6DnwOw/UN2z0Ewt9s+PZElUxJY8u1umhOYAvCNxKnbRvNIjWU=@lists.freedesktop.org X-Gm-Message-State: AOJu0YxwlK8PKnct/zVBE/Z722uiMEVlcMHzUbtDBD1rSO2fElXQd9wF MXNIJ3HERiB4wNkYBcdfZqskHJrvVvx2oCD7xbxrwnm/eYrZYrcWXxQpDxEfwtQ= X-Google-Smtp-Source: AGHT+IESUTwygnYBSZdBsUDXgtACJ/v1ab4RJl/GTGW8J3oCmqBYI3AAq2s4v5mchDc9OY7NZ7CVOQ== X-Received: by 2002:a17:90a:cb01:b0:2e2:9314:2785 with SMTP id 98e67ed59e1d1-2e2a21ef23cmr2286037a91.5.1728463829841; Wed, 09 Oct 2024 01:50:29 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:29 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:14 +0800 Subject: [PATCH v2 01/14] drm/msm/dpu: polish log for resource allocation MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-1-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1834; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=AOnvev//l48K9poLpI3b2jyK6oiNPwqIXWbViweShqc=; b=ZoaNma48RD560N7Wpt6QTcmjBW200b4i9cEzu0XKgwNwqPVL8i7T69/tEfkxovejkPIu+Mr28 li84Bu4qOo4AR+M+tDz5CECNYXgVmRhxQvGYnbyCwDuNNtvMOBsqH7e X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add resource allocation type info. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 15b42a6683639..2b03ab907c2bc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -778,6 +778,21 @@ void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, ARRAY_SIZE(global_state->sspp_to_crtc_id), crtc_id); } +static char *dpu_hw_blk_type_name[] = { + [DPU_HW_BLK_TOP] = "TOP", + [DPU_HW_BLK_SSPP] = "SSPP", + [DPU_HW_BLK_LM] = "LM", + [DPU_HW_BLK_CTL] = "CTL", + [DPU_HW_BLK_PINGPONG] = "pingpong", + [DPU_HW_BLK_INTF] = "INTF", + [DPU_HW_BLK_WB] = "WB", + [DPU_HW_BLK_DSPP] = "DSPP", + [DPU_HW_BLK_MERGE_3D] = "merge_3d", + [DPU_HW_BLK_DSC] = "DSC", + [DPU_HW_BLK_CDM] = "CDM", + [DPU_HW_BLK_MAX] = "none", +}; + int dpu_rm_get_assigned_resources(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t enc_id, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) @@ -828,13 +843,13 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, continue; if (num_blks == blks_size) { - DPU_ERROR("More than %d resources assigned to enc %d\n", - blks_size, enc_id); + DPU_ERROR("More than %d %s assigned to enc %d\n", + blks_size, dpu_hw_blk_type_name[type], enc_id); break; } if (!hw_blks[i]) { - DPU_ERROR("Allocated resource %d unavailable to assign to enc %d\n", - type, enc_id); + DPU_ERROR("%s unavailable to assign to enc %d\n", + dpu_hw_blk_type_name[type], enc_id); break; } blks[num_blks++] = hw_blks[i]; From patchwork Wed Oct 9 08:50:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7CA9CED628 for ; Wed, 9 Oct 2024 08:50:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E7CA10E69A; Wed, 9 Oct 2024 08:50:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="W9oq2YUV"; dkim-atps=neutral Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) by gabe.freedesktop.org (Postfix) with ESMTPS id BB55010E69A for ; Wed, 9 Oct 2024 08:50:34 +0000 (UTC) Received: by mail-pj1-f48.google.com with SMTP id 98e67ed59e1d1-2e28d7d44dbso1195664a91.2 for ; Wed, 09 Oct 2024 01:50:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463834; x=1729068634; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rQUSJNvwZ/PY6GUH9AC1To+F9Rww7eBYxG8hGTmYBHA=; b=W9oq2YUVQAM9BPEPb9foUI2PTqSc8hKYywxYgErfPsK3BJjzSaEx+PoEcjOd1CLrg8 usLO3dsdY5QW0+P0QzElXF4VFEQP9qPwMcO8zsY9YGqnBjTFIgxWJ5fjt6J/P/AIqu4F BIx1QTPVtRZMkkfvCL0nO8hp+xeqChHaWWB4p67GKBHZ4GMZerXUOJck8xa+dDuwoNEe Qy6KgtFkDlL6m7ALHbh/8Npp+sHP4nGE1uCwRdNQxqHzi6sFR1xeDI9GrA1D68TVZSBp 47iQ/UzmUSK/0dG9umKgaGW2ctPuuWd/j1bLYegAwCYpwyglAlqUOQEaoRmVGms+vCYp udMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463834; x=1729068634; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rQUSJNvwZ/PY6GUH9AC1To+F9Rww7eBYxG8hGTmYBHA=; b=PgJKL40mRMTNNC60izn54SXgO6aNmN1JW9/rQwtDTBNhd5zAJm60PXqrapeV+7u6jc XNj7u1JG4lsWYpT1ibJiwsNbOIN40B9pb9cI2vgBROVtatDda1+fW0TvaVNwnAUY4gzr vPGbT7CblaQl++YoiWYyFeVU5Hy3DH1Fgc1oxODOaO1N7leP+jrwM1nKh1b3RwGi1Kqv ZJXSFk9EIEsy2eQkg0FhDROsHx7Ktp6MP17zK2P8MvYbB1T9mnZ6ndMoB5aWLKVCBQgK C5CiIrmvnW09MfuVzDowp7rcATS6eElFlM1gumpkP3noRg46QTIhrBpmHQ8Pg4c5gS68 fvhQ== X-Forwarded-Encrypted: i=1; AJvYcCVexZ5L24g3ztPAaGOTTU3pSilhRm/+KK/xR6YfqHUwMrcuituV/K/YYAFHZ1rKCfDTl8EZCxamYbk=@lists.freedesktop.org X-Gm-Message-State: AOJu0YwtfjlETRBWg1UhzFrtMvuPtyTFL/AUswSPBoYwCpVgV3Hfzf1q cN8bqWucCY3DRnNZa2CSw0LOqRZGSIffgNdAtMGOw5rndBt6sqUMEopc1YAbT9EFfxIFn+yNmvJ fChaXHA== X-Google-Smtp-Source: AGHT+IELZNGpZl+o9brSMTMV2R5qjLAQnLo4r4MZsTmntvKCuRTaaBljTAzcdiFMnYwOHsV1z7J9Aw== X-Received: by 2002:a17:90b:1104:b0:2e2:9522:279e with SMTP id 98e67ed59e1d1-2e2a25247e0mr2199871a91.31.1728463834283; Wed, 09 Oct 2024 01:50:34 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:34 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:15 +0800 Subject: [PATCH v2 02/14] drm/msm/dpu: decide right side per last bit MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-2-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1407; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=VkIAGwnZaBvIGk9O/Pd26yOaUH9F6U5Y+Vxq/wNMgsM=; b=aojPxprQ0psdASS4m8/E0MCuQj6okV8Fejiw7zVz4jm03ih52aCBaafWdJ/sa3xxRnZyuiX6W CVGfU1DgFG7D5QOSOi+332+U+ccsaaKBjtPHPV9UyH4D/pH/Nk9Dih0 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" decide right side of a pair per last bit, in case of multiple mixer pairs. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 7d0fff9472441..3e0e6e9757da5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -369,11 +369,10 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) { struct dpu_crtc_state *crtc_state; - int lm_idx, lm_horiz_position; + int lm_idx; crtc_state = to_dpu_crtc_state(crtc->state); - lm_horiz_position = 0; for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; @@ -384,7 +383,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) cfg.out_width = drm_rect_width(lm_roi); cfg.out_height = drm_rect_height(lm_roi); - cfg.right_mixer = lm_horiz_position++; + cfg.right_mixer = lm_idx & 0x1; cfg.flags = 0; hw_lm->ops.setup_mixer_out(hw_lm, &cfg); } From patchwork Wed Oct 9 08:50:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41CF4CED62A for ; Wed, 9 Oct 2024 08:50:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC75210E696; Wed, 9 Oct 2024 08:50:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="zY27jmH+"; dkim-atps=neutral Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C3F410E152 for ; Wed, 9 Oct 2024 08:50:39 +0000 (UTC) Received: by mail-pj1-f44.google.com with SMTP id 98e67ed59e1d1-2e28d7d44dbso1195738a91.2 for ; Wed, 09 Oct 2024 01:50:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463839; x=1729068639; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=E/voAymQ+FLo0K2rDmsz5j/XLkoeZJYYbnZfE87o5mA=; b=zY27jmH+xUoDbr18qCzIzUK1hej4cWtLcezJfiQ68QAqZdh1+rpFODsOQGKR8iN1WD /JWzRwEekKyP+kqvJeR3KIWIVZIeDJvaag5MbGZZn4VeobHEIXbB1aWia2wjGt0lEgcm VNBe0m1NtstJof6R2LbHX30wUKHVMB4tPVUwCB5yzmfobkNGA2SxKkk9Zw//CHhPd8Zo Y9A2i/L7+yRCwg0RiF9c/kOCpHL6yyO+6Cn2tkXFLV2y2lqkJqhChMJuG8KjS0nVS2Vp xfz6fHoAygyh5VoJhwaPPjBjsG5Onq57jGzZqkLAabw+/ACvxp8g8APAp0UejtG7hIGZ E8Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463839; x=1729068639; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E/voAymQ+FLo0K2rDmsz5j/XLkoeZJYYbnZfE87o5mA=; b=YKyZpyIP0s3R88AAexPJ5ZLIYQCU89jwjcY0LMbodhfxMOuLUKTQ969SE1+KK+5YAa 2cFSN/UI76MhsR1lAIwqbdWrzqU88np5LqxXUR/8yvqYp4Y3CDrLef3DvM3TAx3eUbzL Y28GbFzIyVProQdmMZMiSSb9bHDBohVr1gRMy0XC6SExMrJMvD/+8FTvZVVnv1AQxp0L XCuMNIhwTDleSFgVGYZiwYse3nnd2+zmeX3fexK/Uc8tYHKgt6kVG7GxgHGjgWNOmYsd E19bZwvlTvzJNakr97dySP0F84lc+GyuI8m3JutP6u+tUTv1FA32rQOnu1B6kyJ4uHMR 02rg== X-Forwarded-Encrypted: i=1; AJvYcCV0HiNuc66xvWtB+pOdBzyMpQJKINDCAtRBTPjAK/YYOPesa5N/gyrzNczjCfeReWulvkOyed0d9F8=@lists.freedesktop.org X-Gm-Message-State: AOJu0YweyzVk66muRS9osVP+GFMXSvlxnae6StIlGne0qTcXYA9ptIRK QMct/O8L66WGFKTZgZQW8mR8P21YH0+kmG/W6plI4xGBqQd9VJj2o4HEnDxb1T8= X-Google-Smtp-Source: AGHT+IGLdVPxQWHieF+9EHa8/WCKnJVudcn9L6wpuGsElJdCrsUD5SxSB2GtYHpHGZh8Ho+Hcyh1Xw== X-Received: by 2002:a17:90a:3489:b0:2e2:9a2a:d218 with SMTP id 98e67ed59e1d1-2e2a21ef24bmr2165076a91.2.1728463839143; Wed, 09 Oct 2024 01:50:39 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:38 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:16 +0800 Subject: [PATCH v2 03/14] drm/msm/dpu: fix mixer number counter on allocation MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-3-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1237; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=WThdm3+r0o6lcg95hlJxNuerWQ1yzvjO0VMSK/DVslE=; b=XyWO3HZGDntoWFWpltwc8jk91TUGcI9j/DmmGgwXf1vPYLP+Lq3fLNGmynRO2WPSmNAdXF8VD e+84dPuuD53B+CK0+Zi+DNVJEJHL2kkrA5b3HQ84N4bqC1gD7g3BBDq X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the case to reserve multiple pairs mixers for high resolution. Current code only supports one pair of mixer usage case. To support quad-pipe usage case, two pairs of mixers are needed. Current code resets number of mixer on failure of pair's peer test and retry on another pair. If two pairs are needed, the failure on the test of 2nd pair results clearing to the 1st pair. This patch only clear the bit for the 2nd pair allocation before retry on another pair. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 2b03ab907c2bc..5c9bb64df7930 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -306,7 +306,11 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, if (!rm->mixer_blks[i]) continue; - lm_count = 0; + /* + * Clear the last bit to drop the previous primary mixer if + * fail to find its peer. + */ + lm_count &= 0xfe; lm_idx[lm_count] = i; if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, From patchwork Wed Oct 9 08:50:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D15D0CED628 for ; Wed, 9 Oct 2024 08:50:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4912610E6A3; Wed, 9 Oct 2024 08:50:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="rVL9nN9E"; dkim-atps=neutral Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B65410E69F for ; Wed, 9 Oct 2024 08:50:45 +0000 (UTC) Received: by mail-pg1-f176.google.com with SMTP id 41be03b00d2f7-6bce380eb96so3927074a12.0 for ; Wed, 09 Oct 2024 01:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463845; x=1729068645; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gFxoZp5lvl8L75KXTXnmIeC5GQOmgq4jA/ny4+kC/hI=; b=rVL9nN9EAAA6lc9G5nRDdfyrQAMLmqjxFdQD8V2uOYKEpkn0tzCdVyf31yXWm7qYjl Y6FcE6077qnnyMIr2N6ipYdK/jlkXM/pkOGtwLMPzHkshvjFqFhP6gqE2Ke4frWBUVAd yGtrRbtsjCitdm0mg3brl+XyzLr/UwrTeQ+UVJr6WKYeGnM3pUb3W6R/mPEuiH+EFAG1 gB7QDqChi1C50cfOvL/JcsgddCJKmwxfMf3rBlnKW0L93uitVqyxv+0770vwgnehSSy/ l3asJuPNUP9T5Z/ssHjZPLdAmL1GBfJYxCJoelMIwvmbeJrEaAgk5VP6uXJjOtfnIJ0k X4EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463845; x=1729068645; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gFxoZp5lvl8L75KXTXnmIeC5GQOmgq4jA/ny4+kC/hI=; b=UNfbiHG7kMIjg2YmBqKSjV8GiQQmQ4NnEjfeEeti8+ls0vHinEeuVIm2Vjg6NHV91+ b69s00QL/mBxAXQAoxwM02104nj5kWwKS6XE+JcFh9UEnhjYfi0THRMlhSBskLI5ykxQ F0SyWre+J9SPHVxx8TZExLq8NUsrtKFi7a/kM7f1N8To0Qf2R2pNopBjBPX1t1YZCxOg QWpwfUZuQS1lJ4lf+1Foy+DCoZLBjv7LOeaiA4wxJKM8yPBF8nYM+B1pff+xBjar//wE baZKdnkZo/48oOxQMNbhNk6nHjrSoUa9EsQEQdMfHswT+rbrfI390bt827bbsP7cbc2d nxIA== X-Forwarded-Encrypted: i=1; AJvYcCX96La4ER5DiccUGC+Fo5ihiqToShqzN3SAzgBUPzwqMBAplLeObGjUz6lFZaM32q//BvH7WiyllHg=@lists.freedesktop.org X-Gm-Message-State: AOJu0YxuydwPDy/BPsA7iH9+/Dr5Zg6L4lUgSIHR9jJryiQ330SMPK6U 8tqU6jErXyjfEeZrl2W/nvvDYioMq1HPM40RDEwVjmTD5OQTzt0bNZbhOWkFNpQ= X-Google-Smtp-Source: AGHT+IER5m8hOoH/Wws+QEssyk0f1aSKzdwJ8U1bUR/9WTE+/Czt6Ufxweg/byCCtqaNnoKEwDNiVQ== X-Received: by 2002:a17:90a:f0d1:b0:2e2:abab:c450 with SMTP id 98e67ed59e1d1-2e2ababc590mr1412105a91.11.1728463844828; Wed, 09 Oct 2024 01:50:44 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:44 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:17 +0800 Subject: [PATCH v2 04/14] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-4-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=25681; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=KJa8UFj1F4L8nQh4hIiMMrUpybEXZ51VO2/k9KJv3XQ=; b=Ii9UtPVf6NHG4/sGXzCHJ9n8R3KY/21OqwzXDuPHQEe48KWIvavFH4PFOBQg5RFXaGv6BEMxC LZpHhkxlsxtDUn35atXgn0Bscm1l+J0WFIhkSL0++unKwMxl03gSN/w X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Up to now the driver has been using encoder to allocate hardware resources. Switch it to use CRTC id so that mixer number can be known in dpu_plane_virtual_assign_resources() via CRTC id for sspp alloation. Because the mixer allocation is done in drm_atomic_helper_check_modeset() as part of CRTC operation. While the sspp assignment is in drm_atomic_helper_check_planes() call tree. So CRTC is more central than encoder. Siwtching the id achieves above goal. Co-developed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 189 ++++++++++++++-------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 19 ++- 4 files changed, 116 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index e8400b494687c..bd2509985c4d0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -687,11 +687,11 @@ static int dpu_encoder_virt_atomic_check( * Dont allocate when active is false. */ if (drm_atomic_crtc_needs_modeset(crtc_state)) { - dpu_rm_release(global_state, drm_enc); + dpu_rm_release(global_state, crtc_state->crtc); if (!crtc_state->active_changed || crtc_state->enable) ret = dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, topology); + crtc_state->crtc, topology); } trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); @@ -1125,14 +1125,14 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, /* Query resource that have been reserved in atomic check step. */ num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, + drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, ARRAY_SIZE(hw_pp)); num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + drm_enc->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, + drm_enc->crtc, DPU_HW_BLK_DSPP, hw_dspp, ARRAY_SIZE(hw_dspp)); for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) @@ -1140,7 +1140,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, : NULL; num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSC, + drm_enc->crtc, DPU_HW_BLK_DSC, hw_dsc, ARRAY_SIZE(hw_dsc)); for (i = 0; i < num_dsc; i++) { dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); @@ -1154,7 +1154,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, struct dpu_hw_blk *hw_cdm = NULL; dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CDM, + drm_enc->crtc, DPU_HW_BLK_CDM, &hw_cdm, 1); dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } @@ -2030,7 +2030,7 @@ static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms); num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state, - phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); for (i = 0; i < num_lm; i++) { hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 1952576600575..4f0fa1596b414 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -134,12 +134,12 @@ struct dpu_global_state { struct dpu_rm *rm; - uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; - uint32_t mixer_to_enc_id[LM_MAX - LM_0]; - uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; - uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; - uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; - uint32_t cdm_to_enc_id; + uint32_t pingpong_to_crtc_id[PINGPONG_MAX - PINGPONG_0]; + uint32_t mixer_to_crtc_id[LM_MAX - LM_0]; + uint32_t ctl_to_crtc_id[CTL_MAX - CTL_0]; + uint32_t dspp_to_crtc_id[DSPP_MAX - DSPP_0]; + uint32_t dsc_to_crtc_id[DSC_MAX - DSC_0]; + uint32_t cdm_to_crtc_id; uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE]; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 5c9bb64df7930..a6e1eb888f6c8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -21,9 +21,9 @@ static inline bool reserved_by_other(uint32_t *res_map, int idx, - uint32_t enc_id) + uint32_t crtc_id) { - return res_map[idx] && res_map[idx] != enc_id; + return res_map[idx] && res_map[idx] != crtc_id; } /** @@ -225,7 +225,7 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx) * pingpong * @rm: dpu resource manager handle * @global_state: resources shared across multiple kms objects - * @enc_id: encoder id requesting for allocation + * @crtc_id: crtc id requesting for allocation * @lm_idx: index of proposed layer mixer in rm->mixer_blks[], function checks * if lm, and all other hardwired blocks connected to the lm (pp) is * available and appropriate @@ -239,14 +239,14 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx) */ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, int lm_idx, int *pp_idx, int *dspp_idx, + uint32_t crtc_id, int lm_idx, int *pp_idx, int *dspp_idx, struct dpu_rm_requirements *reqs) { const struct dpu_lm_cfg *lm_cfg; int idx; /* Already reserved? */ - if (reserved_by_other(global_state->mixer_to_enc_id, lm_idx, enc_id)) { + if (reserved_by_other(global_state->mixer_to_crtc_id, lm_idx, crtc_id)) { DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0); return false; } @@ -258,7 +258,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, return false; } - if (reserved_by_other(global_state->pingpong_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->pingpong_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id, lm_cfg->pingpong); return false; @@ -274,7 +274,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, return false; } - if (reserved_by_other(global_state->dspp_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->dspp_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id, lm_cfg->dspp); return false; @@ -286,7 +286,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, static int _dpu_rm_reserve_lms(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, struct dpu_rm_requirements *reqs) { @@ -314,7 +314,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, lm_idx[lm_count] = i; if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, - enc_id, i, &pp_idx[lm_count], + crtc_id, i, &pp_idx[lm_count], &dspp_idx[lm_count], reqs)) { continue; } @@ -333,7 +333,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, continue; if (!_dpu_rm_check_lm_and_get_connected_blks(rm, - global_state, enc_id, j, + global_state, crtc_id, j, &pp_idx[lm_count], &dspp_idx[lm_count], reqs)) { continue; @@ -350,13 +350,16 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, } for (i = 0; i < lm_count; i++) { - global_state->mixer_to_enc_id[lm_idx[i]] = enc_id; - global_state->pingpong_to_enc_id[pp_idx[i]] = enc_id; - global_state->dspp_to_enc_id[dspp_idx[i]] = - reqs->topology.num_dspp ? enc_id : 0; + global_state->mixer_to_crtc_id[lm_idx[i]] = crtc_id; + global_state->pingpong_to_crtc_id[pp_idx[i]] = crtc_id; + global_state->dspp_to_crtc_id[dspp_idx[i]] = + reqs->topology.num_dspp ? crtc_id : 0; - trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, + trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, crtc_id, pp_idx[i] + PINGPONG_0); + + DPU_DEBUG("reserve lm[%d]:%d, pp_idx[%d]:%d, dspp[%d]:%d for crtc_id %d\n", + i, lm_idx[i], i, pp_idx[i], i, dspp_idx[i], crtc_id); } return 0; @@ -365,7 +368,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, static int _dpu_rm_reserve_ctls( struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int ctl_idx[MAX_BLOCKS]; @@ -389,7 +392,7 @@ static int _dpu_rm_reserve_ctls( if (!rm->ctl_blks[j]) continue; - if (reserved_by_other(global_state->ctl_to_enc_id, j, enc_id)) + if (reserved_by_other(global_state->ctl_to_crtc_id, j, crtc_id)) continue; ctl = to_dpu_hw_ctl(rm->ctl_blks[j]); @@ -413,8 +416,8 @@ static int _dpu_rm_reserve_ctls( return -ENAVAIL; for (i = 0; i < ARRAY_SIZE(ctl_idx) && i < num_ctls; i++) { - global_state->ctl_to_enc_id[ctl_idx[i]] = enc_id; - trace_dpu_rm_reserve_ctls(i + CTL_0, enc_id); + global_state->ctl_to_crtc_id[ctl_idx[i]] = crtc_id; + trace_dpu_rm_reserve_ctls(i + CTL_0, crtc_id); } return 0; @@ -422,12 +425,12 @@ static int _dpu_rm_reserve_ctls( static int _dpu_rm_pingpong_next_index(struct dpu_global_state *global_state, int start, - uint32_t enc_id) + uint32_t crtc_id) { int i; for (i = start; i < (PINGPONG_MAX - PINGPONG_0); i++) { - if (global_state->pingpong_to_enc_id[i] == enc_id) + if (global_state->pingpong_to_crtc_id[i] == crtc_id) return i; } @@ -448,7 +451,7 @@ static int _dpu_rm_pingpong_dsc_check(int dsc_idx, int pp_idx) static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc = 0; @@ -461,10 +464,10 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (!rm->dsc_blks[dsc_idx]) continue; - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id)) continue; - pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; @@ -472,7 +475,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (ret) return -ENAVAIL; - global_state->dsc_to_enc_id[dsc_idx] = enc_id; + global_state->dsc_to_crtc_id[dsc_idx] = crtc_id; num_dsc++; pp_idx++; } @@ -488,7 +491,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc = 0; @@ -503,11 +506,11 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; /* consective dsc index to be paired */ - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id) || - reserved_by_other(global_state->dsc_to_enc_id, dsc_idx + 1, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id) || + reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx + 1, crtc_id)) continue; - pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; @@ -517,7 +520,7 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } - pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, enc_id); + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, crtc_id); if (pp_idx < 0) return -ENAVAIL; @@ -527,8 +530,8 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } - global_state->dsc_to_enc_id[dsc_idx] = enc_id; - global_state->dsc_to_enc_id[dsc_idx + 1] = enc_id; + global_state->dsc_to_crtc_id[dsc_idx] = crtc_id; + global_state->dsc_to_crtc_id[dsc_idx + 1] = crtc_id; num_dsc += 2; pp_idx++; /* start for next pair */ } @@ -544,11 +547,9 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, const struct msm_display_topology *top) { - uint32_t enc_id = enc->base.id; - if (!top->num_dsc || !top->num_intf) return 0; @@ -558,22 +559,22 @@ static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, * 2) DSC pair starts from even index, such as index(0,1), (2,3), etc * 3) even PINGPONG connects to even DSC * 4) odd PINGPONG connects to odd DSC - * 5) pair: encoder +--> pp_idx_0 --> dsc_idx_0 + * 5) pair: crtc +--> pp_idx_0 --> dsc_idx_0 * +--> pp_idx_1 --> dsc_idx_1 */ /* num_dsc should be either 1, 2 or 4 */ if (top->num_dsc > top->num_intf) /* merge mode */ - return _dpu_rm_dsc_alloc_pair(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc_pair(rm, global_state, crtc_id, top); else - return _dpu_rm_dsc_alloc(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc(rm, global_state, crtc_id, top); return 0; } static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc) + uint32_t crtc_id) { /* try allocating only one CDM block */ if (!rm->cdm_blk) { @@ -581,12 +582,12 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, return -EIO; } - if (global_state->cdm_to_enc_id) { + if (global_state->cdm_to_crtc_id) { DPU_ERROR("CDM_0 is already allocated\n"); return -EIO; } - global_state->cdm_to_enc_id = enc->base.id; + global_state->cdm_to_crtc_id = crtc_id; return 0; } @@ -594,30 +595,30 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, static int _dpu_rm_make_reservation( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, struct dpu_rm_requirements *reqs) { int ret; - ret = _dpu_rm_reserve_lms(rm, global_state, enc->base.id, reqs); + ret = _dpu_rm_reserve_lms(rm, global_state, crtc_id, reqs); if (ret) { DPU_ERROR("unable to find appropriate mixers\n"); return ret; } - ret = _dpu_rm_reserve_ctls(rm, global_state, enc->base.id, + ret = _dpu_rm_reserve_ctls(rm, global_state, crtc_id, &reqs->topology); if (ret) { DPU_ERROR("unable to find appropriate CTL\n"); return ret; } - ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology); + ret = _dpu_rm_reserve_dsc(rm, global_state, crtc_id, &reqs->topology); if (ret) return ret; if (reqs->topology.needs_cdm) { - ret = _dpu_rm_reserve_cdm(rm, global_state, enc); + ret = _dpu_rm_reserve_cdm(rm, global_state, crtc_id); if (ret) { DPU_ERROR("unable to find CDM blk\n"); return ret; @@ -628,7 +629,7 @@ static int _dpu_rm_make_reservation( } static int _dpu_rm_populate_requirements( - struct drm_encoder *enc, + struct drm_crtc *crtc, struct dpu_rm_requirements *reqs, struct msm_display_topology req_topology) { @@ -642,66 +643,59 @@ static int _dpu_rm_populate_requirements( } static void _dpu_rm_clear_mapping(uint32_t *res_mapping, int cnt, - uint32_t enc_id) + uint32_t crtc_id) { int i; for (i = 0; i < cnt; i++) { - if (res_mapping[i] == enc_id) + if (res_mapping[i] == crtc_id) res_mapping[i] = 0; } } void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc) + struct drm_crtc *crtc) { - _dpu_rm_clear_mapping(global_state->pingpong_to_enc_id, - ARRAY_SIZE(global_state->pingpong_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->mixer_to_enc_id, - ARRAY_SIZE(global_state->mixer_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->ctl_to_enc_id, - ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, - ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dspp_to_enc_id, - ARRAY_SIZE(global_state->dspp_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(&global_state->cdm_to_enc_id, 1, enc->base.id); + uint32_t crtc_id = crtc->base.id; + + _dpu_rm_clear_mapping(global_state->pingpong_to_crtc_id, + ARRAY_SIZE(global_state->pingpong_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->mixer_to_crtc_id, + ARRAY_SIZE(global_state->mixer_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->ctl_to_crtc_id, + ARRAY_SIZE(global_state->ctl_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dsc_to_crtc_id, + ARRAY_SIZE(global_state->dsc_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dspp_to_crtc_id, + ARRAY_SIZE(global_state->dspp_to_crtc_id), crtc_id); } int dpu_rm_reserve( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology topology) { struct dpu_rm_requirements reqs; int ret; - /* Check if this is just a page-flip */ - if (!drm_atomic_crtc_needs_modeset(crtc_state)) - return 0; - if (IS_ERR(global_state)) { DPU_ERROR("failed to global state\n"); return PTR_ERR(global_state); } - DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n", - enc->base.id, crtc_state->crtc->base.id); + DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc->base.id); - ret = _dpu_rm_populate_requirements(enc, &reqs, topology); + ret = _dpu_rm_populate_requirements(crtc, &reqs, topology); if (ret) { DPU_ERROR("failed to populate hw requirements\n"); return ret; } - ret = _dpu_rm_make_reservation(rm, global_state, enc, &reqs); + ret = _dpu_rm_make_reservation(rm, global_state, crtc->base.id, &reqs); if (ret) DPU_ERROR("failed to reserve hw resources: %d\n", ret); - - return ret; } @@ -798,42 +792,43 @@ static char *dpu_hw_blk_type_name[] = { }; int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) { + uint32_t crtc_id = crtc->base.id; struct dpu_hw_blk **hw_blks; - uint32_t *hw_to_enc_id; + uint32_t *hw_to_crtc_id; int i, num_blks, max_blks; switch (type) { case DPU_HW_BLK_PINGPONG: hw_blks = rm->pingpong_blks; - hw_to_enc_id = global_state->pingpong_to_enc_id; + hw_to_crtc_id = global_state->pingpong_to_crtc_id; max_blks = ARRAY_SIZE(rm->pingpong_blks); break; case DPU_HW_BLK_LM: hw_blks = rm->mixer_blks; - hw_to_enc_id = global_state->mixer_to_enc_id; + hw_to_crtc_id = global_state->mixer_to_crtc_id; max_blks = ARRAY_SIZE(rm->mixer_blks); break; case DPU_HW_BLK_CTL: hw_blks = rm->ctl_blks; - hw_to_enc_id = global_state->ctl_to_enc_id; + hw_to_crtc_id = global_state->ctl_to_crtc_id; max_blks = ARRAY_SIZE(rm->ctl_blks); break; case DPU_HW_BLK_DSPP: hw_blks = rm->dspp_blks; - hw_to_enc_id = global_state->dspp_to_enc_id; + hw_to_crtc_id = global_state->dspp_to_crtc_id; max_blks = ARRAY_SIZE(rm->dspp_blks); break; case DPU_HW_BLK_DSC: hw_blks = rm->dsc_blks; - hw_to_enc_id = global_state->dsc_to_enc_id; + hw_to_crtc_id = global_state->dsc_to_crtc_id; max_blks = ARRAY_SIZE(rm->dsc_blks); break; case DPU_HW_BLK_CDM: hw_blks = &rm->cdm_blk; - hw_to_enc_id = &global_state->cdm_to_enc_id; + hw_to_crtc_id = &global_state->cdm_to_crtc_id; max_blks = 1; break; default: @@ -843,17 +838,17 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, num_blks = 0; for (i = 0; i < max_blks; i++) { - if (hw_to_enc_id[i] != enc_id) + if (hw_to_crtc_id[i] != crtc_id) continue; if (num_blks == blks_size) { - DPU_ERROR("More than %d %s assigned to enc %d\n", - blks_size, dpu_hw_blk_type_name[type], enc_id); + DPU_ERROR("More than %d resources assigned to crtc %d\n", + blks_size, crtc_id); break; } if (!hw_blks[i]) { - DPU_ERROR("%s unavailable to assign to enc %d\n", - dpu_hw_blk_type_name[type], enc_id); + DPU_ERROR("%s unavailable to assign to crtc %d\n", + dpu_hw_blk_type_name[type], crtc_id); break; } blks[num_blks++] = hw_blks[i]; @@ -883,38 +878,38 @@ void dpu_rm_print_state(struct drm_printer *p, drm_puts(p, "resource mapping:\n"); drm_puts(p, "\tpingpong="); - for (i = 0; i < ARRAY_SIZE(global_state->pingpong_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->pingpong_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->pingpong_blks[i], - global_state->pingpong_to_enc_id[i]); + global_state->pingpong_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tmixer="); - for (i = 0; i < ARRAY_SIZE(global_state->mixer_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->mixer_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->mixer_blks[i], - global_state->mixer_to_enc_id[i]); + global_state->mixer_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tctl="); - for (i = 0; i < ARRAY_SIZE(global_state->ctl_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->ctl_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->ctl_blks[i], - global_state->ctl_to_enc_id[i]); + global_state->ctl_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tdspp="); - for (i = 0; i < ARRAY_SIZE(global_state->dspp_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->dspp_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dspp_blks[i], - global_state->dspp_to_enc_id[i]); + global_state->dspp_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tdsc="); - for (i = 0; i < ARRAY_SIZE(global_state->dsc_to_enc_id); i++) + for (i = 0; i < ARRAY_SIZE(global_state->dsc_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dsc_blks[i], - global_state->dsc_to_enc_id[i]); + global_state->dsc_to_crtc_id[i]); drm_puts(p, "\n"); drm_puts(p, "\tcdm="); dpu_rm_print_state_helper(p, rm->cdm_blk, - global_state->cdm_to_enc_id); + global_state->cdm_to_crtc_id); drm_puts(p, "\n"); drm_puts(p, "\tsspp="); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index c51c5a9255ce6..720e2c64effbf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -68,26 +68,25 @@ int dpu_rm_init(struct drm_device *dev, * HW blocks can then be accessed through dpu_rm_get_* functions. * HW Reservations should be released via dpu_rm_release_hw. * @rm: DPU Resource Manager handle - * @drm_enc: DRM Encoder handle - * @crtc_state: Proposed Atomic DRM CRTC State handle + * @crtc: DRM CRTC handle * @topology: Pointer to topology info for the display * @Return: 0 on Success otherwise -ERROR */ -int dpu_rm_reserve(struct dpu_rm *rm, +int dpu_rm_reserve( + struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *drm_enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology topology); /** - * dpu_rm_reserve - Given the encoder for the display chain, release any + * dpu_rm_reserve - Given the crtc for the display chain, release any * HW blocks previously reserved for that use case. * @rm: DPU Resource Manager handle - * @enc: DRM Encoder handle + * @crtc: DRM CRTC handle * @Return: 0 on Success otherwise -ERROR */ void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc); + struct drm_crtc *crtc); /** * dpu_rm_reserve_sspp - Reserve the required SSPP for the provided CRTC @@ -111,10 +110,10 @@ void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, struct drm_crtc *crtc); /** - * Get hw resources of the given type that are assigned to this encoder. + * Get hw resources of the given type that are assigned to this crtc. */ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); /** From patchwork Wed Oct 9 08:50:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D321DCED630 for ; Wed, 9 Oct 2024 08:50:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CAF010E69F; Wed, 9 Oct 2024 08:50:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ai0/yfjW"; dkim-atps=neutral Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE42710E6A1 for ; Wed, 9 Oct 2024 08:50:50 +0000 (UTC) Received: by mail-pg1-f177.google.com with SMTP id 41be03b00d2f7-7db54269325so5410441a12.2 for ; Wed, 09 Oct 2024 01:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463850; x=1729068650; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IJDRx4c02GV86ldvKHRV1BWPMQm206AuMFT5TG5pzZk=; b=ai0/yfjWd0VDmQvQo+6sNHieLFhDR2bBvpqLwH77sDD1+PThX3QmxfabNf3rKL44y7 hfUiShxoYnsWPJFHA0+9wF/7aPeOcSw0oVC4hWP5aH6adQFtYlo71237Hu+q/ce7Is/U NLcmLFCV84Ks9wlbMmTRjxxzDO7s1p1hWsBVsLVq1flAht7eu48Nkfgx6edJyjuyg/wA VVIZ05zH3jxZdaM6y7BKhtTR/ifeHVxQikyZZ+uWY4JS/EO2WlpjvBtrZFCxv8lh7gYw azDqyITiAF2JELRwi9J+3Gxz9eS9jxzedOdgc5+DaVq5H6WP5/8bChx3vD6XaT+QQxgB zDpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463850; x=1729068650; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJDRx4c02GV86ldvKHRV1BWPMQm206AuMFT5TG5pzZk=; b=g5EDKCfPRs8v+vc6v87JH2+f9Is3zyskwn8W9TOf03xixZ9c8e36mW0uy1LRCfeVTN rqJacVN8AHiffhksn8TkfW+t2A4+rHXUWVobzPTtPcbcb5ZpUzvX5LvuMFQNozW0PA2p k9jSU8pwe/RYJ1tNKuH+BAbGSk9mrFupYIO61fkk+RcTuv/jBff6go2fitJrTKXVO4b5 KgAuM/Iq1h16+Op0MBFb0wkq0LhIo3z1rBKELFeSKSgF06v+Ar9fFKJVE+F5I62IiJjv Vl2F8c0IjWr4AN1QSSutGJu/EPXULSvO5MkiKwW/5EIohqIF1pYVewVvWuD5GbNF+Mo9 9hpQ== X-Forwarded-Encrypted: i=1; AJvYcCXUzhKihwm9ORUdwOVckFuw2V7UlKWXJrXUg1O97r+OWhF0r7P55/rpR2xGjDfAEPRr7q6vXLVVyJ0=@lists.freedesktop.org X-Gm-Message-State: AOJu0YxWOr+YkitK3E3oTn1F7YSrt1sLglopcpi1k0XQtuFA+mpjpze0 FDtAXRbjP6AMeHRka460fh8uIJts+YRreZzcbMp6rREh2jBMZR/Q9X45MDHWh18= X-Google-Smtp-Source: AGHT+IF+L9jruoxAxge2I9Ue+gETiz0ghYX4QgsAWI8h/xKj1ECDICKwUX5gMAamzfVQ4Q+dxnHnXA== X-Received: by 2002:a17:90a:348c:b0:2e2:af04:8b64 with SMTP id 98e67ed59e1d1-2e2af048bb1mr1177331a91.7.1728463850333; Wed, 09 Oct 2024 01:50:50 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:50 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:18 +0800 Subject: [PATCH v2 05/14] drm/msm/dpu: handle pipes as array MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-5-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=18729; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=opSjxUTcPLTf/RJF/yohmnhWqOovHSpTlisf/okttJs=; b=GJVfYJ44MnX9Zte1yJNawKCyG2T7ZoiGDT+QdS1St4HAN9VNcf3Rcs+olwHjbskGfePd+1axT Q08J7fKuc/DC4n5CxRyPbDpJXOkB1HmcIl4X3Ev1lrIMHPIFmS9/UIT X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Store pipes in array with removing dedicated r_pipe. There are 2 pipes in a drm plane at most currently. While 4 pipes are needed for new usage case. This change generalize the handling to pipe pair and ease handling to another pipe pair later. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 34 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 167 ++++++++++++++++-------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +- 4 files changed, 111 insertions(+), 112 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 3e0e6e9757da5..9656b1df0f122 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -411,7 +411,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), state, to_dpu_plane_state(state), stage_idx, - format->pixel_format, + format->pixel_format, pipe, modifier); DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n", @@ -442,7 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, const struct msm_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; - uint32_t lm_idx; + uint32_t lm_idx, i; bool bg_alpha_enable = false; DECLARE_BITMAP(fetch_active, SSPP_MAX); @@ -463,20 +463,15 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; - set_bit(pstate->pipe.sspp->idx, fetch_active); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe, 0, stage_cfg); - - if (pstate->r_pipe.sspp) { - set_bit(pstate->r_pipe.sspp->idx, fetch_active); + for (i = 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + set_bit(pstate->pipe[i].sspp->idx, fetch_active); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, format, fb ? fb->modifier : 0, - &pstate->r_pipe, 1, stage_cfg); + &pstate->pipe[i], i, stage_cfg); } /* blend config update */ @@ -1387,15 +1382,12 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); - seq_printf(s, "\tsspp[0]:%s\n", - pstate->pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n", - pstate->pipe.multirect_mode, pstate->pipe.multirect_index); - if (pstate->r_pipe.sspp) { - seq_printf(s, "\tsspp[1]:%s\n", - pstate->r_pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n", - pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index); + if (pstate->pipe[i].sspp) { + seq_printf(s, "\tsspp[%d]:%s\n", + i, pstate->pipe[i].sspp->cap->name); + seq_printf(s, "\tmultirect[%d]: mode: %d index: %d\n", + i, pstate->pipe[i].multirect_mode, + pstate->pipe[i].multirect_index); } seq_puts(s, "\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 4df7cfed4d230..e7006fb8c7734 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -429,7 +429,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, unsigned int rotation) { - uint32_t i; + int i; bool inline_rotation = rotation & DRM_MODE_ROTATE_90; /* @@ -619,6 +619,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu, struct msm_drm_private *priv = plane->dev->dev_private; struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); + int i; DPU_DEBUG_PLANE(pdpu, "\n"); @@ -632,12 +633,12 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu, return; /* update sspp */ - _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, - fill_color, fmt); - - if (pstate->r_pipe.sspp) - _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, - fill_color, fmt); + for (i = 0; i < PIPES_PER_STAGE; i++) { + if (pstate->pipe[i].sspp) + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], + &pstate->pipe_cfg[i].dst_rect, + fill_color, fmt); + } } static int dpu_plane_prepare_fb(struct drm_plane *plane, @@ -808,8 +809,8 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; struct drm_rect fb_rect = { 0 }; uint32_t max_linewidth; @@ -834,6 +835,9 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, return -EINVAL; } + /* move the assignment here, to ease handling to another pairs later */ + pipe_cfg = &pstate->pipe_cfg[0]; + r_pipe_cfg = &pstate->pipe_cfg[1]; /* state->src is 16.16, src_rect is not */ drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); @@ -916,11 +920,11 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe = &pstate->pipe; - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; const struct msm_format *fmt; - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe = &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; uint32_t supported_rotations; const struct dpu_sspp_cfg *pipe_hw_caps; const struct dpu_sspp_sub_blks *sblk; @@ -975,10 +979,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe = &pstate->pipe; - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe = &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; const struct drm_crtc_state *crtc_state = NULL; if (new_plane_state->crtc) @@ -1056,7 +1060,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, drm_atomic_get_old_plane_state(state, plane); struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); struct drm_crtc_state *crtc_state; - int ret; + int ret, i; if (plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, @@ -1071,8 +1075,8 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - pstate->pipe.sspp = NULL; - pstate->r_pipe.sspp = NULL; + for (i = 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp = NULL; return 0; } @@ -1110,19 +1114,22 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; uint32_t max_linewidth; + int i; if (plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc); pstate = to_dpu_plane_state(plane_state); - pipe = &pstate->pipe; - r_pipe = &pstate->r_pipe; - pipe_cfg = &pstate->pipe_cfg; - r_pipe_cfg = &pstate->r_pipe_cfg; - pipe->sspp = NULL; - r_pipe->sspp = NULL; + /* loop below code for another pair later */ + pipe = &pstate->pipe[0]; + r_pipe = &pstate->pipe[1]; + pipe_cfg = &pstate->pipe_cfg[0]; + r_pipe_cfg = &pstate->pipe_cfg[1]; + + for (i = 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp = NULL; if (!plane_state->fb) return -EINVAL; @@ -1228,6 +1235,7 @@ void dpu_plane_flush(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; + int i; if (!plane || !plane->state) { DPU_ERROR("invalid plane\n"); @@ -1248,8 +1256,8 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - dpu_plane_flush_csc(pdpu, &pstate->pipe); - dpu_plane_flush_csc(pdpu, &pstate->r_pipe); + for (i = 0; i < PIPES_PER_STAGE; i++) + dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } /* flag h/w flush complete */ @@ -1349,20 +1357,16 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) struct dpu_plane *pdpu = to_dpu_plane(plane); struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); - struct dpu_sw_pipe *pipe = &pstate->pipe; - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; struct drm_crtc *crtc = state->crtc; struct drm_framebuffer *fb = state->fb; bool is_rt_pipe; const struct msm_format *fmt = msm_framebuffer_format(fb); - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); struct msm_gem_address_space *aspace = kms->base.aspace; struct dpu_hw_fmt_layout layout; bool layout_valid = false; - int ret; + int ret, i; ret = dpu_format_populate_layout(aspace, fb, &layout); if (ret) @@ -1381,12 +1385,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) crtc->base.id, DRM_RECT_ARG(&state->dst), &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); - dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, - drm_mode_vrefresh(&crtc->mode), - layout_valid ? &layout : NULL); - - if (r_pipe->sspp) { - dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, + /* move the assignment here, to ease handling to another pairs later */ + for (i = 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], + &pstate->pipe_cfg[i], fmt, drm_mode_vrefresh(&crtc->mode), layout_valid ? &layout : NULL); } @@ -1394,15 +1398,17 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) if (pstate->needs_qos_remap) pstate->needs_qos_remap = false; - pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, - &crtc->mode, pipe_cfg); - - pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); - - if (r_pipe->sspp) { - pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); + pstate->plane_fetch_bw = 0; + pstate->plane_clk = 0; + for (i = 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, + &crtc->mode, &pstate->pipe_cfg[i]); - pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); + pstate->plane_clk = max(pstate->plane_clk, + _dpu_plane_calc_clk(&crtc->mode, + &pstate->pipe_cfg[i])); } } @@ -1410,17 +1416,24 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane) { struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + struct dpu_sw_pipe *pipe; + int i; + + for (i = 0; i < PIPES_PER_STAGE; i += 1) { + pipe = &pstate->pipe[i]; + if (!pipe->sspp) + continue; - trace_dpu_plane_disable(DRMID(plane), false, - pstate->pipe.multirect_mode); + trace_dpu_plane_disable(DRMID(plane), false, + pstate->pipe[i].multirect_mode); - if (r_pipe->sspp) { - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + if (pipe->sspp && pipe->multirect_index == DPU_SSPP_RECT_1) { + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - if (r_pipe->sspp->ops.setup_multirect) - r_pipe->sspp->ops.setup_multirect(r_pipe); + if (pipe->sspp->ops.setup_multirect) + pipe->sspp->ops.setup_multirect(pipe); + } } pstate->pending = true; @@ -1515,30 +1528,26 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, const struct drm_plane_state *state) { const struct dpu_plane_state *pstate = to_dpu_plane_state(state); - const struct dpu_sw_pipe *pipe = &pstate->pipe; - const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; - const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; - const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; + const struct dpu_sw_pipe *pipe; + const struct dpu_sw_pipe_cfg *pipe_cfg; + int i; drm_printf(p, "\tstage=%d\n", pstate->stage); - if (pipe->sspp) { - drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[0]=%s\n", + for (i = 0; i < PIPES_PER_STAGE; i++) { + pipe = &pstate->pipe[i]; + if (!pipe->sspp) + continue; + pipe_cfg = &pstate->pipe_cfg[i]; + drm_printf(p, "\tsspp[%d]=%s\n", i, pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[%d]=%s\n", i, + dpu_get_multirect_mode(pipe->multirect_mode)); + drm_printf(p, "\tmultirect_index[%d]=%s\n", i, dpu_get_multirect_index(pipe->multirect_index)); - drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); - drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); - } - - if (r_pipe->sspp) { - drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[1]=%s\n", - dpu_get_multirect_mode(r_pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[1]=%s\n", - dpu_get_multirect_index(r_pipe->multirect_index)); - drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); - drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); + drm_printf(p, "\tsrc[%d]=" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->src_rect)); + drm_printf(p, "\tdst[%d]=" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->dst_rect)); } } @@ -1576,14 +1585,16 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); + int i; if (!pdpu->is_rt_pipe) return; pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); - if (pstate->r_pipe.sspp) - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); + for (i = 0; i < PIPES_PER_STAGE; i++) { + if (pstate->pipe[i].sspp) + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index e225d5baceb09..39945e0d1b851 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -18,10 +18,8 @@ * struct dpu_plane_state: Define dpu extension of drm plane state object * @base: base drm plane state object * @aspace: pointer to address space for input/output buffers - * @pipe: software pipe description - * @r_pipe: software pipe description of the second pipe - * @pipe_cfg: software pipe configuration - * @r_pipe_cfg: software pipe configuration for the second pipe + * @pipe: software pipe description array + * @pipe_cfg: software pipe configuration array * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -34,10 +32,8 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; - struct dpu_sw_pipe pipe; - struct dpu_sw_pipe r_pipe; - struct dpu_sw_pipe_cfg pipe_cfg; - struct dpu_sw_pipe_cfg r_pipe_cfg; + struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; enum dpu_stage stage; bool needs_qos_remap; bool pending; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 5307cbc2007c5..cb24ad2a6d8d3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -651,9 +651,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, TP_PROTO(uint32_t crtc_id, uint32_t plane_id, struct drm_plane_state *state, struct dpu_plane_state *pstate, uint32_t stage_idx, uint32_t pixel_format, - uint64_t modifier), + struct dpu_sw_pipe *pipe, uint64_t modifier), TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, - pixel_format, modifier), + pixel_format, pipe, modifier), TP_STRUCT__entry( __field( uint32_t, crtc_id ) __field( uint32_t, plane_id ) @@ -676,9 +676,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, __entry->dst_rect = drm_plane_state_dest(state); __entry->stage_idx = stage_idx; __entry->stage = pstate->stage; - __entry->sspp = pstate->pipe.sspp->idx; - __entry->multirect_idx = pstate->pipe.multirect_index; - __entry->multirect_mode = pstate->pipe.multirect_mode; + __entry->sspp = pipe->sspp->idx; + __entry->multirect_idx = pipe->multirect_index; + __entry->multirect_mode = pipe->multirect_mode; __entry->pixel_format = pixel_format; __entry->modifier = modifier; ), From patchwork Wed Oct 9 08:50:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDBE3CED62A for ; Wed, 9 Oct 2024 08:50:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5639E10E6A2; Wed, 9 Oct 2024 08:50:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="C9H37VrJ"; dkim-atps=neutral Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) by gabe.freedesktop.org (Postfix) with ESMTPS id E56C510E69C for ; Wed, 9 Oct 2024 08:50:56 +0000 (UTC) Received: by mail-pj1-f51.google.com with SMTP id 98e67ed59e1d1-2e18856feb4so5569469a91.3 for ; Wed, 09 Oct 2024 01:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463856; x=1729068656; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cVj8AtzhXJ6vFkOcgklF/XoM8iIzrnBxQKfkQbnsapY=; b=C9H37VrJE0ZW9jjdU1HsgjO44XQ7fZLulghOvtoM67HbpGiw5yd7sgltk3MBywAEKp pT6HYwhav9D1H6Q+Vj7HY38t6zv+B0PFL7+En5Gm1Vq640E5Xn5oEFnfRNARFOhss0Dw AYRo4n6iSwMhhtxqBuYN+fdi82jv7SAEjvZQyEeB2Z5rzOi8ZdUR6BGlFJDBLEnSqf4R FtemhnUzHeDQSawMTROdJodqZ7D7VPV+Yp+MzFhS0Piop80D/ellD69pShEaB3U6L6X2 4Znbui4Z/eJuMp/L8D1RhEMtDvsKOsZFA+LvzaEjaQNAvosH7QvWsbYU6xxnoi/mjMhR eQ4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463856; x=1729068656; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cVj8AtzhXJ6vFkOcgklF/XoM8iIzrnBxQKfkQbnsapY=; b=GjJHr0FOLJ1EhXP1CbhblnlK3b4UCvpc3XTxi0uJeEoBNQvFpOIJBrE3uwP3SShSuZ kInE1b15wolH5EmgwbIt2BYIidNE+E6KyPCdFowQ5jIry7E59UlmLgkCmPmZsTs6aVvt JqBVuIXAc8n1WCnFAXprEgRpzP4sVx+h6vtcjavPIdpgtQvyaS3z3wE1frYhsp9LrkRP P3S3x2u7NvqNmZEqEUzla0a+P7OsG3vO8N7yLidSS3LkpFCkKYvRg9XGhS4EH13unvEg dpATyC3UfMVMOQcJRIboSupOZ1jQ/uqrPLBLqly71JWgFqp0v00aNDu1YzlXand0d5me lDxw== X-Forwarded-Encrypted: i=1; AJvYcCVKcs/ZySNSYftqQcPgAeuSe3AspM2RrZdSumwKh6S5Hsfxp7fuF3v6D/i42tSDI8kXoxRTqMokp1A=@lists.freedesktop.org X-Gm-Message-State: AOJu0Yxs9mbFYt7DWTSilcFEyW00bpyynPAwozifxfKsdvAv5PAuLVbt s3QwU+xwzWApgX2yTnqY4OrAYxvRVO4UOJcDrslRIO+NM8ZqzxGBvypyMtv8Ojg= X-Google-Smtp-Source: AGHT+IEnEA+z9bRuIkWot3brQ2ilEwLd/yjDCjTrK0Iel1blGAiCM+EGqb8DDhJHM9w7m1IUfCusbw== X-Received: by 2002:a17:90a:3f87:b0:2d9:dd4a:6a95 with SMTP id 98e67ed59e1d1-2e2a2525ff5mr2151987a91.25.1728463856505; Wed, 09 Oct 2024 01:50:56 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:56 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:19 +0800 Subject: [PATCH v2 06/14] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-6-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=6669; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=ovrZzR71sqoQXwvbNAWE38q7w2iPdZWZ4+becN2ufi8=; b=ZM+3VwG25eltKqRvgmaKTxC2WylhQoCWcvNm0tMhI8u/6sa+5cYA1ch23F9Upi+dT/uH8cxvV Xh905twqT3zDZgwes1P+TA6CI7BFNj3W3PU6iL0pAQHFcYeH8sngfM8 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Split PIPES_PER_STAGE definition per plane and mixer pair. Because there are more than 2 pipes in quad pipe case, while 2 pipes at most per mixer pair. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 ++-- 6 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 9656b1df0f122..43d9817cd858f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -463,7 +463,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_LM_PAIR; i++) { if (!pstate->pipe[i].sspp) continue; set_bit(pstate->pipe[i].sspp->idx, fetch_active); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 602dfad127c2a..2e38f4db00c1e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -493,7 +493,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, if (test_bit(DPU_MIXER_SOURCESPLIT, &ctx->mixer_hw_caps->features)) - pipes_per_stage = PIPES_PER_STAGE; + pipes_per_stage = PIPES_PER_LM_PAIR; else pipes_per_stage = 1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 557ec9a924f81..e6e169094462f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -28,9 +28,9 @@ struct dpu_hw_ctl; * @multirect_index: index of the rectangle of SSPP. */ struct dpu_hw_stage_cfg { - enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; + enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_LM_PAIR]; enum dpu_sspp_multirect_index multirect_index - [DPU_STAGE_MAX][PIPES_PER_STAGE]; + [DPU_STAGE_MAX][PIPES_PER_LM_PAIR]; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index a2eff36a2224c..3277debe11689 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -32,7 +32,8 @@ #define DPU_MAX_PLANES 4 #endif -#define PIPES_PER_STAGE 2 +#define PIPES_PER_PLANE 2 +#define PIPES_PER_LM_PAIR 2 #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index e7006fb8c7734..9a8fbeec2e1e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -633,7 +633,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu, return; /* update sspp */ - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_PLANE; i++) { if (pstate->pipe[i].sspp) _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], &pstate->pipe_cfg[i].dst_rect, @@ -1075,7 +1075,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - for (i = 0; i < PIPES_PER_STAGE; i++) + for (i = 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp = NULL; return 0; @@ -1128,7 +1128,7 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, pipe_cfg = &pstate->pipe_cfg[0]; r_pipe_cfg = &pstate->pipe_cfg[1]; - for (i = 0; i < PIPES_PER_STAGE; i++) + for (i = 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp = NULL; if (!plane_state->fb) @@ -1256,7 +1256,7 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - for (i = 0; i < PIPES_PER_STAGE; i++) + for (i = 0; i < PIPES_PER_PLANE; i++) dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } @@ -1386,7 +1386,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); /* move the assignment here, to ease handling to another pairs later */ - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], @@ -1400,7 +1400,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) pstate->plane_fetch_bw = 0; pstate->plane_clk = 0; - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, @@ -1419,7 +1419,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane) struct dpu_sw_pipe *pipe; int i; - for (i = 0; i < PIPES_PER_STAGE; i += 1) { + for (i = 0; i < PIPES_PER_PLANE; i += 1) { pipe = &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1534,7 +1534,7 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, drm_printf(p, "\tstage=%d\n", pstate->stage); - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_PLANE; i++) { pipe = &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1591,7 +1591,7 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) return; pm_runtime_get_sync(&dpu_kms->pdev->dev); - for (i = 0; i < PIPES_PER_STAGE; i++) { + for (i = 0; i < PIPES_PER_PLANE; i++) { if (pstate->pipe[i].sspp) _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 39945e0d1b851..5c1b3775dce55 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -32,8 +32,8 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; - struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; - struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; + struct dpu_sw_pipe pipe[PIPES_PER_PLANE]; + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE]; enum dpu_stage stage; bool needs_qos_remap; bool pending; From patchwork Wed Oct 9 08:50:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 146E3CED62A for ; Wed, 9 Oct 2024 08:51:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 808C010E6A1; Wed, 9 Oct 2024 08:51:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="eg8IQ6F5"; dkim-atps=neutral Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by gabe.freedesktop.org (Postfix) with ESMTPS id 082C110E6A1 for ; Wed, 9 Oct 2024 08:51:02 +0000 (UTC) Received: by mail-pg1-f169.google.com with SMTP id 41be03b00d2f7-7db238d07b3so5577766a12.2 for ; Wed, 09 Oct 2024 01:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463861; x=1729068661; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1LPn0pitWd582eaxpygCPJ3KnkuQTc8TgGjrVLwJiU4=; b=eg8IQ6F5w07XTBSkiytCLKLzJZpbfxX/A67x6bO7Et/Kw7dgIEAGJF/19t1GoOyrZA 1EMLoCpX3XBgfMY/PQWwcueriJXtYW97Eonca1jqzXRZr3yxcdBctu4P4/vIew66QQ1k DavwTQyhUF5Rp/C0D9d92tYEV81hqAD5sI5TfTgNgh9rEziHHOcknQJ3mHBS3TaDr29l LiIdv8/5RiWetzOx4trn7uOLeCISXTBvD0TrWBRBMPI3XJ7HmmDyLhCO8fyYjJV8o1Cs 6M0M3cFsCyHBKoRvSWiqKu4SYemnEaAh/cuLNcSsMJC4SF1a19doFGCwNqbauXQvXemn +v0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463861; x=1729068661; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1LPn0pitWd582eaxpygCPJ3KnkuQTc8TgGjrVLwJiU4=; b=LUDUMbyhbHAruixvVdeIOot7wRluAdkhWDYSGi5afME1qaidY7EtOr8zA/EhuxvTXB kB3nXAS59ipSfKP7XubwLalfClDkEL27PGw7difec07XYK/OfR3D39C+a4avAz8TsBYa i5wZjSi97KR4VhndSRWI/8SXCVBhmrrzeIuswbBP//lXDkpUXj6usw2ThWRmC14b7gxF mbbs/JzNJXdIu8EM0hy72SxdZDasXcr7QYgEXT0W/+y5fCYta+7tf8axziQ2qILOwmqe Aq0ga2Vk+9rObAbpNN07jsAFw69tjX9HohpFYeOWMCGPR4N82VdQvqUnE1NjGzqbBNK0 TDkA== X-Forwarded-Encrypted: i=1; AJvYcCW+GuE/NIDTeUGBLT5VmozVeFwYP1YwquXqZ1tf6tJipJ7VFam+/m0N/AO17XsrQSGUuLHIkjTegPM=@lists.freedesktop.org X-Gm-Message-State: AOJu0YzgfQSEUD25aPrDH+J+5cH1ImwaliV9rL9S7FHCYFdt0eX4BB4A +pCC/VIQLa5Vu8ePrf9ArdvGmBcHMO6etDFtKkLmxhb85gKv8/ElrYj+CpG4ppg= X-Google-Smtp-Source: AGHT+IEuBbVEOzp/44KTvogO+2Pwv6ey+PCRNhpJDBXR48nTEps9zZhOE/C5TsBcWU49Kk9eDonz1w== X-Received: by 2002:a05:6a21:4006:b0:1d4:fd63:95bc with SMTP id adf61e73a8af0-1d8a3be149bmr3557677637.9.1728463861596; Wed, 09 Oct 2024 01:51:01 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:01 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:20 +0800 Subject: [PATCH v2 07/14] drm/msm/dpu: bind correct pingpong for quad pipe MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-7-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1834; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=9RRYODS3A2d0Z0V8KOVcb66YQ53zyJFTZeiR1EUXh1U=; b=zI/fFfLWAz2Rx1/Bo0e+EbbQoShERiEAOqxWMBxb+PzQbh3DuBOpjimccwD4p8gsYHq+UnPTf qnLp6+iodCIDPeqPBs96CqtOwscwnDXQLGLGX3o192BuKvN1lM195gy X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd interface to 3rd PP instead of the 2nd PP. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index bd2509985c4d0..dfe282c607933 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1100,7 +1100,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; - int num_lm, num_ctl, num_pp, num_dsc; + int num_lm, num_ctl, num_pp, num_dsc, num_pp_per_intf; unsigned int dsc_mask = 0; int i; @@ -1171,9 +1171,14 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, cstate->num_dscs = num_dsc; cstate->num_mixers = num_lm; - dpu_enc->connector = conn_state->connector; + /* + * There may be 4 PP and 2 INTF for quad pipe case, so INTF is not + * mapped to PP 1:1. Let's calculate the stride with pipe/INTF + */ + num_pp_per_intf = num_lm / dpu_enc->num_phys_encs; + for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; struct dpu_hw_ctl *ctl0 = to_dpu_hw_ctl(hw_ctl[0]); @@ -1195,7 +1200,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, return; } - phys->hw_pp = dpu_enc->hw_pp[i]; + phys->hw_pp = dpu_enc->hw_pp[num_pp_per_intf * i]; phys->cached_mode = crtc_state->adjusted_mode; if (phys->ops.atomic_mode_set) From patchwork Wed Oct 9 08:50:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CFE6CED62B for ; Wed, 9 Oct 2024 08:51:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF43D10E6A0; Wed, 9 Oct 2024 08:51:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="F5zXvJup"; dkim-atps=neutral Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) by gabe.freedesktop.org (Postfix) with ESMTPS id 93EA010E6A4 for ; Wed, 9 Oct 2024 08:51:07 +0000 (UTC) Received: by mail-pj1-f45.google.com with SMTP id 98e67ed59e1d1-2e28d7d44dbso1196083a91.2 for ; Wed, 09 Oct 2024 01:51:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463867; x=1729068667; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Xeuc89940OyZEzmfZGsShlcWun218secJztkD+/huVg=; b=F5zXvJupvZbVwXkjSSIqKwLPw3YFevOhIzf0m//A5NP2XoA6BVb36FA0m5m49eG20t BSnH8wIY071er8A6YLL5Zej82rKHW4G1VIQD+LxqGENvibVMxjlAwBudofGoSMyGDoUx VO4n/S5DycuA3V+6A66MpG8DLs3gcCTYUzTONrSxoRWZlRcR7NDDd2iVYV+P44eChYId y4XnXgvueRiSH0L/OBRCWTAl7kpmr3wNX1qoZ2iEQpZhKofOTSereDhKgtLz8KPfKqJQ ux4dtD2zu4sTZb/6AOv3iGFRgVzZjSN5PFCW151pq0aOQ9ZxZeesBerVl6sC5rzkbyiT wdhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463867; x=1729068667; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xeuc89940OyZEzmfZGsShlcWun218secJztkD+/huVg=; b=S+LJzJs970YQMyhwkoecToCgRJ8+Ws3u89FJgo/Tre9cQAy+N7r7DuBSIDKl9MvFsL k24BZ8lGldNlw3xdceLFWPS3Gz1KM7knFItHLZfe9ckhrfibF2fyI0EahV22adwKdv4j g1xID2D55ES3QMdlYdB0mmvuNbwVJ0gSi2tJ+YjqnXFzH5pOeqK1gufJKlspLbQpElow cvnMfZCwZqFJ93+ykDrhJTUAo4CcKIVsi7COhnhkzoj0mt90jSh3OVEms58zuow4Tzj1 dwvgauXUbL2SlQlgnIGUE/gRTF93/PgfUBh+awdpTN7igFWsiYqPHF7DA2X1XBPFiOtf TWPA== X-Forwarded-Encrypted: i=1; AJvYcCVzliUm5fN3f4nxh24GHvEOh99szfwLfMIavciTILY/gxe3qgdO38BNlstIT3AwDRlc43DuvQWQQwA=@lists.freedesktop.org X-Gm-Message-State: AOJu0YwduczCtpgaEFnCTzBui/srMccigsNtvtXWd+mM1RCQBe9HVgZZ Y1+12QLXKrZ3veWly81+4nzvDGubOpVik+i9nlg7taWtoygAzmvPeo76Jmy7AIw= X-Google-Smtp-Source: AGHT+IF0F7RtB5DS5euGqhy7U7rhzvEMjBeGrvubLOfvxfogUs8BIv6homsplq8ODB4C0o2n6DXgtQ== X-Received: by 2002:a17:90b:1104:b0:2e2:9522:279e with SMTP id 98e67ed59e1d1-2e2a25247e0mr2201199a91.31.1728463867148; Wed, 09 Oct 2024 01:51:07 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:06 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:21 +0800 Subject: [PATCH v2 08/14] drm/msm/dpu: update mixer number info earlier MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-8-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1729; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=zBBzWdWsfyqBIiT9wbwcVNQEKc8lnnOJ9lwiSkj7ngI=; b=olKDHeGrWWSragjDEGtR+qG7l03ad9g8wQu7Scz79ICx2dg8oxIEAOpVwrukiQ+/+oPfeExdI 7EvMgTVIa78DCYbucqzqXSwayrVfw07ZG1dzLBNsZo+LiJkdMYaFHoI X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Update mixer number info earlier so that the plane nopipe check can have the info to clip the plane. Otherwise, the first nonpipe check will have mixer number as 0 and plane is not checked. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index dfe282c607933..68655c8817bf8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -638,6 +638,7 @@ static int dpu_encoder_virt_atomic_check( struct dpu_global_state *global_state; struct drm_framebuffer *fb; struct drm_dsc_config *dsc; + struct dpu_crtc_state *cstate; int ret = 0; if (!drm_enc || !crtc_state || !conn_state) { @@ -662,6 +663,8 @@ static int dpu_encoder_virt_atomic_check( dsc = dpu_encoder_get_dsc_config(drm_enc); topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc); + cstate = to_dpu_crtc_state(crtc_state); + cstate->num_mixers = topology.num_lm; /* * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it. @@ -1170,7 +1173,13 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, } cstate->num_dscs = num_dsc; - cstate->num_mixers = num_lm; + if (cstate->num_mixers != num_lm) { + if (!cstate->num_mixers) + DPU_ERROR_ENC(dpu_enc, + "mixer number %d is not as expected %d\n", + num_lm, cstate->num_mixers); + cstate->num_mixers = num_lm; + } dpu_enc->connector = conn_state->connector; /* From patchwork Wed Oct 9 08:50:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59427CED62A for ; Wed, 9 Oct 2024 08:51:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C949C10E69E; Wed, 9 Oct 2024 08:51:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="c5FfxcAr"; dkim-atps=neutral Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) by gabe.freedesktop.org (Postfix) with ESMTPS id A9F8810E69E for ; Wed, 9 Oct 2024 08:51:13 +0000 (UTC) Received: by mail-pj1-f54.google.com with SMTP id 98e67ed59e1d1-2e109539aedso5474639a91.0 for ; Wed, 09 Oct 2024 01:51:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463873; x=1729068673; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lGPiijXBHhXZLgDLI4yCnvpkLyy91sdQEmrQWlXpxFs=; b=c5FfxcAr/3nLYOpBYXmiYcFSr6+ngse2GQWHPDZNLjnpPCBDsVkWXwbnPtnm34f+LH c2JLG53PasgsEDthL+I8qlC+Npy98jS4Y30MsEzmoVG2leWDQvbh8KduUlnzt2lqzCJh OsoMFcSwO//EEajjmbAdKgUjrKcvES9wTGijsv20Q/n+s/Lq27Of1uOjCJGGm0TTkumJ smaRph5uuP4jSWM2n5UVS4lgLBeihKqfedwFGBzpezZPCqiNaZA75yEFNNrGCyZ/kkTo ldKuvgmWy1nWqYekpFEzcQ29XFptf1vba3rmBwl/yMcMZBkV01eLePyAgircaCafdBQr 3SPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463873; x=1729068673; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lGPiijXBHhXZLgDLI4yCnvpkLyy91sdQEmrQWlXpxFs=; b=YL0nErZIfBqXXRnoyxm+3s/wsHdZL3jk2hiOJGGTDRAUW5/wD58nWyV1SVwT72UVLk EYFiK0nHmPRoegjQHvvgYjkqCG6KWneCZqheyyn1vNQ3Dc6Zh2+1XBUfYnQOzfmJAF+/ CMoF/rgR0pY+ni45f0E4gkLlp2eTrKg1ko1Kcx1KTOl/3rWDrugoHQC4jxKoF330Njct M3urUKkne0p47l78/0kCOV7YfeRZexUZQLm9jAN+SMgrgb+KqN2RBRuPE9SJb+9W3BpN CUfmCVrXLrsQ1f3kSWZgGpWTbGD17qGnp5C8jRpkrXAvAtytQ1+tBWT6TXZEoo5xo0wL kUtw== X-Forwarded-Encrypted: i=1; AJvYcCVLaJqqCC9Yy6n6RfnFBLdMli2XkS1LwqsLNBjL8Hn0UpwBVNsmbavPLzwgLafBvqK03fZABVzF+xw=@lists.freedesktop.org X-Gm-Message-State: AOJu0YwkDouZNI0k13pU9lq3bIhg6hscjv6XUFZ1rKTISQg/XEjjndkS 09CqpXcVn3RGgyDtI/j0oEeWkjFqWLSa2JowyLaeL7x3wwHIgTbJkSe6RMpAjG8= X-Google-Smtp-Source: AGHT+IHrjXqIDxYCqwvHmyuAo/2KaTwbzzxWXLOebacPfVE93Zx+pXmlthJkNcFwtHdZDvlnIGicew== X-Received: by 2002:a17:90b:4007:b0:2e0:970d:e37e with SMTP id 98e67ed59e1d1-2e2a246d989mr2280624a91.21.1728463873256; Wed, 09 Oct 2024 01:51:13 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:13 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:22 +0800 Subject: [PATCH v2 09/14] drm/msm/dpu: blend pipes per mixer pairs config MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-9-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=3761; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=vJuCxGkGWnTz/P7Gtny2/1VxQGiyRWGiMV+/Rk64D/Y=; b=1MAjd3Jvkinq6GMa/Z1lrF4XLcay/hBv+mExg+EKDZlBZS5b9WsUnciLcQv8VCirNsVEuE42e uUJS17Cr/0cCekZocENT5LBgQ/bZiJecz/rUoIPmrKAEUZGAwKJUYSi X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Blend pipes by set of mixer pair config. The first 2 pipes are for left half screen with the first set of mixer pair config. And the later 2 pipes are for right in quad pipe case. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 38 ++++++++++++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 43d9817cd858f..66f745399a602 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -442,7 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, const struct msm_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; - uint32_t lm_idx, i; + uint32_t lm_idx, lm_pair, i, pipe_idx; bool bg_alpha_enable = false; DECLARE_BITMAP(fetch_active, SSPP_MAX); @@ -463,15 +463,20 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; - for (i = 0; i < PIPES_PER_LM_PAIR; i++) { - if (!pstate->pipe[i].sspp) - continue; - set_bit(pstate->pipe[i].sspp->idx, fetch_active); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe[i], i, stage_cfg); + /* loop pipe per mixer pair */ + for (lm_pair = 0; lm_pair < PIPES_PER_PLANE / 2; lm_pair++) { + for (i = 0; i < PIPES_PER_LM_PAIR; i++) { + pipe_idx = i + lm_pair * PIPES_PER_LM_PAIR; + if (!pstate->pipe[pipe_idx].sspp) + continue; + set_bit(pstate->pipe[pipe_idx].sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + mixer, cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe[pipe_idx], i, + &stage_cfg[lm_pair]); + } } /* blend config update */ @@ -503,7 +508,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_crtc_mixer *mixer = cstate->mixers; struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; - struct dpu_hw_stage_cfg stage_cfg; + struct dpu_hw_stage_cfg stage_cfg[LM_PAIRS_PER_PLANE]; int i; DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); @@ -516,9 +521,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) } /* initialize stage cfg */ - memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(&stage_cfg, 0, sizeof(stage_cfg)); - _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); + _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg[0]); for (i = 0; i < cstate->num_mixers; i++) { ctl = mixer[i].lm_ctl; @@ -535,8 +540,13 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) mixer[i].mixer_op_mode, ctl->idx - CTL_0); + /* + * call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg. + * There is 4 mixers at most. The first 2 are for the left half, and + * the later 2 are for the right half. + */ ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &stage_cfg); + &stage_cfg[i / 2]); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index 3277debe11689..d8f5cffa60ea6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,6 +34,7 @@ #define PIPES_PER_PLANE 2 #define PIPES_PER_LM_PAIR 2 +#define LM_PAIRS_PER_PLANE 2 #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 #endif From patchwork Wed Oct 9 08:50:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 425EBCED62A for ; Wed, 9 Oct 2024 08:51:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE2E310E6A7; Wed, 9 Oct 2024 08:51:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="zXV0S3P5"; dkim-atps=neutral Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1F72710E6A7 for ; Wed, 9 Oct 2024 08:51:19 +0000 (UTC) Received: by mail-pj1-f41.google.com with SMTP id 98e67ed59e1d1-2e0946f9a8eso4536971a91.1 for ; Wed, 09 Oct 2024 01:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463879; x=1729068679; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vpK0k4xFfIit4zaSmhmserorxSb9ry7uxeuhNDC7oJA=; b=zXV0S3P5rJvbZZk5RkMuC6MUS8hb3uNFRwHqSh/OlEY+piycAASRJfBxhU26it2Ly4 9oIA8UVJKKoNkCAWm7c4pHenAAK8KGuWS1Ur1wKkmdWLNo54NWF2ZcTgtGSogyDwKjlb CX+/IVAs1ygFY63Urn8VBhC/m7iUuUFUmWa+s0PSUkjFoX3zlgQEHnpKjsSjVDdlPVc4 mvZsX5m70nc3y+CyhsGBEtbTPKuxXeCpi2rs3Mo9QTshK3qLdH4lx5fWBEp5Bpx6+SKY /ICoA62Da5GuYtZPXoQkZazQ+DAq7GPm/48qbW7v9A9Rg9CsKuGDlVq0q1Cd1k2Ut+sn YRqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463879; x=1729068679; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vpK0k4xFfIit4zaSmhmserorxSb9ry7uxeuhNDC7oJA=; b=NjEqPNXXnANdnKxLFXPdREI4xwK+kwxr51g+V9b5AM4Fsh9Lq/VMck9E3YY46iBJa9 FJgC6V47GzDtSugARnL673ajhR+U4FqrReEvs/GM5nnVqFvPLINZbFmmVP93YNxBx3Wu GF7riyiYvwOR5x7KVP9E1wy69TEisi17wQ4WMClzCs8sB6rJSxeGutYevONjWt85wX+v T2p5CAVLr5enRqtZdkKIH43dBF8+0BOJgXANwDb7tHlVsmLTuP7tuhm4ZNBdJNT8+Wz9 6BwSZX51ozRt9gnh9offXjDZBV2ODVH8oTPR2DKp2E0IHE5CSAiPKGyon50Ykz95aAqY HwcA== X-Forwarded-Encrypted: i=1; AJvYcCU+oDWqnn2ZwZbqi3+xqRUlDYylCTGFStAnNRw/D02S68QthyH5Yd3GQyynWvJY88Kwxv4wkQwO8mU=@lists.freedesktop.org X-Gm-Message-State: AOJu0YxcSnFhWt4eAGv/yI17xdx9S67PrUfbGM6CR43JQWvvBFS5L/w6 04Dn5YMDw/RD52qT+HYhS2p+6uuCckuMPqCzKgSFKrdvYHWCyX5/b6HsWQpKR1g= X-Google-Smtp-Source: AGHT+IHe9FbYiCWGUad9G8MFOgochWsO+40bvV7MWi4goN1+2gyN6VXnBwTao4ak546a2TWM8Yprwg== X-Received: by 2002:a17:90b:f8d:b0:2e2:af88:2b9f with SMTP id 98e67ed59e1d1-2e2af8834fdmr967039a91.16.1728463878553; Wed, 09 Oct 2024 01:51:18 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:18 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:23 +0800 Subject: [PATCH v2 10/14] drm/msm/dpu: Support quad-pipe in SSPP checking MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-10-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=5070; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=d6FA+M/FjBX/3MEHc7VsbcrNZioGkbL6iFmPiKpmDOA=; b=GNVGnJbpfVw6aGjlDgu20HadTv0FDiH386iH87aVQ269ay9VWGIcPUPm7SHKJB4uiQ11KNiLF T7UOMZoHl8eAHZEJA4fx/XjzPS7+1GXtF2sHMd/brCB8LNDdM/tLjds X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Move requreiment check to routine of every pipe check. Because there is multiple SSPPs for quad-pipe case in future. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 86 ++++++++++++++--------------- 2 files changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index fc54625ae5d4f..05b92ff7eb529 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -143,11 +143,13 @@ struct dpu_hw_pixel_ext { * such as decimation, flip etc to program this field * @dest_rect: destination ROI. * @rotation: simplified drm rotation hint + * @valid: notify that this pipe and config is in use */ struct dpu_sw_pipe_cfg { struct drm_rect src_rect; struct drm_rect dst_rect; unsigned int rotation; + bool valid; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 9a8fbeec2e1e8..904ebec1c8a18 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -739,12 +739,40 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg, - const struct msm_format *fmt, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + struct drm_plane_state *new_plane_state) { uint32_t min_src_size; struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); int ret; + const struct msm_format *fmt; + uint32_t supported_rotations; + const struct dpu_sspp_cfg *pipe_hw_caps; + const struct dpu_sspp_sub_blks *sblk; + + pipe_hw_caps = pipe->sspp->cap; + sblk = pipe->sspp->cap->sblk; + + /* + * We already have verified scaling against platform limitations. + * Now check if the SSPP supports scaling at all. + */ + if (!sblk->scaler_blk.len && + ((drm_rect_width(&new_plane_state->src) >> 16 != + drm_rect_width(&new_plane_state->dst)) || + (drm_rect_height(&new_plane_state->src) >> 16 != + drm_rect_height(&new_plane_state->dst)))) + return -ERANGE; + + fmt = msm_framebuffer_format(new_plane_state->fb); + + supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; + + if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) + supported_rotations |= DRM_MODE_ROTATE_90; + + pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation, + supported_rotations); min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; @@ -920,49 +948,19 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); - const struct msm_format *fmt; - struct dpu_sw_pipe *pipe = &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe = &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0]; - struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1]; - uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps; - const struct dpu_sspp_sub_blks *sblk; - int ret = 0; - - pipe_hw_caps = pipe->sspp->cap; - sblk = pipe->sspp->cap->sblk; - - /* - * We already have verified scaling against platform limitations. - * Now check if the SSPP supports scaling at all. - */ - if (!sblk->scaler_blk.len && - ((drm_rect_width(&new_plane_state->src) >> 16 != - drm_rect_width(&new_plane_state->dst)) || - (drm_rect_height(&new_plane_state->src) >> 16 != - drm_rect_height(&new_plane_state->dst)))) - return -ERANGE; - - fmt = msm_framebuffer_format(new_plane_state->fb); - - supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; - - if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) - supported_rotations |= DRM_MODE_ROTATE_90; - - pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation, - supported_rotations); - r_pipe_cfg->rotation = pipe_cfg->rotation; - - ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, - &crtc_state->adjusted_mode); - if (ret) - return ret; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe_cfg *pipe_cfg; + int ret = 0, i; - if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { - ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, - &crtc_state->adjusted_mode); + for (i = 0; i < PIPES_PER_PLANE; i++) { + pipe = &pstate->pipe[i]; + pipe_cfg = &pstate->pipe_cfg[i]; + if (!pipe_cfg->valid || !pipe->sspp) + break; + DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i); + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, + &crtc_state->adjusted_mode, + new_plane_state); if (ret) return ret; } From patchwork Wed Oct 9 08:50:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0AEC7CED62A for ; Wed, 9 Oct 2024 08:51:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A5A410E6A8; Wed, 9 Oct 2024 08:51:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UDFS6Uxx"; dkim-atps=neutral Received: from mail-pg1-f172.google.com (mail-pg1-f172.google.com [209.85.215.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id BEE2010E6AA for ; Wed, 9 Oct 2024 08:51:24 +0000 (UTC) Received: by mail-pg1-f172.google.com with SMTP id 41be03b00d2f7-7db90a28cf6so474956a12.0 for ; Wed, 09 Oct 2024 01:51:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463884; x=1729068684; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=F3RVtVtcWQ38kTkihMst8OMHNbsHVAelds2Db2o3IYo=; b=UDFS6UxxSSra0Vl4Odk46dIqoPlxhj8J1Tzy95Sc2loOEEzuo19pBMDD9aP+cKXrxL brKVbvw2rGjIqQHm/vi+KYvfOKLgDJOEy0bPV5N3+bCaIBm/2tJPd13ej5ZiyWstKS6o TxxBAC/KyUMRGj1yAOYmRDzvL4QJPXqN6SrRhWnfBjgPwWSpzvES8H5KLDj5XCXfiE2z qvMg7zHel4vwXL4rrlY3zxln0vpY3tssRVziANYUx8BdHSCH9TvCf7v6Vmaw7P1UZzf7 kSDErHsc4F4Zb3NS9X8clYX/ZH3BxCWhSB85/OkGELkD/BqdN6KdhSbPWflA52t/zCob a8Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463884; x=1729068684; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F3RVtVtcWQ38kTkihMst8OMHNbsHVAelds2Db2o3IYo=; b=EKCK7JuTWtymvg4ZDv6ThwvRHFoxgDG6BKXioFjl+lQabCBiAuPdsB5+OsF6yqhojx HoXvIU3myRjzokE6EEr+j+LJBe6np301vNUtx1/GdaBrutq1S+ipC3CR2QLURtfRtvIz AjUWjDLHUbhNN5pWqWmRMex+vzMtJFUpt1dmpCQhwczZ1fVUtUW+c1t++jwmtU6WRPnY NEjTzdOjG2acxoyztJMWuIleZRyyWgXcBQmAuFlOPFm7XENogtRvsk3PwbH8VApnWlY8 a+mFVbSbGAwjd5YTJDqxf956dut6Pq/u7BkjQOwVgwBPCaUH0F8LYSYB41/HgqpFjdW+ Dhng== X-Forwarded-Encrypted: i=1; AJvYcCXjH9rlxZw/bwl718kQyn1LLCcxMlkuJCeVLmGDDBeFN4mNCvuat/YKxxOG5C1TumdY5gnoxllpB1w=@lists.freedesktop.org X-Gm-Message-State: AOJu0YytjgcA9pGSuf16plESFnErqBcuiSasM17d94SX7KFu9fFAE136 +kVPmoSqCm3DpRhGUwP2WGqqvXLhbW3a1uQuetvWCoqfmtluuyderzU+1tleRjE= X-Google-Smtp-Source: AGHT+IHvpp82pkdvaPTIW66VfEKItG5LVqsQe3Zkoe6/T3/uxKCH9ZD03Stms/drz+eJxsVEGQyKiA== X-Received: by 2002:a17:90b:fd7:b0:2e2:91aa:e683 with SMTP id 98e67ed59e1d1-2e2a084ca8amr2758796a91.13.1728463884302; Wed, 09 Oct 2024 01:51:24 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:24 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:24 +0800 Subject: [PATCH v2 11/14] drm/msm/dpu: Share SSPP info for multi-rect case MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-11-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1040; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=GMo45gPySZjy72Hc4Yw7xEv8zW3cyCFzGsnKJn8DLoY=; b=S5CivVtMEYLewBJNoQ4eLfAA051Szb5Ae40kwyuCmurPDIxSr7oJL65CcW9kP+NnxKrfSzSw/ R6CxNMzFZddCCXWtYFQwLsGDsthBKAZQ35QcxpcHqcQtfuGd6WUQh18 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Share SSPP info for multi-rect case if virtual plane is not enabled. Otherwise, the 2nd half of DMA content is not displayed due to sspp pointer of r_pipe is null. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 904ebec1c8a18..898fc2937954e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1042,6 +1042,11 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, pipe->multirect_index = DPU_SSPP_RECT_0; pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + /* + * Signifies that r_pipe is to be used if the width of the 2nd + * pipe is not 0. This does not apply to virtual plane case. + */ + r_pipe->sspp = pipe->sspp; r_pipe->multirect_index = DPU_SSPP_RECT_1; r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; } From patchwork Wed Oct 9 08:50:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65570CED62A for ; Wed, 9 Oct 2024 08:51:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D0E3610E6AB; Wed, 9 Oct 2024 08:51:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="T3yvDKn5"; dkim-atps=neutral Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) by gabe.freedesktop.org (Postfix) with ESMTPS id 660C110E6AB for ; Wed, 9 Oct 2024 08:51:30 +0000 (UTC) Received: by mail-pj1-f48.google.com with SMTP id 98e67ed59e1d1-2e1c91fe739so4962768a91.2 for ; Wed, 09 Oct 2024 01:51:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463890; x=1729068690; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lBJlR6luuHJD2SBRXmS4TBrVXnItCuuwBx1jOrvel4A=; b=T3yvDKn5A0Yt+VQ7ZMFa1wnAniWeDOwetscLOTFHTo86uBcYJRvvuBw3ibFBYEaHv5 ioS9g3lv1PtKaoS/ZUGM8ftchPOC94254q+NzVq/BsiX+CD5uA82UxFSg54dcT0n2cUx Zc+w669DzGaN5E8sGXC3Ylm4MSJ7nVTVsjC66dQX4GI7vbInBiUt3LJwpVUWTUUVmvMU x08P1VWpCwRIOCRzblmfiOz3uCjGOsv4eoV3ZKnQKS/bqNSllYslPzqDA9klXE+Yxq/E f9RG3zP8xw3FhA2IlsIPg0e5t5C3Gq/PoHKoSP4jOiIUr6ERArIITGkm4FEJ/9Ck00No 4qnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463890; x=1729068690; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lBJlR6luuHJD2SBRXmS4TBrVXnItCuuwBx1jOrvel4A=; b=CrENkrQBElTLvywK4gg3iopoxQKc2/zvkFy8g3AiKcpJXGj2DVBrBMiuc/2kpqGJE2 UrcGVgUGZUPGF73roEJNmbi6hT0mYgvfwfKjOQtXybCAwKCnmnDbRZMNkgcOP+ad9hPw qQfDehtdQYD9378SH9fhR6mJrjBMmSWg8fJ56F1b3JnLjR2KAU7qq1CbAvlcKaLH2ovN GWkq/UpEeB6ynyXg90Z6Unv1GiIgHuvhFd2UkyaAIECUxT5K14BQC+ahj35GIiE59FS8 LikYW0OU9EmDiYy5fpsu58jHriJRJoZ8TOqWmD29xU8LYwYfpKmyOemXnvv3IcSwUzua M3dA== X-Forwarded-Encrypted: i=1; AJvYcCVXpUxfO/uqbtVhY3UTOF+r/rZGaK8OCTvl7GZDske1f3caFPaiPvVfXPmmCjpf95ahDx2OecB9OuU=@lists.freedesktop.org X-Gm-Message-State: AOJu0YxetMQx8MB6ezg6RD4j/2zPzd16oSnlnyTunO7edY1hUqghyMsQ u+6jsZ6Pa7yNEbP9MgeKZnezrnstF7OWycP/SpqvL6TfjTMwBRhJDBaVOVlWTOc= X-Google-Smtp-Source: AGHT+IG66GziAUmgiUUsi3KTQJBC4gAlqvuDR119PyWGN/Diu92dHzPdmdutFYrMKyP3/PNQiJlbkA== X-Received: by 2002:a17:90a:ce94:b0:2e2:7f8f:3ad7 with SMTP id 98e67ed59e1d1-2e2a21eeb54mr1854426a91.7.1728463889956; Wed, 09 Oct 2024 01:51:29 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:29 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:25 +0800 Subject: [PATCH v2 12/14] drm/msm/dpu: support plane splitting in quad-pipe case MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-12-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=7922; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=CZPvn+ixECCJlwEHRHraiyoiomUWWKsJjwFhygCQwTY=; b=EHUAFkbmU3QeX8NKH88pnLfL76SKXBm4B7CBY7a1Ly9PBgUR2iMfPx/8K+/9vtilcuHatv8Y+ JEN4cyXPL0WBGTTWsGHnXXvj5hBqCJvz6Olo107OIMCR07oRbbhEDWg X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Clip plane into pipes per left and right half screen ROI if topology is quad pipe. Then split the clipped rectangle by half if the rectangle width still exceeds width limit. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 99 ++++++++++++++++++++++--------- 3 files changed, 84 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 66f745399a602..d2aca0a9493d5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1310,6 +1310,13 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) return 0; } +unsigned int dpu_crtc_get_lm_num(const struct drm_crtc_state *state) +{ + struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); + + return cstate->num_mixers; +} + #ifdef CONFIG_DEBUG_FS static int _dpu_debugfs_status_show(struct seq_file *s, void *data) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 5260e2440f059..ee7cf71f89fc7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -304,4 +304,10 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_client_type( void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); +/** + * dpu_crtc_get_lm_num - Get mixer number in this CRTC pipeline + * state: Pointer to drm crtc state object + */ +unsigned int dpu_crtc_get_lm_num(const struct drm_crtc_state *state); + #endif /* _DPU_CRTC_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 898fc2937954e..480a1b46aba72 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -837,10 +837,12 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_sw_pipe_cfg pipe_cfg; struct drm_rect fb_rect = { 0 }; + const struct drm_display_mode *mode = &crtc_state->adjusted_mode; uint32_t max_linewidth; + u32 lm_num; + int lmcfg_id, lmcfg_num; min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); max_scale = MAX_DOWNSCALE_RATIO << 16; @@ -863,13 +865,10 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, return -EINVAL; } - /* move the assignment here, to ease handling to another pairs later */ - pipe_cfg = &pstate->pipe_cfg[0]; - r_pipe_cfg = &pstate->pipe_cfg[1]; - /* state->src is 16.16, src_rect is not */ - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + lm_num = dpu_crtc_get_lm_num(crtc_state); - pipe_cfg->dst_rect = new_plane_state->dst; + /* state->src is 16.16, src_rect is not */ + drm_rect_fp_to_int(&pipe_cfg.src_rect, &new_plane_state->src); fb_rect.x2 = new_plane_state->fb->width; fb_rect.y2 = new_plane_state->fb->height; @@ -884,34 +883,78 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, max_linewidth = pdpu->catalog->caps->max_linewidth; - drm_rect_rotate(&pipe_cfg->src_rect, + drm_rect_rotate(&pipe_cfg.src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || - _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; + /* + * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair + * configs for left and right half screen in case of 4:4:2 topology. + * But we may have 2 rect to split plane with 1 config for 2:2:1. + * So need to handle super wide plane splitting, and plane on right half + * for quad-pipe case. Check dest rectangle left/right clipping + * first, then check super wide rectangle splitting in every half next. + */ + lmcfg_num = (lm_num + 1) / 2; + /* iterate mixer configs for this plane, to separate left/right with the id */ + for (lmcfg_id = 0; lmcfg_id < lmcfg_num; lmcfg_id++) { + struct drm_rect mixer_rect = {lmcfg_id * mode->hdisplay / lmcfg_num, 0, + (lmcfg_id + 1) * mode->hdisplay / lmcfg_num, mode->vdisplay}; + int cfg_idx = lmcfg_id * PIPES_PER_LM_PAIR; + struct dpu_sw_pipe_cfg *cur_pipecfg = &pstate->pipe_cfg[cfg_idx]; + + drm_rect_fp_to_int(&cur_pipecfg->src_rect, &new_plane_state->src); + cur_pipecfg->dst_rect = new_plane_state->dst; + + DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT + " vs clip window " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&cur_pipecfg->src_rect), + DRM_RECT_ARG(&mixer_rect)); + + /* If this plane does not fall into mixer rect, check next mixer rect */ + if (!drm_rect_clip_scaled(&cur_pipecfg->src_rect, &cur_pipecfg->dst_rect, &mixer_rect)) { + memset(&pstate->pipe_cfg[cfg_idx], 0, 2 * sizeof(struct dpu_sw_pipe_cfg)); + memset(&pstate->pipe[cfg_idx], 0, 2 * sizeof(struct dpu_sw_pipe)); + continue; } - *r_pipe_cfg = *pipe_cfg; - pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; - pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; - r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; - r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; - } else { - memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); - } + cur_pipecfg->valid = true; + cur_pipecfg->dst_rect.x1 -= mixer_rect.x1; + cur_pipecfg->dst_rect.x2 -= mixer_rect.x1; + + DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&cur_pipecfg->src_rect), DRM_RECT_ARG(&cur_pipecfg->dst_rect)); + + /* Split super wide rect into 2 rect */ + if ((drm_rect_width(&cur_pipecfg->src_rect) > max_linewidth) || + _dpu_plane_calc_clk(mode, cur_pipecfg) > max_mdp_clk_rate) { + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[cfg_idx + 1]; + + if (drm_rect_width(&cur_pipecfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&cur_pipecfg->src_rect), max_linewidth); + return -E2BIG; + } + + memcpy(r_pipe_cfg, cur_pipecfg, sizeof(struct dpu_sw_pipe_cfg)); + cur_pipecfg->src_rect.x2 = (cur_pipecfg->src_rect.x1 + cur_pipecfg->src_rect.x2) >> 1; + cur_pipecfg->dst_rect.x2 = (cur_pipecfg->dst_rect.x1 + cur_pipecfg->dst_rect.x2) >> 1; + r_pipe_cfg->src_rect.x1 = cur_pipecfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 = cur_pipecfg->dst_rect.x2; + r_pipe_cfg->valid = true; + DPU_DEBUG_PLANE(pdpu, "Split super wide plane into:" + DRM_RECT_FMT " and " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&cur_pipecfg->src_rect), + DRM_RECT_ARG(&r_pipe_cfg->src_rect)); + } else { + memset(&pstate->pipe_cfg[cfg_idx + 1], 0, sizeof(struct dpu_sw_pipe_cfg)); + memset(&pstate->pipe[cfg_idx + 1], 0, sizeof(struct dpu_sw_pipe)); + } - drm_rect_rotate_inv(&pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + drm_rect_rotate_inv(&cur_pipecfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); + } pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); From patchwork Wed Oct 9 08:50:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12D16CED62B for ; Wed, 9 Oct 2024 08:51:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7EF1F10E6A4; Wed, 9 Oct 2024 08:51:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="bK8Cf/Sm"; dkim-atps=neutral Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTPS id A9EBF10E6A5 for ; Wed, 9 Oct 2024 08:51:35 +0000 (UTC) Received: by mail-pg1-f177.google.com with SMTP id 41be03b00d2f7-7c1324be8easo475496a12.1 for ; Wed, 09 Oct 2024 01:51:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463895; x=1729068695; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=J50cstReZOAStzssDowtSyHGuYNkBj/m3heNj/5l6AQ=; b=bK8Cf/Sm4HkajZQYq7FKt0SeFB6AOTZBNSmvnNj6lgm5M1AUbTaVAusuHPiuyg9ekN H7oaWzwzb/SDdNSDve9MXbGGQSJwXaez8qvFhAgIOzxfkuZywqMeFbxPkHJjQQteRZbS CeHn7H0XFOqtZK7NBsjsgqvXnRCbVcn4vrsD4uH7VGrVJrpfhV7ijib9k0SJiQlMheyl JcQ5PymbmygWb0cIqO0Z2i68sGsDU0XE/xAjbs3u6cAkVTkVXR/DbXXG+RjfQXdiYRz1 oHYVPWbVkSVlWA9FjQ0FFSeomJecGjQ9+q/ZCqJOtuW7tqcmjPl7C+pGKxSZtBbo+AYU aoWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463895; x=1729068695; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J50cstReZOAStzssDowtSyHGuYNkBj/m3heNj/5l6AQ=; b=bMJD73utEWumHEdA8e73lU98d+YnuK5tiq19S77z7/CgcCK8WCmJArX09pq+bsIhtb rBW/nlTR9XHG/XxmUBWl5RcGIabKHmohie+bB2fXQ1XinRdbjLtuHVR8tbntmskKE8qq v3iAnIozh4zjjf1v9FisXjqR3fZpoBdNQJo1g4sXPjNIQ109TBPIdTfYlO7w505rtGxc gn14OvsxdEqITgFxjsonv8MJvgg7gw052jltyWtTCJeqxRD6fR1MaxRWtL8ufDIHGLZC J7CwUvywQGkhxOZbtLd6gDJTZoy/s31VRfsaSNms56Mbs+6Qzj/shS7FOcA1v7aAcSsv 4k7g== X-Forwarded-Encrypted: i=1; AJvYcCWA/Dvp3NZEBatsi91gmU3tLdKwzn2UBNclwPSel9I3wixUL3A1J/hAWisKFU2XM3bPR9Yl69Rj0mg=@lists.freedesktop.org X-Gm-Message-State: AOJu0YzOXqoU438XcJqFy8t6N4f6SHiImWbvdjQs/1dcM/oB9SKKPhQs mE2yGcZx/AwlfcDoHClD/7YuO/Oug/T0oXm3jpZV3CYmv40QUHCWsVVRyTE6AMI= X-Google-Smtp-Source: AGHT+IGh9hWeUvEBQWoVINgVGvCvhY1wTX7fgeC/PcJue28p3V3B/iyUf2JTyGKo3OaTbJ8zsQLDwA== X-Received: by 2002:a17:90b:4c12:b0:2da:82d4:c63c with SMTP id 98e67ed59e1d1-2e27dd3c2c0mr9615183a91.4.1728463895250; Wed, 09 Oct 2024 01:51:35 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:34 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:26 +0800 Subject: [PATCH v2 13/14] drm/msm/dpu: support SSPP assignment for quad-pipe case MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-13-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=5496; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=81jK3N0j+q+DAMnsIs+UuOUU0xKWIcMiivwpFJMyey8=; b=T2DDlAeki79IVTctGUrvaj5XGACyxwdgxLwVCSDMiyi7MaCokffcNiEXMdg9z8ampm5Okjoid qYQVV0H1p1TBiQAtOoEekEoUnh5BEej73xKINai11HinJq+tccjEGZy X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Support SSPP assignment for quad-pipe case with unified method. The first 2 pipes can share a set of mixer config and enable multi-rect mode if condition is met. It is also the case for the later 2 pipes. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 85 +++++++++++++++---------------- 1 file changed, 42 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 480a1b46aba72..23de2ca6fabb0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -999,7 +999,7 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, pipe = &pstate->pipe[i]; pipe_cfg = &pstate->pipe_cfg[i]; if (!pipe_cfg->valid || !pipe->sspp) - break; + continue; DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i); ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, &crtc_state->adjusted_mode, @@ -1154,13 +1154,10 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); struct dpu_rm_sspp_requirements reqs; struct dpu_plane_state *pstate; - struct dpu_sw_pipe *pipe; - struct dpu_sw_pipe *r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_plane *pdpu = to_dpu_plane(plane); const struct msm_format *fmt; uint32_t max_linewidth; - int i; + int i, lm_num, lmcfg_id, lmcfg_num; if (plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, @@ -1168,12 +1165,6 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, pstate = to_dpu_plane_state(plane_state); - /* loop below code for another pair later */ - pipe = &pstate->pipe[0]; - r_pipe = &pstate->pipe[1]; - pipe_cfg = &pstate->pipe_cfg[0]; - r_pipe_cfg = &pstate->pipe_cfg[1]; - for (i = 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp = NULL; @@ -1189,41 +1180,49 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, max_linewidth = dpu_kms->catalog->caps->max_linewidth; - pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); - if (!pipe->sspp) - return -ENODEV; - - if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) { - pipe->multirect_index = DPU_SSPP_RECT_SOLO; - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - - r_pipe->sspp = NULL; - } else { - if (dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_linewidth) && - dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max_linewidth) && - (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || - test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) { - r_pipe->sspp = pipe->sspp; + lm_num = dpu_crtc_get_lm_num(crtc_state); + lmcfg_num = (lm_num + 1) / 2; + for (lmcfg_id = 0; lmcfg_id < lmcfg_num; lmcfg_id++) { + for (i = lmcfg_id * PIPES_PER_LM_PAIR; i < (lmcfg_id + 1) * PIPES_PER_LM_PAIR; i++) { + struct dpu_sw_pipe *pipe = &pstate->pipe[i]; + struct dpu_sw_pipe *r_pipe = &pstate->pipe[i + 1]; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[i]; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[i + 1]; - pipe->multirect_index = DPU_SSPP_RECT_0; - pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + if (!pipe_cfg->valid) + break; - r_pipe->multirect_index = DPU_SSPP_RECT_1; - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - } else { - /* multirect is not possible, use two SSPP blocks */ - r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); - if (!r_pipe->sspp) + pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); + if (!pipe->sspp) return -ENODEV; - pipe->multirect_index = DPU_SSPP_RECT_SOLO; - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + /* + * If current pipe is the first pipe in pipe pair, check + * multi-rect opportunity for the 2nd pipe in the pair. + * SSPP multi-rect mode cross mixer pairs is not supported. + */ + if (!(i % 2) && + r_pipe_cfg->valid && + drm_rect_width(&r_pipe_cfg->src_rect) != 0 && + dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_linewidth) && + dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max_linewidth) && + (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) { + pipe->multirect_index = DPU_SSPP_RECT_0; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + + DPU_DEBUG_PLANE(pdpu, "allocating sspp_%d for pipe %d and set pipe %d as multi-rect\n", + pipe->sspp->idx - SSPP_NONE, i, i + 1); + r_pipe->sspp = pipe->sspp; + r_pipe->multirect_index = DPU_SSPP_RECT_1; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + i++; + } else { + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + DPU_DEBUG_PLANE(pdpu, "allocating sspp_%d for pipe %d.\n", + pipe->sspp->idx - SSPP_NONE, i); + } } } From patchwork Wed Oct 9 08:50:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 13827906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F22E4CED628 for ; Wed, 9 Oct 2024 08:51:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 71C9410E6AC; Wed, 9 Oct 2024 08:51:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="nTGbmXFJ"; dkim-atps=neutral Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) by gabe.freedesktop.org (Postfix) with ESMTPS id 26F3710E6AC for ; Wed, 9 Oct 2024 08:51:41 +0000 (UTC) Received: by mail-pg1-f178.google.com with SMTP id 41be03b00d2f7-7e9f98f2147so2322628a12.1 for ; Wed, 09 Oct 2024 01:51:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463901; x=1729068701; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Pwqv1rhTGFasLdg0WvU6AXjOOGyCaNS4WyGtK80xkko=; b=nTGbmXFJkcBbpZFVZ/N/vqSDj2wW5cuB3n/ZLgtmLLQb2WM3UgEu4gmRvLA/JcLTWA JUrtNlPYNNlx8cvhojcRS0ASZDB72hJoRWPlG8KqjfHOrvaZhxEiWvng/G4G53GI/CEg cnNqDFL/2oYARfHU2cyLwW2E/3iBStFeaDVQSk77STz6wT9n/JsohXZtIR1ZWlQzfm1h nJDiFMZjXLQJdRoG3Uvp6IyLHX1xGOog4ZAgqFiRM1JOi4mlCCNSw0HLExZwr0L/RE/R dRRvJIsxgs73rQ3i667qkaTaKb4wOeeU35LhkJ5j9uNAFzuHC60FJpnKvAA5iwX/IlBb zERA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463901; x=1729068701; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Pwqv1rhTGFasLdg0WvU6AXjOOGyCaNS4WyGtK80xkko=; b=UNnyjkGKPbqWgA9vhth0zzJqweTgU7nLBQH07YXqbbH6/zRWVYgMqItzCzMmYMnk+r rRXHi/1yhpwW+WKAMd8F7kkgprK2nAuwaCA+X6lf7FlwwR6eZt6OeAEY9EyMYP92zuu3 9vQhQuLrkC0259oyGUAzNrQg48vvmWmAA3RGPo/CpWjcjBdj4FZWZ7cz6Rdo0sPtrzVN jDJoBAiafKulUFvMT4g9DnLjHXqDWwQBtDqyFT8MTVVg2V58s1TETL99mG69FhnnDeu8 iyfQAwi/cN/TPGKIXjPXF/5QzD5n2XLBSrpX1FHTJOcjmh2EnKpM+JXdE1JlI9WcWIlV ZOlg== X-Forwarded-Encrypted: i=1; AJvYcCUpfO6pKwftIpHvKUqPwi5JUxrp0j3BuK0yhFyzaGICMTazI1BZ66OShyStxA+arELIL/QnFi6vZQw=@lists.freedesktop.org X-Gm-Message-State: AOJu0YwzS53jXR+gCzM26scA7ZNLTYjz5m9mladsN/oNWhVtVH2GGtpc pHVFaPxvylBvQ0UDBiXtEQxK43l1Fle/ou9aE2sCzpQrc8jpxmg/qH4qNCf6yzA= X-Google-Smtp-Source: AGHT+IH/OP3QTgGjxIuKJ0oyytzwGzO6tFYp3oV193Ebfd756Hp2A4o+GBtu5EabM4fWhmuN+lSVgA== X-Received: by 2002:a17:90a:744a:b0:2dd:92e5:6f7d with SMTP id 98e67ed59e1d1-2e2a2471e84mr2313793a91.20.1728463900699; Wed, 09 Oct 2024 01:51:40 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:40 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:27 +0800 Subject: [PATCH v2 14/14] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case MIME-Version: 1.0 Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-14-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=6009; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=7+ZvIkQm3+KbgF5bXG62KdNVBcWEMmn0s/slfuucy/Q=; b=rgEs/g/vWs4Vpc3qv0Yve1dY4lYYjjpml8TIJBgX0vKvSOeV5royXLdUYsPS6UFPTrxwJBslz J2BLnZXAbGsBNs2tGlsVrNZkPkX5KG0DZyxhksp051co0lyg7Gn5H4C X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Request 4 mixers and 4 DSC for the case that both dual-DSI and DSC are enabled. We prefer to use 4 pipes for dual DSI case for it is power optimal for DSC. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 ++++++++++++++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +- 6 files changed, 30 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index d2aca0a9493d5..dbdfff1c7792a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, struct dpu_crtc_state *crtc_state) { struct dpu_crtc_mixer *m; - u32 crcs[CRTC_DUAL_MIXERS]; + u32 crcs[CRTC_QUAD_MIXERS]; int rc = 0; int i; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index ee7cf71f89fc7..f8276afd99192 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -211,7 +211,7 @@ struct dpu_crtc_state { bool bw_control; bool bw_split_vote; - struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; + struct drm_rect lm_bounds[CRTC_QUAD_MIXERS]; uint64_t input_fence_timeout_ns; @@ -219,10 +219,10 @@ struct dpu_crtc_state { /* HW Resources reserved for the crtc */ u32 num_mixers; - struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; + struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS]; u32 num_ctls; - struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; + struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS]; u32 num_dscs; enum dpu_crtc_crc_source crc_source; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 68655c8817bf8..ed220ac691e8a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -54,7 +54,7 @@ #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) -#define MAX_CHANNELS_PER_ENC 2 +#define MAX_CHANNELS_PER_ENC 4 #define IDLE_SHORT_TIMEOUT 1 @@ -588,15 +588,19 @@ static struct msm_display_topology dpu_encoder_get_topology( /* Datapath topology selection * - * Dual display + * Dual display without DSC * 2 LM, 2 INTF ( Split display using 2 interfaces) * + * Dual display with DSC + * 4 LM, 2 INTF ( Split display using 2 interfaces) + * * Single display * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * * Add dspps to the reservation requirements if ctm is requested */ + if (intf_count == 2) topology.num_lm = 2; else if (!dpu_kms->catalog->caps->has_3d_merge) @@ -615,10 +619,21 @@ static struct msm_display_topology dpu_encoder_get_topology( * 2 DSC encoders, 2 layer mixers and 1 interface * this is power optimal and can drive up to (including) 4k * screens + * But for dual display case, we prefer 4 layer mixers. Because + * the resolution is always high in the case and 4 DSCs are more + * power optimal. While a single SSPP can only co-work with one + * mixer pair. So 4 mixers are needed in this case. */ - topology.num_dsc = 2; - topology.num_lm = 2; - topology.num_intf = 1; + + if (intf_count == 2) { + topology.num_dsc = 4; + topology.num_lm = 4; + topology.num_intf = 2; + } else { + topology.num_dsc = 2; + topology.num_lm = 2; + topology.num_intf = 1; + } } return topology; @@ -2031,8 +2046,8 @@ static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc) struct dpu_hw_mixer_cfg mixer; int i, num_lm; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_lm[2]; - struct dpu_hw_mixer *hw_mixer[2]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC]; struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; memset(&mixer, 0, sizeof(mixer)); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index e77ebe3a68da9..c877ee45535ac 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -324,7 +324,8 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( /* Use merge_3d unless DSC MERGE topology is used */ if (phys_enc->split_role == ENC_ROLE_SOLO && - dpu_cstate->num_mixers == CRTC_DUAL_MIXERS && + (dpu_cstate->num_mixers == CRTC_DUAL_MIXERS || + dpu_cstate->num_mixers == CRTC_QUAD_MIXERS) && !dpu_encoder_use_dsc_merge(phys_enc->parent)) return BLEND_3D_H_ROW_INT; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index bf86d643887dd..f79ecd409a830 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -25,6 +25,7 @@ #define MAX_IMG_HEIGHT 0x3fff #define CRTC_DUAL_MIXERS 2 +#define CRTC_QUAD_MIXERS 4 #define MAX_XIN_COUNT 16 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index d8f5cffa60ea6..671e03406df74 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -32,9 +32,9 @@ #define DPU_MAX_PLANES 4 #endif -#define PIPES_PER_PLANE 2 #define PIPES_PER_LM_PAIR 2 #define LM_PAIRS_PER_PLANE 2 +#define PIPES_PER_PLANE (PIPES_PER_LM_PAIR * LM_PAIRS_PER_PLANE) #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 #endif